From patchwork Tue Nov 27 16:48:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrice Gasnier X-Patchwork-Id: 1003924 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=st.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 4348rD4Bwgz9s55 for ; Wed, 28 Nov 2018 03:49:00 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731367AbeK1DrV (ORCPT ); Tue, 27 Nov 2018 22:47:21 -0500 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:34967 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731264AbeK1DrU (ORCPT ); Tue, 27 Nov 2018 22:47:20 -0500 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id wARGhqGK025837; Tue, 27 Nov 2018 17:48:27 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2nxw02hfed-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 27 Nov 2018 17:48:27 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id B735433C; Tue, 27 Nov 2018 17:47:58 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag5node3.st.com [10.75.127.15]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 79632532D; Tue, 27 Nov 2018 16:48:26 +0000 (GMT) Received: from localhost (10.75.127.44) by SFHDAG5NODE3.st.com (10.75.127.15) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 27 Nov 2018 17:48:26 +0100 From: Fabrice Gasnier To: , , CC: , , , , , , , , Subject: [PATCH 1/3] dt-bindings: mfd: syscon: Add optional clock support Date: Tue, 27 Nov 2018 17:48:15 +0100 Message-ID: <1543337297-21873-2-git-send-email-fabrice.gasnier@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1543337297-21873-1-git-send-email-fabrice.gasnier@st.com> References: <1543337297-21873-1-git-send-email-fabrice.gasnier@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.44] X-ClientProxiedBy: SFHDAG6NODE2.st.com (10.75.127.17) To SFHDAG5NODE3.st.com (10.75.127.15) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-11-27_14:, , signatures=0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some system control registers need to be clocked, so the registers can be accessed. Add an optional clock. Signed-off-by: Fabrice Gasnier --- Documentation/devicetree/bindings/mfd/syscon.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.txt b/Documentation/devicetree/bindings/mfd/syscon.txt index 25d9e9c..a9aaa51 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.txt +++ b/Documentation/devicetree/bindings/mfd/syscon.txt @@ -17,6 +17,7 @@ Optional property: - reg-io-width: the size (in bytes) of the IO accesses that should be performed on the device. - hwlocks: reference to a phandle of a hardware spinlock provider node. +- clocks: phandle to the syscon clock Examples: gpr: iomuxc-gpr@20e0000 {