From patchwork Wed Nov 7 14:43:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 994306 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kontron.de Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=as-electronics.de header.i=@as-electronics.de header.b="XtbpgVZP"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42qqHr6MVrz9sDL for ; Thu, 8 Nov 2018 01:56:40 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727203AbeKHA0d (ORCPT ); Wed, 7 Nov 2018 19:26:33 -0500 Received: from mo4-p05-ob.smtp.rzone.de ([85.215.255.130]:15069 "EHLO mo4-p05-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728005AbeKHA0c (ORCPT ); Wed, 7 Nov 2018 19:26:32 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1541602547; s=strato-dkim-0002; d=as-electronics.de; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=L+2C2V6X05Jd6Z3JyhwcUJuCDtAzLwdUlTWG7X9XnDk=; b=XtbpgVZPqwdWVJpMpdt/48/ZmRpGd6bbk2bjtcN/pL0bwSafyxSyOU/+tJJ+KfVfjI espJy1abK5QzI5ysfmlRNG4W9CELzvzBfiEGs3sZ3dGvhB2LbFvaot69KgewuhWTk7m1 j7NBpkJFjLZEV6JXqN/lCpVbCtsMz9HOt5AnwVb5OHM1iGizEuAkTaZAkUtop1BKzWJk Rgmse/uiVO/4eBy0XUx/nWat1tddtpOJItYFrUmg8e8YaG2HU+ax1I07uEJ/l23q7tkr NDZPAhB71OsJ5CAohi6hL+YgeNc8k7k7ruBEaNFM7u+74cXrbfXUoJE13KZTo7idBSVd sGSw== X-RZG-AUTH: ":LX8JdEmkW/4tAFwMkcNJIloh1hrA5u3owhPk7bdT5Fx22AatU+eLaHfutoZdl+X9BETxn4/4+IVqx7ZdE8mPU5nMS5P2QgHAetWm5FNngAjmE0pFNjw=" X-RZG-CLASS-ID: mo05 Received: from fs-work.fritz.box by smtp.strato.de (RZmta 44.3 AUTH) with ESMTPSA id j097e4uA7Ei8UQl (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA (curve secp521r1 with 521 ECDH bits, eq. 15360 bits RSA)) (Client did not present a certificate); Wed, 7 Nov 2018 15:44:08 +0100 (CET) From: Frieder Schrempf To: linux-mtd@lists.infradead.org, boris.brezillon@bootlin.com, linux-spi@vger.kernel.org Cc: dwmw2@infradead.org, computersforpeace@gmail.com, marek.vasut@gmail.com, richard@nod.at, miquel.raynal@bootlin.com, broonie@kernel.org, david.wolfe@nxp.com, fabio.estevam@nxp.com, prabhakar.kushwaha@nxp.com, yogeshnarayan.gaur@nxp.com, han.xu@nxp.com, shawnguo@kernel.org, Frieder Schrempf , Rob Herring , Mark Rutland , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 02/10] dt-bindings: spi: Move the bindings for the FSL QSPI driver Date: Wed, 7 Nov 2018 15:43:19 +0100 Message-Id: <1541601809-16950-3-git-send-email-frieder.schrempf@kontron.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1541601809-16950-1-git-send-email-frieder.schrempf@kontron.de> References: <1541601809-16950-1-git-send-email-frieder.schrempf@kontron.de> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Frieder Schrempf Move the documentation of the old SPI NOR driver to the place of the new SPI memory interface based driver. Signed-off-by: Frieder Schrempf --- .../devicetree/bindings/mtd/fsl-quadspi.txt | 65 -------------------- .../devicetree/bindings/spi/spi-fsl-qspi.txt | 65 ++++++++++++++++++++ 2 files changed, 65 insertions(+), 65 deletions(-) diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt deleted file mode 100644 index 483e9cf..0000000 --- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt +++ /dev/null @@ -1,65 +0,0 @@ -* Freescale Quad Serial Peripheral Interface(QuadSPI) - -Required properties: - - compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi", - "fsl,imx7d-qspi", "fsl,imx6ul-qspi", - "fsl,ls1021a-qspi" - or - "fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi", - "fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi" - - reg : the first contains the register location and length, - the second contains the memory mapping address and length - - reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory" - - interrupts : Should contain the interrupt for the device - - clocks : The clocks needed by the QuadSPI controller - - clock-names : Should contain the name of the clocks: "qspi_en" and "qspi". - -Optional properties: - - fsl,qspi-has-second-chip: The controller has two buses, bus A and bus B. - Each bus can be connected with two NOR flashes. - Most of the time, each bus only has one NOR flash - connected, this is the default case. - But if there are two NOR flashes connected to the - bus, you should enable this property. - (Please check the board's schematic.) - - big-endian : That means the IP register is big endian - -Example: - -qspi0: quadspi@40044000 { - compatible = "fsl,vf610-qspi"; - reg = <0x40044000 0x1000>, <0x20000000 0x10000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_QSPI0_EN>, - <&clks VF610_CLK_QSPI0>; - clock-names = "qspi_en", "qspi"; - - flash0: s25fl128s@0 { - .... - }; -}; - -Example showing the usage of two SPI NOR devices: - -&qspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi2>; - status = "okay"; - - flash0: n25q256a@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q256a", "jedec,spi-nor"; - spi-max-frequency = <29000000>; - reg = <0>; - }; - - flash1: n25q256a@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q256a", "jedec,spi-nor"; - spi-max-frequency = <29000000>; - reg = <1>; - }; -}; diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt new file mode 100644 index 0000000..483e9cf --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt @@ -0,0 +1,65 @@ +* Freescale Quad Serial Peripheral Interface(QuadSPI) + +Required properties: + - compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi", + "fsl,imx7d-qspi", "fsl,imx6ul-qspi", + "fsl,ls1021a-qspi" + or + "fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi", + "fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi" + - reg : the first contains the register location and length, + the second contains the memory mapping address and length + - reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory" + - interrupts : Should contain the interrupt for the device + - clocks : The clocks needed by the QuadSPI controller + - clock-names : Should contain the name of the clocks: "qspi_en" and "qspi". + +Optional properties: + - fsl,qspi-has-second-chip: The controller has two buses, bus A and bus B. + Each bus can be connected with two NOR flashes. + Most of the time, each bus only has one NOR flash + connected, this is the default case. + But if there are two NOR flashes connected to the + bus, you should enable this property. + (Please check the board's schematic.) + - big-endian : That means the IP register is big endian + +Example: + +qspi0: quadspi@40044000 { + compatible = "fsl,vf610-qspi"; + reg = <0x40044000 0x1000>, <0x20000000 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_QSPI0_EN>, + <&clks VF610_CLK_QSPI0>; + clock-names = "qspi_en", "qspi"; + + flash0: s25fl128s@0 { + .... + }; +}; + +Example showing the usage of two SPI NOR devices: + +&qspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi2>; + status = "okay"; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + reg = <0>; + }; + + flash1: n25q256a@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + reg = <1>; + }; +}; From patchwork Wed Nov 7 14:43:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 994284 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kontron.de Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42qq256dXxz9s9h for ; Thu, 8 Nov 2018 01:44:45 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727203AbeKHAPX (ORCPT ); Wed, 7 Nov 2018 19:15:23 -0500 Received: from mo4-p05-ob.smtp.rzone.de ([85.215.255.133]:20269 "EHLO mo4-p05-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726635AbeKHAPW (ORCPT ); Wed, 7 Nov 2018 19:15:22 -0500 X-RZG-AUTH: ":LX8JdEmkW/4tAFwMkcNJIloh1hrA5u3owhPk7bdT5Fx22AatU+eLaHfutoZdl+X9BETxn4/4+IVqx7ZdE8mPU5nMS5P2QgHAetWm5FNngAjmE0pFNjw=" X-RZG-CLASS-ID: mo05 Received: from fs-work.fritz.box by smtp.strato.de (RZmta 44.3 AUTH) with ESMTPSA id j097e4uA7EiCUQm (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA (curve secp521r1 with 521 ECDH bits, eq. 15360 bits RSA)) (Client did not present a certificate); Wed, 7 Nov 2018 15:44:12 +0100 (CET) From: Frieder Schrempf To: linux-mtd@lists.infradead.org, boris.brezillon@bootlin.com, linux-spi@vger.kernel.org Cc: dwmw2@infradead.org, computersforpeace@gmail.com, marek.vasut@gmail.com, richard@nod.at, miquel.raynal@bootlin.com, broonie@kernel.org, david.wolfe@nxp.com, fabio.estevam@nxp.com, prabhakar.kushwaha@nxp.com, yogeshnarayan.gaur@nxp.com, han.xu@nxp.com, shawnguo@kernel.org, Frieder Schrempf , Rob Herring , Mark Rutland , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 03/10] dt-bindings: spi: Adjust the bindings for the FSL QSPI driver Date: Wed, 7 Nov 2018 15:43:20 +0100 Message-Id: <1541601809-16950-4-git-send-email-frieder.schrempf@kontron.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1541601809-16950-1-git-send-email-frieder.schrempf@kontron.de> References: <1541601809-16950-1-git-send-email-frieder.schrempf@kontron.de> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Frieder Schrempf Adjust the documentation of the new SPI memory interface based driver to reflect the new drivers settings. The "old" driver was using the "fsl,qspi-has-second-chip" property to select one of two dual chip setups (two chips on one bus or two chips on separate buses). And it used the order in which the subnodes are defined in the dt to select the CS, the chip is connected to. Both methods are wrong and in fact the "reg" property should be used to determine which bus and CS a chip is connected to. This also enables us to use different setups than just single chip, or symmetric dual chip. So the porting of the driver from the MTD to the SPI framework actually enforces the use of the "reg" properties and makes "fsl,qspi-has-second-chip" superfluous. As all boards that have "fsl,qspi-has-second-chip" set, also have correct "reg" properties, the removal of this property shouldn't lead to any incompatibilities. The only compatibility issues I can see are with imx6sx-sdb.dts and imx6sx-sdb-reva.dts, which have their reg properties set incorrectly (see explanation here: [2]), all other boards should stay compatible. Also the "big-endian" flag was removed, as this setting is now selected by the driver, depending on which SoC is in use. Signed-off-by: Frieder Schrempf --- .../devicetree/bindings/spi/spi-fsl-qspi.txt | 21 +++++++++----------- 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt index 483e9cf..6d7c9ec 100644 --- a/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt +++ b/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt @@ -3,9 +3,8 @@ Required properties: - compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi", "fsl,imx7d-qspi", "fsl,imx6ul-qspi", - "fsl,ls1021a-qspi" + "fsl,ls1021a-qspi", "fsl,ls2080a-qspi" or - "fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi", "fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi" - reg : the first contains the register location and length, the second contains the memory mapping address and length @@ -14,15 +13,13 @@ Required properties: - clocks : The clocks needed by the QuadSPI controller - clock-names : Should contain the name of the clocks: "qspi_en" and "qspi". -Optional properties: - - fsl,qspi-has-second-chip: The controller has two buses, bus A and bus B. - Each bus can be connected with two NOR flashes. - Most of the time, each bus only has one NOR flash - connected, this is the default case. - But if there are two NOR flashes connected to the - bus, you should enable this property. - (Please check the board's schematic.) - - big-endian : That means the IP register is big endian +Required SPI slave node properties: + - reg: There are two buses (A and B) with two chip selects each. + This encodes to which bus and CS the flash is connected: + <0>: Bus A, CS 0 + <1>: Bus A, CS 1 + <2>: Bus B, CS 0 + <3>: Bus B, CS 1 Example: @@ -40,7 +37,7 @@ qspi0: quadspi@40044000 { }; }; -Example showing the usage of two SPI NOR devices: +Example showing the usage of two SPI NOR devices on bus A: &qspi2 { pinctrl-names = "default";