From patchwork Tue Oct 30 19:30:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 991048 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=redhat.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42l1pv1jStz9sCN for ; Wed, 31 Oct 2018 06:33:25 +1100 (AEDT) Received: from localhost ([::1]:55143 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHZlS-0007ye-Ld for incoming@patchwork.ozlabs.org; Tue, 30 Oct 2018 15:33:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42665) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHZjn-0005dG-Bw for qemu-devel@nongnu.org; Tue, 30 Oct 2018 15:31:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gHZjd-0007wK-GN for qemu-devel@nongnu.org; Tue, 30 Oct 2018 15:31:34 -0400 Received: from mx1.redhat.com ([209.132.183.28]:58440) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gHZjP-0007pZ-TA; Tue, 30 Oct 2018 15:31:16 -0400 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id B0F46308A95D; Tue, 30 Oct 2018 19:31:14 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-205.brq.redhat.com [10.40.204.205]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 6F57C1057042; Tue, 30 Oct 2018 19:31:06 +0000 (UTC) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Peter Maydell , Guenter Roeck , "Edgar E. Iglesias" , Igor Mitsyanko , Alistair Francis Date: Tue, 30 Oct 2018 20:30:43 +0100 Message-Id: <20181030193044.25954-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.41]); Tue, 30 Oct 2018 19:31:15 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v3] arm: exynos4: Add dma support for smdkc210 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, Richard Henderson , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Guenter Roeck QEMU already supports pl330. Instantiate it for smdkc210. Relevant part of Linux arch/arm/boot/dts/exynos4.dtsi: / { soc: soc { amba { pdma0: pdma@12680000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12680000 0x1000>; interrupts = ; clocks = <&clock CLK_PDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <32>; }; pdma1: pdma@12690000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12690000 0x1000>; interrupts = ; clocks = <&clock CLK_PDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <32>; }; mdma1: mdma@12850000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12850000 0x1000>; interrupts = ; clocks = <&clock CLK_MDMA>; clock-names = "apb_pclk"; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <1>; }; }; }; }; Signed-off-by: Guenter Roeck Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis [PMD: Do not set default qdev properties, create the controllers in the SoC rather than the board (Peter Maydell), add dtsi in commit message] Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell --- Another intent to salvage previous work from Guenter Roeck: https://lists.gnu.org/archive/html/qemu-devel/2018-10/msg06302.html Since v2: https://lists.gnu.org/archive/html/qemu-devel/2018-10/msg06459.html - rename init -> create - create controllers in SoC rather than the board (Peter Maydell) - add Linux dtsi in commit message Since v1: https://lists.gnu.org/archive/html/qemu-devel/2018-10/msg06335.html - Do not factor out pl330_init, which resulted in buggy v1, see: https://lists.gnu.org/archive/html/qemu-devel/2018-10/msg06448.html hw/arm/exynos4210.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index 827318a003..cd27b9387c 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -96,6 +96,11 @@ /* EHCI */ #define EXYNOS4210_EHCI_BASE_ADDR 0x12580000 +/* DMA */ +#define EXYNOS4210_PL330_BASE0_ADDR 0x12680000 +#define EXYNOS4210_PL330_BASE1_ADDR 0x12690000 +#define EXYNOS4210_PL330_BASE2_ADDR 0x12850000 + static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43, 0x09, 0x00, 0x00, 0x00 }; @@ -160,6 +165,19 @@ static uint64_t exynos4210_calc_affinity(int cpu) return (0x9 << ARM_AFF1_SHIFT) | cpu; } +static void pl330_create(uint32_t base, qemu_irq irq, int nreq) +{ + SysBusDevice *busdev; + DeviceState *dev; + + dev = qdev_create(NULL, "pl330"); + qdev_prop_set_uint8(dev, "num_periph_req", nreq); + qdev_init_nofail(dev); + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, base); + sysbus_connect_irq(busdev, 0, irq); +} + Exynos4210State *exynos4210_init(MemoryRegion *system_mem) { Exynos4210State *s = g_new(Exynos4210State, 1); @@ -410,5 +428,13 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem) sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR, s->irq_table[exynos4210_get_irq(28, 3)]); + /*** DMA controllers ***/ + pl330_create(EXYNOS4210_PL330_BASE0_ADDR, + qemu_irq_invert(s->irq_table[exynos4210_get_irq(35, 1)]), 32); + pl330_create(EXYNOS4210_PL330_BASE1_ADDR, + qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32); + pl330_create(EXYNOS4210_PL330_BASE2_ADDR, + qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1); + return s; }