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Dong" To: "linux-arm-kernel@lists.infradead.org" Subject: [PATCH V2 5/8] ARM: imx: add initial support for imx7ulp Thread-Topic: [PATCH V2 5/8] ARM: imx: add initial support for imx7ulp Thread-Index: AQHUasZvrl43Zkhf+kGzjW4zG+S1sQ== Date: Tue, 23 Oct 2018 11:49:21 +0000 Message-ID: <1540295058-26090-6-git-send-email-aisheng.dong@nxp.com> References: <1540295058-26090-1-git-send-email-aisheng.dong@nxp.com> In-Reply-To: <1540295058-26090-1-git-send-email-aisheng.dong@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK0PR03CA0033.apcprd03.prod.outlook.com (2603:1096:203:2f::21) To AM0PR04MB4211.eurprd04.prod.outlook.com (2603:10a6:208:66::21) authentication-results: spf=none (sender IP is ) smtp.mailfrom=aisheng.dong@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.66] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM0PR04MB4404; 6:RU3sLdThNa48GaED2LpjoKNoM4JfZwlRbYs3AJeUimfe+HJFu6iSeqpWDFA1SUF4OQJmXBmNkyYICfKrzq8UPzS8sZIqwTigsDOQ59UyYP+4LJh6k6RJnvtG9czMPVueuJ+KARcmVwRip4FHJTA77l8rmSljvtN20D3/AQyp9Q2CDX8x48Lko7hhuo9DYtK/BPvzKyl8unK2dLV6vHvzsRGBCqaA+itAAsROZOB4iRDGKCHbXvzBFy4nXRx2yC+kNxwrRHQb7IyKh9PpWCdfM2VLFN/sCkgHPfQCiEF6mzedeF/MM2ZluToIlpXWeE2dNGSB0G6ZUXat07ZFO/UJZN1l1GJ+/3YOkPfJaF6ZUTQAxsMn+v3jx7EEymSsGdpTpMS03rPhGlyiCbN0bOwG8znBKcoNN5vZ1PXTlQXdaRuGEma4A7KqH+dgF9kBOoFSAtW5wNV+mCCDoVZcSTneqw==; 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Dong" , "dongas86@gmail.com" , "linux@armlinux.org.uk" , "robh+dt@kernel.org" , dl-linux-imx , "kernel@pengutronix.de" , Fabio Estevam , "shawnguo@kernel.org" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org The i.MX 7ULP family of processors represents NXP’s latest achievement in ultra-low-power processing for use cases demanding long battery life. Targeted towards the growing market of portable devices, the i.MX 7ULP family of processors features NXP's advanced implementation of the Arm® Cortex®-A7 core, the Arm Cortex-M4 core, as well as a 3D and 2D Graphics Processing Units (GPUs). The i.MX 7ULP family provides up to 32-bit LPDDR2/LPDDR3 memory interface and a number of other interfaces for connecting peripherals, such as WLAN, Bluetooth, GPS, displays, and camera sensors. This patch aims to add an initial support for imx7ulp. Note that we need configure power mode to Partial Stop mode 3 with system/bus clock enabled first as the default enabled STOP mode will gate off system/bus clock when execute WFI in MX7ULP SoC. And there's still no MXC_CPU_IMX7ULP IDs read from register as ULP has no anatop as before. So we encode one with 0xff in reverse order in case new ones will be in the future. Cc: Shawn Guo Signed-off-by: Dong Aisheng --- ChangeLog: v1->v2: * switch to SPDX license * more description of new SOC in commit message --- arch/arm/mach-imx/Kconfig | 9 +++++++++ arch/arm/mach-imx/Makefile | 1 + arch/arm/mach-imx/common.h | 1 + arch/arm/mach-imx/cpu.c | 3 +++ arch/arm/mach-imx/mach-imx7ulp.c | 32 ++++++++++++++++++++++++++++++++ arch/arm/mach-imx/mxc.h | 1 + arch/arm/mach-imx/pm-imx7ulp.c | 28 ++++++++++++++++++++++++++++ 7 files changed, 75 insertions(+) create mode 100644 arch/arm/mach-imx/mach-imx7ulp.c create mode 100644 arch/arm/mach-imx/pm-imx7ulp.c diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index abc3371..c12a05c 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -558,6 +558,15 @@ config SOC_IMX7D help This enables support for Freescale i.MX7 Dual processor. +config SOC_IMX7ULP + bool "i.MX7ULP support" + select ARM_GIC + select CLKSRC_IMX_TPM + select HAVE_ARM_ARCH_TIMER + select PINCTRL_IMX7ULP + help + This enables support for Freescale i.MX7 Ultra Low Power processor. + config SOC_VF610 bool "Vybrid Family VF610 support" select ARM_GIC if ARCH_MULTI_V7 diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index bae179a..8af2f7e 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -83,6 +83,7 @@ obj-$(CONFIG_SOC_IMX6SX) += mach-imx6sx.o obj-$(CONFIG_SOC_IMX6UL) += mach-imx6ul.o obj-$(CONFIG_SOC_IMX7D_CA7) += mach-imx7d.o obj-$(CONFIG_SOC_IMX7D_CM4) += mach-imx7d-cm4.o +obj-$(CONFIG_SOC_IMX7ULP) += mach-imx7ulp.o pm-imx7ulp.o ifeq ($(CONFIG_SUSPEND),y) AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 423dd76..bc915e5 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -120,6 +120,7 @@ void imx6dl_pm_init(void); void imx6sl_pm_init(void); void imx6sx_pm_init(void); void imx6ul_pm_init(void); +void imx7ulp_pm_init(void); #ifdef CONFIG_PM void imx51_pm_init(void); diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index c73593e..0b137ee 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -145,6 +145,9 @@ struct device * __init imx_soc_device_init(void) case MXC_CPU_IMX7D: soc_id = "i.MX7D"; break; + case MXC_CPU_IMX7ULP: + soc_id = "i.MX7ULP"; + break; default: soc_id = "Unknown"; } diff --git a/arch/arm/mach-imx/mach-imx7ulp.c b/arch/arm/mach-imx/mach-imx7ulp.c new file mode 100644 index 0000000..ad8be07 --- /dev/null +++ b/arch/arm/mach-imx/mach-imx7ulp.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * Author: Dong Aisheng + */ + +#include +#include +#include + +#include "common.h" +#include "hardware.h" + +static void __init imx7ulp_init_machine(void) +{ + imx7ulp_pm_init(); + + mxc_set_cpu_type(MXC_CPU_IMX7ULP); + imx_print_silicon_rev("i.MX7ULP", IMX_CHIP_REVISION_1_0); + of_platform_default_populate(NULL, NULL, imx_soc_device_init()); +} + +static const char *const imx7ulp_dt_compat[] __initconst = { + "fsl,imx7ulp", + NULL, +}; + +DT_MACHINE_START(IMX7ulp, "Freescale i.MX7ULP (Device Tree)") + .init_machine = imx7ulp_init_machine, + .dt_compat = imx7ulp_dt_compat, +MACHINE_END diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h index b130a53..8e72d4e 100644 --- a/arch/arm/mach-imx/mxc.h +++ b/arch/arm/mach-imx/mxc.h @@ -44,6 +44,7 @@ #define MXC_CPU_IMX6ULZ 0x6b #define MXC_CPU_IMX6SLL 0x67 #define MXC_CPU_IMX7D 0x72 +#define MXC_CPU_IMX7ULP 0xff #define IMX_DDR_TYPE_LPDDR2 1 diff --git a/arch/arm/mach-imx/pm-imx7ulp.c b/arch/arm/mach-imx/pm-imx7ulp.c new file mode 100644 index 0000000..9fb7da0 --- /dev/null +++ b/arch/arm/mach-imx/pm-imx7ulp.c @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * Author: Dong Aisheng + */ + +#include +#include +#include + +#define SMC_PMCTRL 0x10 +#define BP_PMCTRL_PSTOPO 16 +#define PSTOPO_PSTOP3 0x3 + +void __init imx7ulp_pm_init(void) +{ + struct device_node *np; + void __iomem *smc1_base; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-smc1"); + smc1_base = of_iomap(np, 0); + WARN_ON(!smc1_base); + + /* Partial Stop mode 3 with system/bus clock enabled */ + writel_relaxed(PSTOPO_PSTOP3 << BP_PMCTRL_PSTOPO, + smc1_base + SMC_PMCTRL); +} From patchwork Tue Oct 23 11:49:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aisheng Dong X-Patchwork-Id: 988182 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="HpieLfYI"; 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Dong" To: "linux-arm-kernel@lists.infradead.org" Subject: [PATCH V2 6/8] dts: imx: add common imx7ulp dtsi support Thread-Topic: [PATCH V2 6/8] dts: imx: add common imx7ulp dtsi support Thread-Index: AQHUasZy0umcS31uIkGUsUUWU6Vs+g== Date: Tue, 23 Oct 2018 11:49:25 +0000 Message-ID: <1540295058-26090-7-git-send-email-aisheng.dong@nxp.com> References: <1540295058-26090-1-git-send-email-aisheng.dong@nxp.com> In-Reply-To: <1540295058-26090-1-git-send-email-aisheng.dong@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK0PR03CA0033.apcprd03.prod.outlook.com (2603:1096:203:2f::21) To AM0PR04MB4211.eurprd04.prod.outlook.com (2603:10a6:208:66::21) authentication-results: spf=none (sender IP is ) smtp.mailfrom=aisheng.dong@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.66] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM0PR04MB4404; 6:aOp194FjUyjk+zp2Bc4k1axs0KYG23RRhEZxRMZH0jAwE2QtcuKlDF67y48mTLvOuA1PRmoEZV3wX8qe4CezQh9HAQvumI/VMucX4mCxo/3b5XZLUReHcVII1t5eusbXWK+NQLXZq8+aMR0GfUy7tJYKyB8nMoCqAWBbp1FVlSEsfsaEC003FV56On5s9UKILiaYNooA0Afly/Qb3/rvSUOXTZij4qwNMMBueUQoZJk8YxoQil/rtVn74KpQceVLhiJO9y8ARcpMI0muzeXecYXWYsCX6aEmSix5clQ9HptNkPB6+0+GiOnt7pqUqH0n2pbmeD9eXUpXms6gRvh3gHiybngxLiXmd6pohgC+5UW90b26M/TBfMiXhHGjdtI/pWUd2+GVTBpZTQSDE1BZjAPUcWCwAQ6g3jJWnSTXqWDkRFUCDzr9PbI2HHHAQkx/P3FQ3ZRTs5ygiygzmPzHkg==; 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Dong" , "devicetree@vger.kernel.org" , "dongas86@gmail.com" , "linux@armlinux.org.uk" , "robh+dt@kernel.org" , dl-linux-imx , "kernel@pengutronix.de" , Fabio Estevam , "shawnguo@kernel.org" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org The i.MX 7ULP family of processors represents NXP’s latest achievement in ultra-low-power processing for use cases demanding long battery life. Targeted towards the growing market of portable devices, the i.MX 7ULP family of processors features NXP's advanced implementation of the Arm® Cortex®-A7 core, the Arm Cortex-M4 core, as well as a 3D and 2D Graphics Processing Units (GPUs). This patch aims to add the initial support including: 1) CLK 2) GPIO PTC, PTD, PTE, PTF 3) uSDHC 1/2 4) LPUART 4/5/6/7 5) LPI2C 6/7 Cc: Rob Herring Cc: Shawn Guo Cc: devicetree@vger.kernel.org Cc: Sascha Hauer Cc: Fabio Estevam Signed-off-by: Dong Aisheng --- ChangeLog: v1->v2: * update clk part due to binding change * separate soc.dtsi from board.dts --- arch/arm/boot/dts/imx7ulp.dtsi | 323 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 323 insertions(+) create mode 100644 arch/arm/boot/dts/imx7ulp.dtsi diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi new file mode 100644 index 0000000..795edc2 --- /dev/null +++ b/arch/arm/boot/dts/imx7ulp.dtsi @@ -0,0 +1,323 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * Dong Aisheng + */ + +#include +#include +#include + +#include "imx7ulp-pinfunc.h" + +/ { + interrupt-parent = <&intc>; + + #address-cells = <1>; + #size-cells = <1>; + + aliases { + gpio0 = &gpio_ptc; + gpio1 = &gpio_ptd; + gpio2 = &gpio_pte; + gpio3 = &gpio_ptf; + i2c0 = &lpi2c6; + i2c1 = &lpi2c7; + mmc0 = &usdhc0; + mmc1 = &usdhc1; + serial0 = &lpuart4; + serial1 = &lpuart5; + serial2 = &lpuart6; + serial3 = &lpuart7; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + }; + }; + + intc: interrupt-controller@40021000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x40021000 0x1000>, + <0x40022000 0x1000>; + }; + + rosc: clock-rosc { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "rosc"; + #clock-cells = <0>; + }; + + sosc: clock-sosc { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "sosc"; + #clock-cells = <0>; + }; + + sirc: clock-sirc { + compatible = "fixed-clock"; + clock-frequency = <16000000>; + clock-output-names = "sirc"; + #clock-cells = <0>; + }; + + firc: clock-firc { + compatible = "fixed-clock"; + clock-frequency = <48000000>; + clock-output-names = "firc"; + #clock-cells = <0>; + }; + + upll: clock-upll { + compatible = "fixed-clock"; + clock-frequency = <480000000>; + clock-output-names = "upll"; + #clock-cells = <0>; + }; + + mpll: clock-mpll { + compatible = "fixed-clock"; + clock-frequency = <480000000>; + clock-output-names = "mpll"; + #clock-cells = <0>; + }; + + timer { + compatible = "arm,armv7-timer"; + arm,cpu-registers-not-fw-configured; + interrupts = , + ; + clock-frequency = <1000000>; + status = "disabled"; + }; + + ahbbridge0: bus@40000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40000000 0x800000>; + ranges; + + lpuart4: serial@402d0000 { + compatible = "fsl,imx7ulp-lpuart"; + reg = <0x402d0000 0x1000>; + interrupts = ; + clocks = <&pcc2 IMX7ULP_CLK_LPUART4>; + clock-names = "ipg"; + assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; + assigned-clock-rates = <24000000>; + status = "disabled"; + }; + + lpuart5: serial@402e0000 { + compatible = "fsl,imx7ulp-lpuart"; + reg = <0x402e0000 0x1000>; + interrupts = ; + clocks = <&pcc2 IMX7ULP_CLK_LPUART5>; + clock-names = "ipg"; + assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + tpm5: tpm@40260000 { + compatible = "fsl,imx7ulp-tpm"; + reg = <0x40260000 0x1000>; + interrupts = ; + clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, + <&pcc2 IMX7ULP_CLK_LPTPM5>; + clock-names = "ipg", "per"; + }; + + usdhc0: usdhc@40370000 { + compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc"; + reg = <0x40370000 0x10000>; + interrupts = ; + clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, + <&scg1 IMX7ULP_CLK_NIC1_DIV>, + <&pcc2 IMX7ULP_CLK_USDHC0>; + clock-names ="ipg", "ahb", "per"; + assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>; + bus-width = <4>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc1: usdhc@40380000 { + compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc"; + reg = <0x40380000 0x10000>; + interrupts = ; + clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, + <&scg1 IMX7ULP_CLK_NIC1_DIV>, + <&pcc2 IMX7ULP_CLK_USDHC1>; + clock-names ="ipg", "ahb", "per"; + assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC1>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>; + bus-width = <4>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + scg1: scg1@403e0000 { + compatible = "fsl,imx7ulp-scg1"; + reg = <0x403e0000 0x10000>; + clocks = <&rosc>, <&sosc>, <&sirc>, + <&firc>, <&upll>, <&mpll>; + clock-names = "rosc", "sosc", "sirc", + "firc", "upll", "mpll"; + #clock-cells = <1>; + }; + + pcc2: pcc2@403f0000 { + compatible = "fsl,imx7ulp-pcc2"; + reg = <0x403f0000 0x10000>; + #clock-cells = <1>; + assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; + }; + + smc1: smc1@40410000 { + compatible = "fsl,imx7ulp-smc1"; + reg = <0x40410000 0x1000>; + }; + + pcc3: pcc3@40b30000 { + compatible = "fsl,imx7ulp-pcc3"; + reg = <0x40b30000 0x10000>; + #clock-cells = <1>; + }; + }; + + ahbbridge1: bus@40800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40800000 0x800000>; + ranges; + + lpi2c6: lpi2c@40a40000 { + compatible = "fsl,imx7ulp-lpi2c"; + reg = <0x40a40000 0x10000>; + interrupts = ; + clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>; + clock-names = "ipg"; + assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpi2c7: lpi2c@40a50000 { + compatible = "fsl,imx7ulp-lpi2c"; + reg = <0x40a50000 0x10000>; + interrupts = ; + clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>; + clock-names = "ipg"; + assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpuart6: serial@40a60000 { + compatible = "fsl,imx7ulp-lpuart"; + reg = <0x40a60000 0x1000>; + interrupts = ; + clocks = <&pcc3 IMX7ULP_CLK_LPUART6>; + clock-names = "ipg"; + assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpuart7: serial@40a70000 { + compatible = "fsl,imx7ulp-lpuart"; + reg = <0x40a70000 0x1000>; + interrupts = ; + clocks = <&pcc3 IMX7ULP_CLK_LPUART7>; + clock-names = "ipg"; + assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + iomuxc1: iomuxc@40ac0000 { + compatible = "fsl,imx7ulp-iomuxc1"; + reg = <0x40ac0000 0x1000>; + }; + + gpio_ptc: gpio@40ae0000 { + compatible = "fsl,vf610-gpio"; + reg = <0x40ae0000 0x1000 0x400f0000 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, + <&pcc3 IMX7ULP_CLK_PCTLC>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc1 0 0 32>; + }; + + gpio_ptd: gpio@40af0000 { + compatible = "fsl,vf610-gpio"; + reg = <0x40af0000 0x1000 0x400f0040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, + <&pcc3 IMX7ULP_CLK_PCTLD>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc1 0 32 32>; + }; + + gpio_pte: gpio@40b00000 { + compatible = "fsl,vf610-gpio"; + reg = <0x40b00000 0x1000 0x400f0080 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, + <&pcc3 IMX7ULP_CLK_PCTLE>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc1 0 64 32>; + }; + + gpio_ptf: gpio@40b10000 { + compatible = "fsl,vf610-gpio"; + reg = <0x40b10000 0x1000 0x400f00c0 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, + <&pcc3 IMX7ULP_CLK_PCTLF>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc1 0 96 32>; + }; + }; +}; From patchwork Tue Oct 23 11:49:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aisheng Dong X-Patchwork-Id: 988188 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="rHZrDEBf"; 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Dong" To: "linux-arm-kernel@lists.infradead.org" Subject: [PATCH V2 7/8] dts: fsl: add imx7ulp evk support Thread-Topic: [PATCH V2 7/8] dts: fsl: add imx7ulp evk support Thread-Index: AQHUasZ0XlqnNuls/0irXYYkG2XyZQ== Date: Tue, 23 Oct 2018 11:49:29 +0000 Message-ID: <1540295058-26090-8-git-send-email-aisheng.dong@nxp.com> References: <1540295058-26090-1-git-send-email-aisheng.dong@nxp.com> In-Reply-To: <1540295058-26090-1-git-send-email-aisheng.dong@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK0PR03CA0033.apcprd03.prod.outlook.com (2603:1096:203:2f::21) To AM0PR04MB4211.eurprd04.prod.outlook.com (2603:10a6:208:66::21) authentication-results: spf=none (sender IP is ) smtp.mailfrom=aisheng.dong@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.66] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM0PR04MB4404; 6:AJKMv1F6pY9bBEMkzdmIxIdAvREPugaAGALmEgrNBmNc2KZsv/HDhXHsjY27KdnHfNthCWGcYDOLpz7a565107xAEkDd4DN27g6wLA6htPcpJYon6NW4ZS3LswnVUT5GwBjqxecb4CGjvv2rl18OnmUZ97QuTGKQzTOgbQ1iLW1+XS7MoqAGQ8K6Fu/oMjVXPuPQkcGmoYBNDSBfIE+wohycu3p0iGsRJx46RFHF1AzpukSzacDTeDeep3S7ROIhcZn6XhureGf3lZ9zXe7hr87jvKKUkGac2Tz7vr0k+uV27sqsObwUwtb2+ocsvltnzHBDJw+4TMYezj1LWVHxhgMTLkcZXCovVZilCnz7UJsu00HvHQyiqo4lWXsI1nP+vZJ8KVY9lUMfezRJTpi0NVCfhyykSHpQaAmO6hELzFchzhnCMkdFch50J4VGczm1SGiEl/kLRrawp7gEWf4v6A==; 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Dong" , "devicetree@vger.kernel.org" , "dongas86@gmail.com" , "linux@armlinux.org.uk" , "robh+dt@kernel.org" , dl-linux-imx , "kernel@pengutronix.de" , Fabio Estevam , "shawnguo@kernel.org" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org The NXP i.MX 7ULP Evaluation Kit (EVK) provides a platform for rapid evaluation of the i.MX 7ULP, which features NXP's advanced implementation of the Arm® Cortex®-A7 core, the Arm Cortex-M4 core, as well as a 3D and 2D Graphics Processing Units (GPUs). The EVK enables HDMI output for simple out-of-the-box to bring up but allows reconfiguration for MIPI displays. The EVK is designed as a System-On-Module(SOM) board that connects to an associated baseboard. The SOM provides 1 GB LPDDR3, 8 MB Quad SPI flash, Micro SD 3.0 card socket, WiFi/ Bluetooth capability, USB 2.0 OTG with Type C connector and an NXP PF1550 power management IC (PMIC). The baseboard provides additional capabilities including a full SD/MMC 3.0 card socket, audio codec, multiple sensors, an HDMI connector, and an alternate MIPI display connector. Additionally, the EVK facilitates software development with the ultimate goal of faster time to market through the support of both Linux® OS and AndroidTM rich operating systems, as well as FreeRTOS. This patch aims to support the preliminary booting up features as follows: GPIO LPUART FEC SD/MMC See more board details: https://www.nxp.com/products/processors-and-microcontrollers/ arm-based-processors-and-mcus/i.mx-applications-processors/ i.mx-7-processors/evaluation-kit-for-the-i.mx-7ulp-applications -processor:MCIMX7ULP-EVK Cc: Rob Herring Cc: Shawn Guo Cc: devicetree@vger.kernel.org Cc: Sascha Hauer Cc: Fabio Estevam Signed-off-by: Dong Aisheng --- ChangeLog: v1->v2: * switch to SPDX license * pad name update * fix Character '_' not recommended in node name * separate from soc.dtsi file --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx7ulp-evk.dts | 94 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 96 insertions(+) create mode 100644 arch/arm/boot/dts/imx7ulp-evk.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d7268ae..39eac9c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -573,6 +573,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-sdb-sht11.dtb \ imx7s-colibri-eval-v3.dtb \ imx7s-warp.dtb +dtb-$(CONFIG_SOC_IMX7ULP) += \ + imx7ulp-evk.dtb dtb-$(CONFIG_SOC_LS1021A) += \ ls1021a-moxa-uc-8410a.dtb \ ls1021a-qds.dtb \ diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/imx7ulp-evk.dts new file mode 100644 index 0000000..d876cb3 --- /dev/null +++ b/arch/arm/boot/dts/imx7ulp-evk.dts @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * Dong Aisheng + */ + +/dts-v1/; + +#include "imx7ulp.dtsi" + +/ { + model = "NXP i.MX7ULP EVK"; + compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT based system"; + + chosen { + stdout-path = &lpuart4; + }; + + memory@60000000 { + reg = <0x60000000 0x40000000>; + }; + + reg_vsd_3v3: regulator-vsd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc0_rst>; + gpio = <&gpio_ptd 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&lpuart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart4>; + status = "okay"; +}; + +&usdhc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc0_cmd_data>, <&pinctrl_usdhc0_clk>, + <&pinctrl_usdhc0_cd>; + cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_vsd_3v3>; + status = "okay"; +}; + +&iomuxc1 { + pinctrl_lpuart4: lpuart4grp { + pinmux = < + IMX7ULP_PAD_PTC3__LPUART4_RX + IMX7ULP_PAD_PTC2__LPUART4_TX + >; + bias-pull-up; + }; + + pinctrl_usdhc0_cmd_data: usdhc0-cmd-data-grp { + pinmux = < + IMX7ULP_PAD_PTD1__SDHC0_CMD + IMX7ULP_PAD_PTD2__SDHC0_CLK + IMX7ULP_PAD_PTD7__SDHC0_D3 + IMX7ULP_PAD_PTD8__SDHC0_D2 + IMX7ULP_PAD_PTD9__SDHC0_D1 + IMX7ULP_PAD_PTD10__SDHC0_D0 + >; + drive-strength = <1>; + bias-pull-up; + }; + + pinctrl_usdhc0_clk: usdhc0-clk-grp { + pinmux = < + IMX7ULP_PAD_PTD2__SDHC0_CLK + >; + drive-strength = <1>; + bias-pull-down; + }; + + pinctrl_usdhc0_cd: usdhc0-gpio-cd-grp { + pinmux = < + IMX7ULP_PAD_PTC10__PTC10 /* USDHC0 CD */ + >; + bias-pull-up; + }; + + pinctrl_usdhc0_rst: usdhc0-gpio-rst-grp { + pinmux = < + IMX7ULP_PAD_PTD0__PTD0 /* USDHC0 RST */ + >; + bias-pull-up; + }; +}; From patchwork Tue Oct 23 11:49:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aisheng Dong X-Patchwork-Id: 988189 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Dong" To: "linux-arm-kernel@lists.infradead.org" Subject: [PATCH V2 8/8] ARM: imx_v6_v7_defconfig: add imx7ulp support Thread-Topic: [PATCH V2 8/8] ARM: imx_v6_v7_defconfig: add imx7ulp support Thread-Index: AQHUasZ229H9KlvQ+0icoCoPm0NpTw== Date: Tue, 23 Oct 2018 11:49:33 +0000 Message-ID: <1540295058-26090-9-git-send-email-aisheng.dong@nxp.com> References: <1540295058-26090-1-git-send-email-aisheng.dong@nxp.com> In-Reply-To: <1540295058-26090-1-git-send-email-aisheng.dong@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK0PR03CA0033.apcprd03.prod.outlook.com (2603:1096:203:2f::21) To AM0PR04MB4211.eurprd04.prod.outlook.com (2603:10a6:208:66::21) authentication-results: spf=none (sender IP is ) smtp.mailfrom=aisheng.dong@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.66] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM0PR04MB4404; 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Dong" , "dongas86@gmail.com" , "linux@armlinux.org.uk" , "robh+dt@kernel.org" , dl-linux-imx , "kernel@pengutronix.de" , Fabio Estevam , "shawnguo@kernel.org" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org Select CONFIG_SOC_IMX7ULP by default. Patch generated via make ARCH=arm savedefconfig Cc: Shawn Guo Cc: Sascha Hauer Cc: Fabio Estevam Signed-off-by: Dong Aisheng --- v1->v2: * rebase to new version --- arch/arm/configs/imx_v6_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 1ad5736..27ee422 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -38,6 +38,7 @@ CONFIG_SOC_IMX6SLL=y CONFIG_SOC_IMX6SX=y CONFIG_SOC_IMX6UL=y CONFIG_SOC_IMX7D=y +CONFIG_SOC_IMX7ULP=y CONFIG_SOC_VF610=y CONFIG_PCI=y CONFIG_PCI_MSI=y