From patchwork Sat Oct 20 21:24:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Corbin X-Patchwork-Id: 987240 Return-Path: X-Original-To: incoming-buildroot@patchwork.ozlabs.org Delivered-To: patchwork-incoming-buildroot@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=busybox.net (client-ip=140.211.166.138; helo=whitealder.osuosl.org; envelope-from=buildroot-bounces@busybox.net; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=embecosm.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=embecosm.com header.i=@embecosm.com header.b="PsQGfhez"; dkim-atps=neutral Received: from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42cwnP6TPdz9sC2 for ; Sun, 21 Oct 2018 08:26:01 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by whitealder.osuosl.org (Postfix) with ESMTP id B782687653; Sat, 20 Oct 2018 21:25:58 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from whitealder.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id m3gDE2LutSHO; Sat, 20 Oct 2018 21:25:57 +0000 (UTC) Received: from ash.osuosl.org (ash.osuosl.org [140.211.166.34]) by whitealder.osuosl.org (Postfix) with ESMTP id 0E72187672; Sat, 20 Oct 2018 21:25:57 +0000 (UTC) X-Original-To: buildroot@lists.busybox.net Delivered-To: buildroot@osuosl.org Received: from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137]) by ash.osuosl.org (Postfix) with ESMTP id 9798C1BF3A2 for ; Sat, 20 Oct 2018 21:25:55 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by fraxinus.osuosl.org (Postfix) with ESMTP id 951608638F for ; Sat, 20 Oct 2018 21:25:55 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from fraxinus.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id kcmJ9XRgZsPk for ; Sat, 20 Oct 2018 21:25:54 +0000 (UTC) X-Greylist: from auto-whitelisted by SQLgrey-1.7.6 Received: from mail-wr1-f68.google.com (mail-wr1-f68.google.com [209.85.221.68]) by fraxinus.osuosl.org (Postfix) with ESMTPS id 244D38625D for ; Sat, 20 Oct 2018 21:25:54 +0000 (UTC) Received: by mail-wr1-f68.google.com with SMTP id 61-v6so40875376wrb.6 for ; Sat, 20 Oct 2018 14:25:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; h=from:to:cc:subject:date:message-id; bh=gW1AQ3cYA5xdquBDneFhBB53jgz2zANoN2Y6ogAu/XY=; b=PsQGfhezaxHXn/+c16HIgISMYzqZAe5cxHJg9FIVSBxvZmItSHkTmsHR23Zgek++zr wrRnuyEgXp90Q9Rv7uLpwsM57eH0Gz6jt2p9+AEc0ekZpg/2hTTZIX1xxLdWnNUMm0kI SKHBNdKKpWqmwSqAfTcx+2NpkfPW2DEwJN5fKv7dZdhvqx88YiYzIYO1QEmKeDCqLYso tAOy5awt3V7UJIcxb5o1v/sLIpD3T/0oFDQPLl/O+7FjtspC8xgjZhmOx68dy0L2r1cM Mtauiy9X4LdH1yWhKwGXga06fjDk6C4U0hqWldaJ0Dic1jGU7p4YlB1+nIGC8FsUKU2P 1xgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=gW1AQ3cYA5xdquBDneFhBB53jgz2zANoN2Y6ogAu/XY=; b=d0NwvAS43nk+46I1X8NAAOt2MW1gDW+nnEcjYX1xzQlZN7PygtWL0C6O8hgmZFbGVM I9ZVYvNxqHi2PWT3r5jhN8PsfDwoXXT+2nXk6OW6+BgqGabNmFUp+A1xtN+qvNBWpLYB b7+RuHTeh6KKSef5HAsIdIXoWyHgQRSdhDu1X9xlUqE+TDJ6mwL0xLNZLkBzuLUFXETL eRBkkZTk5zBTQM+Lj7LhfN4+wwFgrNIdDHggDv7Bq/DX/7Z2CnbeKoXB7AXroJi8j0Wu Dy46i0KLAd4ywXNboxDDiYuxqZSJHKUiv5YvnAfrnHpS5BQQs2HExjLOHzMwPo9o0V+L W4lw== X-Gm-Message-State: AGRZ1gIQisAoNo8K/ywVKKYEp/YJFJOC1vz7xb39obSqjZRhsVJ+udTE YpsVYG6Pvsq1cs5T4NMPh3c9O9+EBBE= X-Google-Smtp-Source: AJdET5fW5GB5aMIjU244gsvVHWk2hXxB6v3urti8VE4SC3R8jJOQXojTMOyU1VoE7ay87swbN4P5Rw== X-Received: by 2002:adf:ef09:: with SMTP id e9-v6mr8647757wro.292.1540070752137; Sat, 20 Oct 2018 14:25:52 -0700 (PDT) Received: from tait.lan.virginwifi.ie ([5.148.126.125]) by smtp.gmail.com with ESMTPSA id x8-v6sm67933226wrd.54.2018.10.20.14.25.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 20 Oct 2018 14:25:51 -0700 (PDT) From: Mark Corbin To: buildroot@buildroot.org Date: Sat, 20 Oct 2018 22:24:42 +0100 Message-Id: <20181020212443.4935-1-mark.corbin@embecosm.com> X-Mailer: git-send-email 2.17.1 Subject: [Buildroot] [PATCH 1/2] arch: add support for RISC-V 32-bit (riscv32) architecture X-BeenThere: buildroot@busybox.net X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion and development of buildroot List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Corbin MIME-Version: 1.0 Errors-To: buildroot-bounces@busybox.net Sender: "buildroot" This enables a riscv32 system to be built with a Buildroot generated toolchain (gcc >= 7.x, binutils >= 2.30, glibc only). This requires a custom version of glibc 2.26 from the riscv-glibc repository. Note that there are no tags in this repository, so the glibc version just consists of the 40 character commit id string. Thanks to Fabrice Bellard for pointing me towards the 32-bit glibc repository and for providing the necessary patch to get it to build. Signed-off-by: Mark Corbin --- arch/Config.in.riscv | 23 +++++++++++-- arch/arch.mk.riscv | 4 ++- configs/qemu_riscv64_virt_defconfig | 1 + .../0001-riscv32.patch | 33 +++++++++++++++++++ .../glibc.hash | 7 ++++ package/glibc/glibc.mk | 7 ++++ 6 files changed, 71 insertions(+), 4 deletions(-) create mode 100644 package/glibc/4e2943456e690d89f48e6e710757dd09404b0c9a/0001-riscv32.patch create mode 100644 package/glibc/4e2943456e690d89f48e6e710757dd09404b0c9a/glibc.hash diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv index 4361890bf4..4615f3c797 100644 --- a/arch/Config.in.riscv +++ b/arch/Config.in.riscv @@ -66,13 +66,26 @@ config BR2_RISCV_ISA_CUSTOM_RVC endif config BR2_RISCV_64 - bool - default y + bool "64-bit" + default n select BR2_ARCH_IS_64 choice prompt "Target ABI" - default BR2_RISCV_ABI_LP64 + default BR2_RISCV_ABI_ILP32 if !BR2_ARCH_IS_64 + default BR2_RISCV_ABI_LP64 if BR2_ARCH_IS_64 + +config BR2_RISCV_ABI_ILP32 + bool "ilp32" + depends on !BR2_ARCH_IS_64 + +config BR2_RISCV_ABI_ILP32F + bool "ilp32f" + depends on !BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVF + +config BR2_RISCV_ABI_ILP32D + bool "ilp32d" + depends on !BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVD config BR2_RISCV_ABI_LP64 bool "lp64" @@ -88,12 +101,16 @@ config BR2_RISCV_ABI_LP64D endchoice config BR2_ARCH + default "riscv32" if !BR2_ARCH_IS_64 default "riscv64" if BR2_ARCH_IS_64 config BR2_ENDIAN default "LITTLE" config BR2_GCC_TARGET_ABI + default "ilp32" if BR2_RISCV_ABI_ILP32 + default "ilp32f" if BR2_RISCV_ABI_ILP32F + default "ilp32d" if BR2_RISCV_ABI_ILP32D default "lp64" if BR2_RISCV_ABI_LP64 default "lp64f" if BR2_RISCV_ABI_LP64F default "lp64d" if BR2_RISCV_ABI_LP64D diff --git a/arch/arch.mk.riscv b/arch/arch.mk.riscv index 022d1a6809..f3bf2b3467 100644 --- a/arch/arch.mk.riscv +++ b/arch/arch.mk.riscv @@ -5,8 +5,10 @@ ifeq ($(BR2_riscv),y) -ifeq ($(BR2_ARCH_IS_64),y) +ifeq ($(BR2_RISCV_64),y) GCC_TARGET_ARCH := rv64i +else +GCC_TARGET_ARCH := rv32i endif ifeq ($(BR2_RISCV_ISA_RVM),y) diff --git a/configs/qemu_riscv64_virt_defconfig b/configs/qemu_riscv64_virt_defconfig index 59343ee98f..e15f804341 100644 --- a/configs/qemu_riscv64_virt_defconfig +++ b/configs/qemu_riscv64_virt_defconfig @@ -1,5 +1,6 @@ # Architecture BR2_riscv=y +BR2_RISCV_64=y # System BR2_SYSTEM_DHCP="eth0" diff --git a/package/glibc/4e2943456e690d89f48e6e710757dd09404b0c9a/0001-riscv32.patch b/package/glibc/4e2943456e690d89f48e6e710757dd09404b0c9a/0001-riscv32.patch new file mode 100644 index 0000000000..0d5a6b7710 --- /dev/null +++ b/package/glibc/4e2943456e690d89f48e6e710757dd09404b0c9a/0001-riscv32.patch @@ -0,0 +1,33 @@ +diff --git a/elf/dl-runtime.c b/elf/dl-runtime.c +index 51d3819d4a..e728e8907e 100644 +--- a/elf/dl-runtime.c ++++ b/elf/dl-runtime.c +@@ -146,6 +146,7 @@ _dl_fixup ( + if (__glibc_unlikely (GLRO(dl_bind_not))) + return value; + ++ (void)refsym; + return elf_machine_fixup_plt (l, result, refsym, sym, reloc, rel_addr, value); + } + +diff --git a/sysdeps/riscv/ldsodefs.h b/sysdeps/riscv/ldsodefs.h +index db993df80a..91e7a8c88f 100644 +--- a/sysdeps/riscv/ldsodefs.h ++++ b/sysdeps/riscv/ldsodefs.h +@@ -25,14 +25,14 @@ struct La_riscv_regs; + struct La_riscv_retval; + + #define ARCH_PLTENTER_MEMBERS \ +- Elf64_Addr (*riscv_gnu_pltenter) (Elf64_Sym *, unsigned int, \ ++ ElfW(Addr) (*riscv_gnu_pltenter) (ElfW(Sym) *, unsigned int, \ + uintptr_t *, uintptr_t *, \ + const struct La_riscv_regs *, \ + unsigned int *, const char *name, \ + long int *framesizep); + + #define ARCH_PLTEXIT_MEMBERS \ +- unsigned int (*riscv_gnu_pltexit) (Elf64_Sym *, unsigned int, \ ++ unsigned int (*riscv_gnu_pltexit) (ElfW(Sym) *, unsigned int, \ + uintptr_t *, uintptr_t *, \ + const struct La_riscv_regs *, \ + struct La_riscv_retval *, \ diff --git a/package/glibc/4e2943456e690d89f48e6e710757dd09404b0c9a/glibc.hash b/package/glibc/4e2943456e690d89f48e6e710757dd09404b0c9a/glibc.hash new file mode 100644 index 0000000000..3eb5e04e96 --- /dev/null +++ b/package/glibc/4e2943456e690d89f48e6e710757dd09404b0c9a/glibc.hash @@ -0,0 +1,7 @@ +# Locally calculated (fetched from Github) +sha256 a40f908125135bad2cf92c18d07ad25b3091b161b3a5d3aea46c23ffd2ac90b8 glibc-4e2943456e690d89f48e6e710757dd09404b0c9a.tar.gz + +# Hashes for license files +sha256 8177f97513213526df2cf6184d8ff986c675afb514d4e68a404010521b880643 COPYING +sha256 dc626520dcd53a22f727af3ee42c770e56c97a64fe3adb063799d8ab032fe551 COPYING.LIB +sha256 61abdd6930c9c599062d89e916b3e7968783879b6be0ee1c6229dd6169def431 LICENSES diff --git a/package/glibc/glibc.mk b/package/glibc/glibc.mk index 708c22f723..cea77dff39 100644 --- a/package/glibc/glibc.mk +++ b/package/glibc/glibc.mk @@ -7,6 +7,9 @@ ifeq ($(BR2_arc),y) GLIBC_VERSION = arc-2018.03-release GLIBC_SITE = $(call github,foss-for-synopsys-dwc-arc-processors,glibc,$(GLIBC_VERSION)) +else ifeq ($(BR2_riscv)$(BR2_RISCV_64),y) +GLIBC_VERSION = 4e2943456e690d89f48e6e710757dd09404b0c9a +GLIBC_SITE = $(call github,riscv,riscv-glibc,$(GLIBC_VERSION)) else # Generate version string using: # git describe --match 'glibc-*' --abbrev=40 origin/release/MAJOR.MINOR/master @@ -79,7 +82,11 @@ GLIBC_CONF_ENV = \ # Override the default library locations of /lib64/ and # /usr/lib64// for RISC-V. ifeq ($(BR2_riscv),y) +ifeq ($(BR2_RISCV_64),y) GLIBC_CONF_ENV += libc_cv_slibdir=/lib64 libc_cv_rtlddir=/lib +else +GLIBC_CONF_ENV += libc_cv_slibdir=/lib32 libc_cv_rtlddir=/lib +endif endif # Even though we use the autotools-package infrastructure, we have to From patchwork Sat Oct 20 21:24:43 2018 Content-Type: text/plain; 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Sat, 20 Oct 2018 14:25:56 -0700 (PDT) From: Mark Corbin To: buildroot@buildroot.org Date: Sat, 20 Oct 2018 22:24:43 +0100 Message-Id: <20181020212443.4935-2-mark.corbin@embecosm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181020212443.4935-1-mark.corbin@embecosm.com> References: <20181020212443.4935-1-mark.corbin@embecosm.com> Subject: [Buildroot] [PATCH 2/2] configs/qemu: add qemu_riscv32_virt_defconfig X-BeenThere: buildroot@busybox.net X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion and development of buildroot List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Corbin MIME-Version: 1.0 Errors-To: buildroot-bounces@busybox.net Sender: "buildroot" Add RISC-V 32-bit defconfig for QEMU virt machine. Tested with QEMU 2.12.1 Signed-off-by: Mark Corbin Reviewed-by: Romain Naour Tested-by: Romain Naour --- board/qemu/riscv32-virt/linux.config | 23 +++++++++++++++++++++++ board/qemu/riscv32-virt/readme.txt | 7 +++++++ configs/qemu_riscv32_virt_defconfig | 24 ++++++++++++++++++++++++ 3 files changed, 54 insertions(+) create mode 100644 board/qemu/riscv32-virt/linux.config create mode 100644 board/qemu/riscv32-virt/readme.txt create mode 100644 configs/qemu_riscv32_virt_defconfig diff --git a/board/qemu/riscv32-virt/linux.config b/board/qemu/riscv32-virt/linux.config new file mode 100644 index 0000000000..c25583f768 --- /dev/null +++ b/board/qemu/riscv32-virt/linux.config @@ -0,0 +1,23 @@ +CONFIG_ARCH_RV32I=y +CONFIG_SMP=y +CONFIG_NR_CPUS=8 +CONFIG_PCI=y +CONFIG_SYSVIPC=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_WIRELESS is not set +CONFIG_VIRTIO_BLK=y +CONFIG_NETDEVICES=y +CONFIG_VIRTIO_NET=y +# CONFIG_ETHERNET is not set +# CONFIG_WLAN is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_VIRT_DRIVERS=y +CONFIG_VIRTIO_MMIO=y +CONFIG_EXT2_FS=y +CONFIG_EXT4_FS=y +CONFIG_TMPFS=y diff --git a/board/qemu/riscv32-virt/readme.txt b/board/qemu/riscv32-virt/readme.txt new file mode 100644 index 0000000000..2da99580e5 --- /dev/null +++ b/board/qemu/riscv32-virt/readme.txt @@ -0,0 +1,7 @@ +Run the emulation with: + + qemu-system-riscv32 -M virt -kernel output/images/bbl -append "root=/dev/vda ro console=ttyS0" -drive file=output/images/rootfs.ext2,format=raw,id=hd0 -device virtio-blk-device,drive=hd0 -netdev user,id=net0 -device virtio-net-device,netdev=net0 -nographic + +The login prompt will appear in the terminal that started Qemu. + +Tested with QEMU 2.12.1 diff --git a/configs/qemu_riscv32_virt_defconfig b/configs/qemu_riscv32_virt_defconfig new file mode 100644 index 0000000000..aec85e4639 --- /dev/null +++ b/configs/qemu_riscv32_virt_defconfig @@ -0,0 +1,24 @@ +# Architecture +BR2_riscv=y + +# System +BR2_SYSTEM_DHCP="eth0" + +# Filesystem +BR2_TARGET_ROOTFS_EXT2=y +BR2_TARGET_GENERIC_GETTY=y +BR2_TARGET_GENERIC_GETTY_PORT="ttyS0" + +# Linux headers same as kernel, a 4.15 series +BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_15=y + +# Kernel +BR2_LINUX_KERNEL=y +BR2_LINUX_KERNEL_CUSTOM_GIT=y +BR2_LINUX_KERNEL_CUSTOM_REPO_URL="https://github.com/riscv/riscv-linux.git" +BR2_LINUX_KERNEL_CUSTOM_REPO_VERSION="fe92d7905c6ea0ebeabeb725b8040754ede7c220" +BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y +BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="board/qemu/riscv32-virt/linux.config" + +# Bootloader +BR2_TARGET_RISCV_PK=y