From patchwork Sat Oct 20 13:38:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Walmsley X-Patchwork-Id: 987197 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="OBiHFoRW"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42ckQT1wHHz9sj2 for ; Sun, 21 Oct 2018 00:38:57 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727573AbeJTVtN (ORCPT ); Sat, 20 Oct 2018 17:49:13 -0400 Received: from mail-wr1-f68.google.com ([209.85.221.68]:38848 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727534AbeJTVtN (ORCPT ); Sat, 20 Oct 2018 17:49:13 -0400 Received: by mail-wr1-f68.google.com with SMTP id d10-v6so605767wrs.5 for ; Sat, 20 Oct 2018 06:38:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZvxOUP5Fom85HZYW6S3mncAl5RrZvlD+akPdxng1h0A=; b=OBiHFoRWGSmBv7ST/JPrISARyB8LRjBOUYLcjAKz8XWUZyA2L3FCOttjWFJeXVvyqr 8pmxNj86PAIkXrw187mSpr/qK6pFofaNLRlMy6UGs4YGUurpYeF4CRgVj5TZtu044yTQ tnOkMWY3yO1d8QsgpkyEFSagnyoQ8V63WzoAvGHfsjKXe+vs1xlbNiXXYReSUfNJbz05 cVKM0NTvF/EzQw68ymE6YMT9gk12+lnfDvvUKOA3lTxUKR6rsStWSsCM2yZIux+HCi+u Nz2A+UKrw+pukQTAYkmMJulGQL2XogQTiR8Vvh9myI7W17+0yhw4cKvD99XGBcPZTevm ScCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZvxOUP5Fom85HZYW6S3mncAl5RrZvlD+akPdxng1h0A=; b=bCPODOfBK28q2JIjiGuSWQXABaSur95DTQPcWaXbhegxMGIIbdph8XKYOcXreg5uT3 x7lNpMFHvt9+n2WkdGkUEOW4+KamHSpjGnIWz58+Sc7U4YjzhwG0vHPgSMdi1+8UuTYp 68dTX8aSCYE8qgVUrlSg7DIfUSs+hHaYhmvWg+QQlP/4C0En664nIUMsdIK+S56WiEOL LzMbVG2qqmkU1cWv8tUa3vEqldg9Lar4DkSR7EyyIFYF4vEPb+88ekszH93tu/RSPQHm qtrM2TuTpSaye/i/VmnSlhMIt0hTgRPVWZa4F0PQkIBs5hrPgIwLQTCCaz4FmpMnWMhW CDaQ== X-Gm-Message-State: AGRZ1gJwejzg45fuclSNZ2WsSVGSSECPHPfEVFFMSb8jJYP2a7EvT5VQ 6ZLfS99YMEHXY3cOQuxPz7GbeQ== X-Google-Smtp-Source: AJdET5fwa2wuI67FoW/kdcoyeYefbSZ/8qcn2kZ0BY8xUuW5D54vtMt75emXeALF9/wR6n/a2pEKTg== X-Received: by 2002:adf:9246:: with SMTP id 64-v6mr6403097wrj.130.1540042721693; Sat, 20 Oct 2018 06:38:41 -0700 (PDT) Received: from viisi.sifive.com ([37.152.39.96]) by smtp.gmail.com with ESMTPSA id f1-v6sm5227207wme.23.2018.10.20.06.38.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 20 Oct 2018 06:38:41 -0700 (PDT) From: Paul Walmsley To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: Paul Walmsley , Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Palmer Dabbelt , Megan Wachs , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Paul Walmsley Subject: [PATCH 2/3] dt-bindings: clk: add documentation for the SiFive PRCI driver Date: Sat, 20 Oct 2018 06:38:23 -0700 Message-Id: <20181020133823.27103-3-paul.walmsley@sifive.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181020133823.27103-1-paul.walmsley@sifive.com> References: <20181020133823.27103-1-paul.walmsley@sifive.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT binding documentation for the Linux driver for the SiFive PRCI clock & reset control IP block, as found on the SiFive FU540 chip. Cc: Michael Turquette Cc: Stephen Boyd Cc: Rob Herring Cc: Mark Rutland Cc: Palmer Dabbelt Cc: Megan Wachs Cc: linux-clk@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Paul Walmsley Signed-off-by: Paul Walmsley --- .../bindings/clock/sifive/fu540-prci.txt | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt diff --git a/Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt new file mode 100644 index 000000000000..27d8fdd4f3a2 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt @@ -0,0 +1,40 @@ +SiFive FU540 PRCI bindings + +On the FU540 family of SoCs, most system-wide clock and reset integration +is via the PRCI IP block. + +Required properties: +- compatible: Should be "sifive,fu540-c000-prci0" +- reg: Should describe the PRCI's register target physical address region +- clocks: Should point to the hfclk device tree node and the rtcclk + device tree node. The RTC clock here is not a time-of-day clock, + but is instead a high-stability clock source for system timers + and cycle counters. +- #clock-cells: Should be <1> + +The clock consumer should specify the desired clock via the clock ID +macros defined in include/linux/clk/sifive-fu540-prci.h. These macros +begin with PRCI_CLK_. + + + +Examples: + +hfclk: hfclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <33333333>; + clock-output-names = "hfclk"; +}; +rtcclk: rtcclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <1000000>; + clock-output-names = "rtcclk"; +}; +prci0: prci@10000000 { + compatible = "sifive,fu540-c000-prci0", "sifive,prci0"; + reg = <0x0 0x10000000 0x0 0x1000>; + clocks = <&hfclk>, <&rtcclk>; + #clock-cells = <1>; +};