From patchwork Sat Oct 20 10:10:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Walmsley X-Patchwork-Id: 987182 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="UQ/ifgKT"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42cdrP6HRjz9s9J for ; Sat, 20 Oct 2018 21:12:37 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727405AbeJTSWN (ORCPT ); Sat, 20 Oct 2018 14:22:13 -0400 Received: from mail-wr1-f67.google.com ([209.85.221.67]:38543 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727296AbeJTSWN (ORCPT ); Sat, 20 Oct 2018 14:22:13 -0400 Received: by mail-wr1-f67.google.com with SMTP id d10-v6so274643wrs.5 for ; Sat, 20 Oct 2018 03:12:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wASbXyBYFMcRIkQoK4CDFHurMQnCI3R8vyfKJiCMxpo=; b=UQ/ifgKTmwDizP/mPww3MG4vreiMpQ8AIMKtieTEAr/e5NNsOKHszM+NRRM5OWqRsR qd7ENY4cc1KqZyzybNUHmPRaqI6hA4icH9yhk/XO/ZBZfrz6kYQx9AeN67iH+tBwv+FU V0RC56nui14BWbtNn9eSkTrSwa54zWoy1tp6eRuJzqVI59aqjD/I6MaLS8bPm9LHklNb skVlnVaiuJ1Oprg0CLRSONC3L12mEW3lgYXtpwuxPX+grGwr2ieMHUVwhx2wbVa9g+Ao vDpf340Npqsz22uc4wCjnpaa2VXxa05BQcbbC5DP5C0sUQg5fjAOPqw/un60bBBRGGwc h83g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wASbXyBYFMcRIkQoK4CDFHurMQnCI3R8vyfKJiCMxpo=; b=F1K5EpEE7Z4903nupRrFT1F3APsGL2Qd3c1M9HimtL2QqvbarzTWDgAPKqeEe1oAbj pR8STF/hB4DIUOjtn7/5Q8ur4A+Gv2r1NnneLg0bcBYQZSlwMu6405ShDJG84jmCBnTX Tx+ENS8/DOnSxr3D+nyNvB0WIxWfqblyrnXAVhfCiXGkpLViDQNaiZypD+VF0/MooOY9 9uNhcV+smIsO05HnOSvyx78lB8MUvytCMKerq6/5t0z43RExh4sxQQwjRMYWgIFJaKuh pJ2GwrQUauYSPL0wlmmtkHbdTcQhT2gMel3XzaMIatTtCyqgKRPrMF4keUTJWql2N8EA 4bug== X-Gm-Message-State: ABuFfohc8qr8uTbjBPf3O+q+nx2cp6VgmG+zi4vye1wzr4x32+Ud4qiC 1DNH25j5NLInPGZm7G1sDe2gDg== X-Google-Smtp-Source: ACcGV61ZRzN6qFa7EQQvAdvDjUdCAOdb5iqDYDLhqLEJ6Z8ehDOvwiwg5DMGbTi4qEM7MxgN/YkMEg== X-Received: by 2002:a05:6000:1284:: with SMTP id f4mr16331584wrx.140.1540030337812; Sat, 20 Oct 2018 03:12:17 -0700 (PDT) Received: from viisi.sifive.com ([37.152.39.96]) by smtp.gmail.com with ESMTPSA id 2-v6sm23773438wro.96.2018.10.20.03.12.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 20 Oct 2018 03:12:17 -0700 (PDT) From: Paul Walmsley To: linux-serial@vger.kernel.org Cc: Paul Walmsley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Greg Kroah-Hartman , Rob Herring , Mark Rutland , Palmer Dabbelt , Paul Walmsley Subject: [PATCH v3 1/2] dt-bindings: serial: add documentation for the SiFive UART driver Date: Sat, 20 Oct 2018 03:10:46 -0700 Message-Id: <20181020101045.15991-2-paul.walmsley@sifive.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181020101045.15991-1-paul.walmsley@sifive.com> References: <20181020101045.15991-1-paul.walmsley@sifive.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT binding documentation for the Linux driver for the SiFive asynchronous serial IP block. Cc: linux-serial@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman Cc: Rob Herring Cc: Mark Rutland Cc: Palmer Dabbelt Reviewed-by: Palmer Dabbelt Signed-off-by: Paul Walmsley Signed-off-by: Paul Walmsley --- v3: update description and example for compatible strings, per discussion with Rob Herring. .../bindings/serial/sifive-serial.txt | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/sifive-serial.txt diff --git a/Documentation/devicetree/bindings/serial/sifive-serial.txt b/Documentation/devicetree/bindings/serial/sifive-serial.txt new file mode 100644 index 000000000000..a426b18ba049 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/sifive-serial.txt @@ -0,0 +1,33 @@ +SiFive asynchronous serial interface (UART) + +Required properties: + +- compatible: should be something similar to + "sifive,-uart" for the UART as integrated + on a particular chip, and "sifive,uart" for the + general UART IP block programming model. Supported + compatible strings as of the date of this writing are: + "sifive,fu540-c000-uart0" for the SiFive UART v0 as + integrated onto the SiFive FU540 chip, or "sifive,uart0" + for the SiFive UART v0 IP block with no chip integration + tweaks (if any) +- reg: address and length of the register space +- interrupts: Should contain the UART interrupt identifier +- clocks: Should contain a clock identifier for the UART's parent clock + + +UART RTL that corresponds to the IP block version numbers can be found +here: + +https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/uart + + +Example: + +uart0: serial@10010000 { + compatible = "sifive,fu540-c000-uart0", "sifive,uart0"; + interrupt-parent = <&plic0>; + interrupts = <80>; + reg = <0x0 0x10010000 0x0 0x1000>; + clocks = <&prci PRCI_CLK_TLCLK>; +};