From patchwork Tue Oct 16 02:50:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Hua X-Patchwork-Id: 984495 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-487608-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="kwpgBDXu"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="YPj/YJFI"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42Z0DS1yhwz9s9J for ; Tue, 16 Oct 2018 13:50:48 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:cc:content-type; q=dns; s=default; b=T39CfXkz8k0nZAzDlIFYFw7TSzjMInkcINRbNWuJPoL F2vWLJrUwT83a6cdaWWa3VmoAEuItochK+eWe5S5YtoIMmFGqIGkFFniEBtWZEG4 Ta6Del9Vr3BZ9KWF8pVk4ji0FtZ6FM1/ppFt6HEyK1aA3WVQK0ePsyeQ2/WFck0o = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:cc:content-type; s=default; bh=TzVhs/BiIKz03acoMj4X1almF68=; b=kwpgBDXua5FHizhfv eapQ+gqxykmmzBRftwsN2hOdR993SBAbWXnQMhHZYevKNPIIy+RczIj3O0vgc9It +su61iCRGX5sccNRAh2cGUIds9yxHewSxYPLlx9+4rsFGy8VvfXDPtGoG7qw+iPS dOVQ1Te3pQTTRJtzSldQ5Lo7co= Received: (qmail 90941 invoked by alias); 16 Oct 2018 02:50:28 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 90795 invoked by uid 89); 16 Oct 2018 02:50:27 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS, TIME_LIMIT_EXCEEDED autolearn=unavailable version=3.3.2 spammy=4497, granted, assemble, HX-Received:sk:k13-v6m X-HELO: mail-oi1-f170.google.com Received: from mail-oi1-f170.google.com (HELO mail-oi1-f170.google.com) (209.85.167.170) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 16 Oct 2018 02:50:16 +0000 Received: by mail-oi1-f170.google.com with SMTP id s69-v6so16779669oie.10 for ; Mon, 15 Oct 2018 19:50:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to:cc; bh=8nRoLGS8vgrJapimO20hZr4iQAdUzk3b8C3K+F4X4Ao=; b=YPj/YJFI3HOjERuBkmyhncOp6obTuPooyqCYfVuWQXjECcdYgSbbZq2XPK+ldbe+xz WB0CD3AuxZgEn+pzVAP+bjLlZgpv2420lLJRlU+1Z728TM2xcEXgZfkcbLz1ODiKpdn5 0xBERegAzvoX+h71eCadrja/QKmhyPhuXee/tDn112coJ3hEV0v8EDfruOUZrNSOdUCs 5D6FAKrcHgvxPkKbZEkqcTBWyd+jFZlhYzWe45gejS65REthlm2XEbDo+9n3w7hY5aiq tryVpI/9JlE5k6t4Hyrn/P11efU9bteIrnR2KBayJ9WfoXqomF21qWvdVQxUKV5tsO15 Ivag== MIME-Version: 1.0 From: Paul Hua Date: Tue, 16 Oct 2018 10:50:02 +0800 Message-ID: Subject: [PATCH v3 1/6] [MIPS] Split Loongson (MMI) from loongson3a To: gcc-patches Cc: Matthew Fortune , "Jeff Law (law@redhat.com)" X-IsSubscribed: yes From e9d36eb4d4a841486ac82037497a2671481f8a27 Mon Sep 17 00:00:00 2001 From: Chenghua Xu Date: Sun, 14 Oct 2018 11:11:00 +0800 Subject: [PATCH 1/6] Add support for loongson mmi instructions. gcc/ * config.gcc (extra_headers): Add loongson-mmiintrin.h. * config/mips/loongson.md: Move to ... * config/mips/loongson-mmi.md: here; Adjustment. * config/mips/loongsson.h: Move to ... State as deprecated. Include loongson-mmiintrin.h for back compatibility and warning. * config/mips/loongsson-mmiintrin.h: ... here. * config/mips/mips.c (mips_hard_regno_mode_ok_uncached, mips_vector_mode_supported_p, AVAIL_NON_MIPS16): Use TARGET_LOONGSON_MMI instead of TARGET_LOONGSON_VECTORS. (mips_option_override): Make sure MMI use hard float; Default enable MMI on Loongson 2e/2f/3a. (mips_shift_truncation_mask, mips_expand_vpc_loongson_even_odd, mips_expand_vpc_loongson_pshufh, mips_expand_vpc_loongson_bcast, mips_expand_vector_init): Use TARGET_LOONGSON_MMI instead of TARGET_LOONGSON_VECTORS. * gcc/config/mips/mips.h (TARGET_LOONGSON_VECTORS): Delete. (TARGET_CPU_CPP_BUILTINS): Add __mips_loongson_mmi. (SHIFT_COUNT_TRUNCATED): Use TARGET_LOONGSON_MMI instead of TARGET_LOONGSON_VECTORS. * gcc/config/mips/mips.md (MOVE64, MOVE128): Use TARGET_LOONGSON_MMI instead of TARGET_LOONGSON_VECTORS. (Loongson MMI patterns): Include loongson-mmi.md instead of loongson.md. * gcc/config/mips/mips.opt (-mloongson-mmi): New option. * gcc/doc/invoke.texi (-mloongson-mmi): Document. gcc/testsuite/ * gcc.target/mips/loongson-shift-count-truncated-1.c (dg-options): Run under -mloongson-mmi option. Include loongson-mmiintrin.h instead of loongson.h. * gcc.target/mips/loongson-simd.c: Likewise. * gcc.target/mips/mips.exp (mips_option_groups): Add -mloongson-mmi option. (mips-dg-init): Add -mloongson-mmi option. * gcc.target/mips/umips-store16-1.c (dg-options): Add forbid_cpu=loongson3a. * lib/target-supports.exp: Rename check_mips_loongson_hw_available to check_mips_loongson_mmi_hw_available. Rename check_effective_target_mips_loongson_runtime to check_effective_target_mips_loongson_mmi_runtime. (check_effective_target_vect_int): Use mips_loongson_mmi instead of mips_loongson when check et-is-effective-target. (add_options_for_mips_loongson_mmi): New proc. Rename check_effective_target_mips_loongson to check_effective_target_mips_loongson_mmi. (check_effective_target_vect_shift, check_effective_target_whole_vector_shift, check_effective_target_vect_no_int_min_max, check_effective_target_vect_no_align, check_effective_target_vect_short_mult, check_vect_support_and_set_flags):Use mips_loongson_mmi instead of mips_loongson when check et-is-effective-target. --- gcc/config.gcc | 2 +- gcc/config/mips/{loongson.md => loongson-mmi.md} | 241 ++++--- gcc/config/mips/loongson-mmiintrin.h | 691 +++++++++++++++++++++ gcc/config/mips/loongson.h | 669 +------------------- gcc/config/mips/mips.c | 34 +- gcc/config/mips/mips.h | 21 +- gcc/config/mips/mips.md | 16 +- gcc/config/mips/mips.opt | 4 + gcc/doc/invoke.texi | 7 + .../mips/loongson-shift-count-truncated-1.c | 6 +- gcc/testsuite/gcc.target/mips/loongson-simd.c | 4 +- gcc/testsuite/gcc.target/mips/mips.exp | 7 + gcc/testsuite/gcc.target/mips/umips-store16-1.c | 2 +- gcc/testsuite/lib/target-supports.exp | 47 +- 14 files changed, 913 insertions(+), 838 deletions(-) rename gcc/config/mips/{loongson.md => loongson-mmi.md} (79%) create mode 100644 gcc/config/mips/loongson-mmiintrin.h diff --git a/gcc/config.gcc b/gcc/config.gcc index 8521f7d556e..7871700db13 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -441,7 +441,7 @@ microblaze*-*-*) ;; mips*-*-*) cpu_type=mips - extra_headers="loongson.h msa.h" + extra_headers="loongson.h loongson-mmiintrin.h msa.h" extra_objs="frame-header-opt.o" extra_options="${extra_options} g.opt fused-madd.opt mips/mips-tables.opt" ;; diff --git a/gcc/config/mips/loongson.md b/gcc/config/mips/loongson-mmi.md similarity index 79% rename from gcc/config/mips/loongson.md rename to gcc/config/mips/loongson-mmi.md index 14794d3671f..ad23f676581 100644 --- a/gcc/config/mips/loongson.md +++ b/gcc/config/mips/loongson-mmi.md @@ -1,5 +1,4 @@ -;; Machine description for Loongson-specific patterns, such as -;; ST Microelectronics Loongson-2E/2F etc. +;; Machine description for Loongson MultiMedia extensions Instructions (MMI). ;; Copyright (C) 2008-2018 Free Software Foundation, Inc. ;; Contributed by CodeSourcery. ;; @@ -102,7 +101,7 @@ (define_expand "mov" [(set (match_operand:VWHB 0) (match_operand:VWHB 1))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" { if (mips_legitimize_move (mode, operands[0], operands[1])) DONE; @@ -111,8 +110,8 @@ ;; Handle legitimized moves between values of vector modes. (define_insn "mov_internal" [(set (match_operand:VWHB 0 "nonimmediate_operand" "=m,f,d,f, d, m, d") - (match_operand:VWHB 1 "move_operand" "f,m,f,dYG,dYG,dYG,m"))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + (match_operand:VWHB 1 "move_operand" "f,m,f,dYG,dYG,dYG,m"))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" { return mips_output_move (operands[0], operands[1]); } [(set_attr "move_type" "fpstore,fpload,mfc,mtc,move,store,load") (set_attr "mode" "DI")]) @@ -122,7 +121,7 @@ (define_expand "vec_init" [(set (match_operand:VWHB 0 "register_operand") (match_operand 1 ""))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" { mips_expand_vector_init (operands[0], operands[1]); DONE; @@ -135,7 +134,7 @@ (unspec:VHB [(truncate: (match_operand:DI 1 "reg_or_0_operand" "Jd"))] UNSPEC_LOONGSON_VINIT))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "dmtc1\t%z1,%0" [(set_attr "move_type" "mtc") (set_attr "mode" "DI")]) @@ -146,7 +145,7 @@ (vec_concat:V2SI (match_operand:SI 1 "register_operand" "f") (match_operand:SI 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "punpcklwd\t%0,%1,%2" [(set_attr "type" "fcvt")]) @@ -155,33 +154,33 @@ ;; Pack with signed saturation. (define_insn "vec_pack_ssat_" [(set (match_operand: 0 "register_operand" "=f") - (vec_concat: + (vec_concat: (ss_truncate: (match_operand:VWH 1 "register_operand" "f")) (ss_truncate: (match_operand:VWH 2 "register_operand" "f"))))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "packss\t%0,%1,%2" [(set_attr "type" "fmul")]) ;; Pack with unsigned saturation. (define_insn "vec_pack_usat_" [(set (match_operand: 0 "register_operand" "=f") - (vec_concat: + (vec_concat: (us_truncate: (match_operand:VH 1 "register_operand" "f")) (us_truncate: (match_operand:VH 2 "register_operand" "f"))))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "packus\t%0,%1,%2" [(set_attr "type" "fmul")]) ;; Addition, treating overflow by wraparound. (define_insn "add3" [(set (match_operand:VWHB 0 "register_operand" "=f") - (plus:VWHB (match_operand:VWHB 1 "register_operand" "f") + (plus:VWHB (match_operand:VWHB 1 "register_operand" "f") (match_operand:VWHB 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "padd\t%0,%1,%2" [(set_attr "type" "fadd")]) @@ -193,38 +192,38 @@ ;; GPRs instead of FPRs. (define_insn "loongson_paddd" [(set (match_operand:DI 0 "register_operand" "=f") - (unspec:DI [(match_operand:DI 1 "register_operand" "f") + (unspec:DI [(match_operand:DI 1 "register_operand" "f") (match_operand:DI 2 "register_operand" "f")] UNSPEC_LOONGSON_PADDD))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "paddd\t%0,%1,%2" [(set_attr "type" "fadd")]) ;; Addition, treating overflow by signed saturation. (define_insn "ssadd3" [(set (match_operand:VHB 0 "register_operand" "=f") - (ss_plus:VHB (match_operand:VHB 1 "register_operand" "f") + (ss_plus:VHB (match_operand:VHB 1 "register_operand" "f") (match_operand:VHB 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "padds\t%0,%1,%2" [(set_attr "type" "fadd")]) ;; Addition, treating overflow by unsigned saturation. (define_insn "usadd3" [(set (match_operand:VHB 0 "register_operand" "=f") - (us_plus:VHB (match_operand:VHB 1 "register_operand" "f") + (us_plus:VHB (match_operand:VHB 1 "register_operand" "f") (match_operand:VHB 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "paddus\t%0,%1,%2" [(set_attr "type" "fadd")]) ;; Logical AND NOT. (define_insn "loongson_pandn_" [(set (match_operand:VWHBDI 0 "register_operand" "=f") - (and:VWHBDI + (and:VWHBDI (not:VWHBDI (match_operand:VWHBDI 1 "register_operand" "f")) (match_operand:VWHBDI 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "pandn\t%0,%1,%2" [(set_attr "type" "fmul")]) @@ -233,7 +232,7 @@ [(set (match_operand:VWHB 0 "register_operand" "=f") (and:VWHB (match_operand:VWHB 1 "register_operand" "f") (match_operand:VWHB 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "and\t%0,%1,%2" [(set_attr "type" "fmul")]) @@ -242,7 +241,7 @@ [(set (match_operand:VWHB 0 "register_operand" "=f") (ior:VWHB (match_operand:VWHB 1 "register_operand" "f") (match_operand:VWHB 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "or\t%0,%1,%2" [(set_attr "type" "fcvt")]) @@ -251,7 +250,7 @@ [(set (match_operand:VWHB 0 "register_operand" "=f") (xor:VWHB (match_operand:VWHB 1 "register_operand" "f") (match_operand:VWHB 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "xor\t%0,%1,%2" [(set_attr "type" "fmul")]) @@ -261,7 +260,7 @@ (and:VWHB (not:VWHB (match_operand:VWHB 1 "register_operand" "f")) (not:VWHB (match_operand:VWHB 2 "register_operand" "f"))))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "nor\t%0,%1,%2" [(set_attr "type" "fmul")]) @@ -269,47 +268,47 @@ (define_insn "one_cmpl2" [(set (match_operand:VWHB 0 "register_operand" "=f") (not:VWHB (match_operand:VWHB 1 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "nor\t%0,%1,%1" [(set_attr "type" "fmul")]) ;; Average. (define_insn "loongson_pavg" [(set (match_operand:VHB 0 "register_operand" "=f") - (unspec:VHB [(match_operand:VHB 1 "register_operand" "f") + (unspec:VHB [(match_operand:VHB 1 "register_operand" "f") (match_operand:VHB 2 "register_operand" "f")] UNSPEC_LOONGSON_PAVG))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "pavg\t%0,%1,%2" [(set_attr "type" "fadd")]) ;; Equality test. (define_insn "loongson_pcmpeq" [(set (match_operand:VWHB 0 "register_operand" "=f") - (unspec:VWHB [(match_operand:VWHB 1 "register_operand" "f") + (unspec:VWHB [(match_operand:VWHB 1 "register_operand" "f") (match_operand:VWHB 2 "register_operand" "f")] UNSPEC_LOONGSON_PCMPEQ))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "pcmpeq\t%0,%1,%2" [(set_attr "type" "fadd")]) ;; Greater-than test. (define_insn "loongson_pcmpgt" [(set (match_operand:VWHB 0 "register_operand" "=f") - (unspec:VWHB [(match_operand:VWHB 1 "register_operand" "f") + (unspec:VWHB [(match_operand:VWHB 1 "register_operand" "f") (match_operand:VWHB 2 "register_operand" "f")] UNSPEC_LOONGSON_PCMPGT))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "pcmpgt\t%0,%1,%2" [(set_attr "type" "fadd")]) ;; Extract halfword. (define_insn "loongson_pextrh" [(set (match_operand:V4HI 0 "register_operand" "=f") - (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "f") + (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "f") (match_operand:SI 2 "register_operand" "f")] UNSPEC_LOONGSON_PEXTR))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "pextrh\t%0,%1,%2" [(set_attr "type" "fcvt")]) @@ -322,7 +321,7 @@ (match_operand:V4HI 2 "register_operand" "f")) (parallel [(const_int 4) (const_int 1) (const_int 2) (const_int 3)])))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "pinsrh_0\t%0,%1,%2" [(set_attr "type" "fdiv")]) @@ -334,7 +333,7 @@ (match_operand:V4HI 2 "register_operand" "f")) (parallel [(const_int 0) (const_int 4) (const_int 2) (const_int 3)])))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "pinsrh_1\t%0,%1,%2" [(set_attr "type" "fdiv")]) @@ -346,7 +345,7 @@ (match_operand:V4HI 2 "register_operand" "f")) (parallel [(const_int 0) (const_int 1) (const_int 4) (const_int 3)])))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "pinsrh_2\t%0,%1,%2" [(set_attr "type" "fdiv")]) @@ -358,7 +357,7 @@ (match_operand:V4HI 2 "register_operand" "f")) (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 4)])))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "pinsrh_3\t%0,%1,%2" [(set_attr "type" "fdiv")]) @@ -368,7 +367,7 @@ (match_operand:SI 2 "register_operand" "f") (match_operand:SI 3 "const_0_to_3_operand" "")] UNSPEC_LOONGSON_PINSRH))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "pinsrh_%3\t%0,%1,%2" [(set_attr "type" "fdiv")]) @@ -378,7 +377,7 @@ (match_operand:HI 2 "register_operand" "f") (match_operand:SI 3 "const_0_to_3_operand" "")] UNSPEC_LOONGSON_PINSRH))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" { rtx ext = gen_reg_rtx (SImode); emit_move_insn (ext, gen_lowpart (SImode, operands[2])); @@ -388,10 +387,10 @@ ;; Multiply and add packed integers. (define_insn "loongson_pmaddhw" [(set (match_operand:V2SI 0 "register_operand" "=f") - (unspec:V2SI [(match_operand:V4HI 1 "register_operand" "f") + (unspec:V2SI [(match_operand:V4HI 1 "register_operand" "f") (match_operand:V4HI 2 "register_operand" "f")] UNSPEC_LOONGSON_PMADD))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "pmaddhw\t%0,%1,%2" [(set_attr "type" "fmul")]) @@ -400,7 +399,7 @@ (match_operand:V4HI 1 "register_operand" "") (match_operand:V4HI 2 "register_operand" "") (match_operand:V2SI 3 "register_operand" "")] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" { rtx t = gen_reg_rtx (V2SImode); emit_insn (gen_loongson_pmaddhw (t, operands[1], operands[2])); @@ -411,9 +410,9 @@ ;; Maximum of signed halfwords. (define_insn "smaxv4hi3" [(set (match_operand:V4HI 0 "register_operand" "=f") - (smax:V4HI (match_operand:V4HI 1 "register_operand" "f") + (smax:V4HI (match_operand:V4HI 1 "register_operand" "f") (match_operand:V4HI 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "pmaxsh\t%0,%1,%2" [(set_attr "type" "fadd")]) @@ -421,7 +420,7 @@ [(match_operand:VWB 0 "register_operand" "") (match_operand:VWB 1 "register_operand" "") (match_operand:VWB 2 "register_operand" "")] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" { mips_expand_vec_minmax (operands[0], operands[1], operands[2], gen_loongson_pcmpgt, false); @@ -431,18 +430,18 @@ ;; Maximum of unsigned bytes. (define_insn "umaxv8qi3" [(set (match_operand:V8QI 0 "register_operand" "=f") - (umax:V8QI (match_operand:V8QI 1 "register_operand" "f") + (umax:V8QI (match_operand:V8QI 1 "register_operand" "f") (match_operand:V8QI 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "pmaxub\t%0,%1,%2" [(set_attr "type" "fadd")]) ;; Minimum of signed halfwords. (define_insn "sminv4hi3" [(set (match_operand:V4HI 0 "register_operand" "=f") - (smin:V4HI (match_operand:V4HI 1 "register_operand" "f") + (smin:V4HI (match_operand:V4HI 1 "register_operand" "f") (match_operand:V4HI 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "pminsh\t%0,%1,%2" [(set_attr "type" "fadd")]) @@ -450,7 +449,7 @@ [(match_operand:VWB 0 "register_operand" "") (match_operand:VWB 1 "register_operand" "") (match_operand:VWB 2 "register_operand" "")] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" { mips_expand_vec_minmax (operands[0], operands[1], operands[2], gen_loongson_pcmpgt, true); @@ -460,76 +459,76 @@ ;; Minimum of unsigned bytes. (define_insn "uminv8qi3" [(set (match_operand:V8QI 0 "register_operand" "=f") - (umin:V8QI (match_operand:V8QI 1 "register_operand" "f") + (umin:V8QI (match_operand:V8QI 1 "register_operand" "f") (match_operand:V8QI 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "pminub\t%0,%1,%2" [(set_attr "type" "fadd")]) ;; Move byte mask. (define_insn "loongson_pmovmsk" [(set (match_operand:VB 0 "register_operand" "=f") - (unspec:VB [(match_operand:VB 1 "register_operand" "f")] + (unspec:VB [(match_operand:VB 1 "register_operand" "f")] UNSPEC_LOONGSON_PMOVMSK))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "pmovmsk\t%0,%1" [(set_attr "type" "fabs")]) ;; Multiply unsigned integers and store high result. (define_insn "umul3_highpart" [(set (match_operand:VH 0 "register_operand" "=f") - (unspec:VH [(match_operand:VH 1 "register_operand" "f") + (unspec:VH [(match_operand:VH 1 "register_operand" "f") (match_operand:VH 2 "register_operand" "f")] UNSPEC_LOONGSON_PMULHU))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "pmulhu\t%0,%1,%2" [(set_attr "type" "fmul")]) ;; Multiply signed integers and store high result. (define_insn "smul3_highpart" [(set (match_operand:VH 0 "register_operand" "=f") - (unspec:VH [(match_operand:VH 1 "register_operand" "f") + (unspec:VH [(match_operand:VH 1 "register_operand" "f") (match_operand:VH 2 "register_operand" "f")] UNSPEC_LOONGSON_PMULH))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "pmulh\t%0,%1,%2" [(set_attr "type" "fmul")]) ;; Multiply signed integers and store low result. (define_insn "mul3" [(set (match_operand:VH 0 "register_operand" "=f") - (mult:VH (match_operand:VH 1 "register_operand" "f") - (match_operand:VH 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + (mult:VH (match_operand:VH 1 "register_operand" "f") + (match_operand:VH 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "pmull\t%0,%1,%2" [(set_attr "type" "fmul")]) ;; Multiply unsigned word integers. (define_insn "loongson_pmulu" [(set (match_operand:DI 0 "register_operand" "=f") - (unspec:DI [(match_operand:VW 1 "register_operand" "f") + (unspec:DI [(match_operand:VW 1 "register_operand" "f") (match_operand:VW 2 "register_operand" "f")] UNSPEC_LOONGSON_PMULU))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "pmulu\t%0,%1,%2" [(set_attr "type" "fmul")]) ;; Absolute difference. (define_insn "loongson_pasubub" [(set (match_operand:VB 0 "register_operand" "=f") - (unspec:VB [(match_operand:VB 1 "register_operand" "f") + (unspec:VB [(match_operand:VB 1 "register_operand" "f") (match_operand:VB 2 "register_operand" "f")] UNSPEC_LOONGSON_PASUBUB))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "pasubub\t%0,%1,%2" [(set_attr "type" "fadd")]) ;; Sum of unsigned byte integers. (define_insn "loongson_biadd" [(set (match_operand: 0 "register_operand" "=f") - (unspec: [(match_operand:VB 1 "register_operand" "f")] + (unspec: [(match_operand:VB 1 "register_operand" "f")] UNSPEC_LOONGSON_BIADD))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "biadd\t%0,%1" [(set_attr "type" "fabs")]) @@ -537,63 +536,63 @@ [(set (match_operand:V8QI 0 "register_operand" "=f") (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "f")] UNSPEC_LOONGSON_BIADD))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "biadd\t%0,%1" [(set_attr "type" "fabs")]) ;; Sum of absolute differences. (define_insn "loongson_psadbh" [(set (match_operand: 0 "register_operand" "=f") - (unspec: [(match_operand:VB 1 "register_operand" "f") + (unspec: [(match_operand:VB 1 "register_operand" "f") (match_operand:VB 2 "register_operand" "f")] UNSPEC_LOONGSON_PSADBH))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "pasubub\t%0,%1,%2;biadd\t%0,%0" [(set_attr "type" "fadd")]) ;; Shuffle halfwords. (define_insn "loongson_pshufh" [(set (match_operand:VH 0 "register_operand" "=f") - (unspec:VH [(match_operand:VH 1 "register_operand" "f") + (unspec:VH [(match_operand:VH 1 "register_operand" "f") (match_operand:SI 2 "register_operand" "f")] UNSPEC_LOONGSON_PSHUFH))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "pshufh\t%0,%1,%2" [(set_attr "type" "fmul")]) ;; Shift left logical. (define_insn "ashl3" [(set (match_operand:VWH 0 "register_operand" "=f") - (ashift:VWH (match_operand:VWH 1 "register_operand" "f") + (ashift:VWH (match_operand:VWH 1 "register_operand" "f") (match_operand:SI 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "psll\t%0,%1,%2" [(set_attr "type" "fcvt")]) ;; Shift right arithmetic. (define_insn "ashr3" [(set (match_operand:VWH 0 "register_operand" "=f") - (ashiftrt:VWH (match_operand:VWH 1 "register_operand" "f") + (ashiftrt:VWH (match_operand:VWH 1 "register_operand" "f") (match_operand:SI 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "psra\t%0,%1,%2" [(set_attr "type" "fcvt")]) ;; Shift right logical. (define_insn "lshr3" [(set (match_operand:VWH 0 "register_operand" "=f") - (lshiftrt:VWH (match_operand:VWH 1 "register_operand" "f") + (lshiftrt:VWH (match_operand:VWH 1 "register_operand" "f") (match_operand:SI 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "psrl\t%0,%1,%2" [(set_attr "type" "fcvt")]) ;; Subtraction, treating overflow by wraparound. (define_insn "sub3" [(set (match_operand:VWHB 0 "register_operand" "=f") - (minus:VWHB (match_operand:VWHB 1 "register_operand" "f") + (minus:VWHB (match_operand:VWHB 1 "register_operand" "f") (match_operand:VWHB 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "psub\t%0,%1,%2" [(set_attr "type" "fadd")]) @@ -603,28 +602,28 @@ ;; 'minus' here. (define_insn "loongson_psubd" [(set (match_operand:DI 0 "register_operand" "=f") - (unspec:DI [(match_operand:DI 1 "register_operand" "f") + (unspec:DI [(match_operand:DI 1 "register_operand" "f") (match_operand:DI 2 "register_operand" "f")] UNSPEC_LOONGSON_PSUBD))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "psubd\t%0,%1,%2" [(set_attr "type" "fadd")]) ;; Subtraction, treating overflow by signed saturation. (define_insn "sssub3" [(set (match_operand:VHB 0 "register_operand" "=f") - (ss_minus:VHB (match_operand:VHB 1 "register_operand" "f") + (ss_minus:VHB (match_operand:VHB 1 "register_operand" "f") (match_operand:VHB 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "psubs\t%0,%1,%2" [(set_attr "type" "fadd")]) ;; Subtraction, treating overflow by unsigned saturation. (define_insn "ussub3" [(set (match_operand:VHB 0 "register_operand" "=f") - (us_minus:VHB (match_operand:VHB 1 "register_operand" "f") + (us_minus:VHB (match_operand:VHB 1 "register_operand" "f") (match_operand:VHB 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "psubus\t%0,%1,%2" [(set_attr "type" "fadd")]) @@ -639,7 +638,7 @@ (const_int 5) (const_int 13) (const_int 6) (const_int 14) (const_int 7) (const_int 15)])))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "punpckhbh\t%0,%1,%2" [(set_attr "type" "fdiv")]) @@ -651,7 +650,7 @@ (match_operand:V4HI 2 "register_operand" "f")) (parallel [(const_int 2) (const_int 6) (const_int 3) (const_int 7)])))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "punpckhhw\t%0,%1,%2" [(set_attr "type" "fdiv")]) @@ -665,7 +664,7 @@ (const_int 12) (const_int 13) (const_int 6) (const_int 7) (const_int 14) (const_int 15)])))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "punpckhhw\t%0,%1,%2" [(set_attr "type" "fdiv")]) @@ -676,7 +675,7 @@ (match_operand:V2SI 1 "register_operand" "f") (match_operand:V2SI 2 "register_operand" "f")) (parallel [(const_int 1) (const_int 3)])))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "punpckhwd\t%0,%1,%2" [(set_attr "type" "fcvt")]) @@ -690,7 +689,7 @@ (const_int 6) (const_int 7) (const_int 12) (const_int 13) (const_int 14) (const_int 15)])))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "punpckhwd\t%0,%1,%2" [(set_attr "type" "fcvt")]) @@ -702,7 +701,7 @@ (match_operand:V4HI 2 "register_operand" "f")) (parallel [(const_int 2) (const_int 3) (const_int 6) (const_int 7)])))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "punpckhwd\t%0,%1,%2" [(set_attr "type" "fcvt")]) @@ -717,7 +716,7 @@ (const_int 1) (const_int 9) (const_int 2) (const_int 10) (const_int 3) (const_int 11)])))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "punpcklbh\t%0,%1,%2" [(set_attr "type" "fdiv")]) @@ -729,7 +728,7 @@ (match_operand:V4HI 2 "register_operand" "f")) (parallel [(const_int 0) (const_int 4) (const_int 1) (const_int 5)])))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "punpcklhw\t%0,%1,%2" [(set_attr "type" "fdiv")]) @@ -743,7 +742,7 @@ (const_int 8) (const_int 9) (const_int 2) (const_int 3) (const_int 10) (const_int 11)])))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "punpcklhw\t%0,%1,%2" [(set_attr "type" "fdiv")]) @@ -754,7 +753,7 @@ (match_operand:V2SI 1 "register_operand" "f") (match_operand:V2SI 2 "register_operand" "f")) (parallel [(const_int 0) (const_int 2)])))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "punpcklwd\t%0,%1,%2" [(set_attr "type" "fcvt")]) @@ -768,7 +767,7 @@ (const_int 2) (const_int 3) (const_int 8) (const_int 9) (const_int 10) (const_int 11)])))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "punpcklwd\t%0,%1,%2" [(set_attr "type" "fcvt")]) @@ -780,14 +779,14 @@ (match_operand:V4HI 2 "register_operand" "f")) (parallel [(const_int 0) (const_int 1) (const_int 4) (const_int 5)])))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "punpcklwd\t%0,%1,%2" [(set_attr "type" "fcvt")]) (define_expand "vec_unpacks_lo_" [(match_operand: 0 "register_operand" "") (match_operand:VHB 1 "register_operand" "")] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" { mips_expand_vec_unpack (operands, false, false); DONE; @@ -796,7 +795,7 @@ (define_expand "vec_unpacks_hi_" [(match_operand: 0 "register_operand" "") (match_operand:VHB 1 "register_operand" "")] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" { mips_expand_vec_unpack (operands, false, true); DONE; @@ -805,7 +804,7 @@ (define_expand "vec_unpacku_lo_" [(match_operand: 0 "register_operand" "") (match_operand:VHB 1 "register_operand" "")] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" { mips_expand_vec_unpack (operands, true, false); DONE; @@ -814,7 +813,7 @@ (define_expand "vec_unpacku_hi_" [(match_operand: 0 "register_operand" "") (match_operand:VHB 1 "register_operand" "")] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" { mips_expand_vec_unpack (operands, true, true); DONE; @@ -823,35 +822,35 @@ ;; Whole vector shifts, used for reduction epilogues. (define_insn "vec_shl_" [(set (match_operand:VWHBDI 0 "register_operand" "=f") - (unspec:VWHBDI [(match_operand:VWHBDI 1 "register_operand" "f") - (match_operand:SI 2 "register_operand" "f")] - UNSPEC_LOONGSON_DSLL))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + (unspec:VWHBDI [(match_operand:VWHBDI 1 "register_operand" "f") + (match_operand:SI 2 "register_operand" "f")] + UNSPEC_LOONGSON_DSLL))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "dsll\t%0,%1,%2" [(set_attr "type" "fcvt")]) (define_insn "vec_shr_" [(set (match_operand:VWHBDI 0 "register_operand" "=f") - (unspec:VWHBDI [(match_operand:VWHBDI 1 "register_operand" "f") - (match_operand:SI 2 "register_operand" "f")] - UNSPEC_LOONGSON_DSRL))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + (unspec:VWHBDI [(match_operand:VWHBDI 1 "register_operand" "f") + (match_operand:SI 2 "register_operand" "f")] + UNSPEC_LOONGSON_DSRL))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "dsrl\t%0,%1,%2" [(set_attr "type" "fcvt")]) (define_insn "vec_loongson_extract_lo_" [(set (match_operand: 0 "register_operand" "=r") - (vec_select: - (match_operand:VWHB 1 "register_operand" "f") - (parallel [(const_int 0)])))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + (vec_select: + (match_operand:VWHB 1 "register_operand" "f") + (parallel [(const_int 0)])))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" "mfc1\t%0,%1" [(set_attr "type" "mfc")]) (define_expand "reduc_plus_scal_" [(match_operand: 0 "register_operand" "") (match_operand:VWHB 1 "register_operand" "")] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" { rtx tmp = gen_reg_rtx (GET_MODE (operands[1])); mips_expand_vec_reduc (tmp, operands[1], gen_add3); @@ -862,7 +861,7 @@ (define_expand "reduc_smax_scal_" [(match_operand: 0 "register_operand" "") (match_operand:VWHB 1 "register_operand" "")] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" { rtx tmp = gen_reg_rtx (GET_MODE (operands[1])); mips_expand_vec_reduc (tmp, operands[1], gen_smax3); @@ -873,7 +872,7 @@ (define_expand "reduc_smin_scal_" [(match_operand: 0 "register_operand" "") (match_operand:VWHB 1 "register_operand" "")] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" { rtx tmp = gen_reg_rtx (GET_MODE (operands[1])); mips_expand_vec_reduc (tmp, operands[1], gen_smin3); @@ -884,7 +883,7 @@ (define_expand "reduc_umax_scal_" [(match_operand: 0 "register_operand" "") (match_operand:VB 1 "register_operand" "")] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" { rtx tmp = gen_reg_rtx (GET_MODE (operands[1])); mips_expand_vec_reduc (tmp, operands[1], gen_umax3); @@ -895,7 +894,7 @@ (define_expand "reduc_umin_scal_" [(match_operand: 0 "register_operand" "") (match_operand:VB 1 "register_operand" "")] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" { rtx tmp = gen_reg_rtx (GET_MODE (operands[1])); mips_expand_vec_reduc (tmp, operands[1], gen_umin3); diff --git a/gcc/config/mips/loongson-mmiintrin.h b/gcc/config/mips/loongson-mmiintrin.h new file mode 100644 index 00000000000..6f35fb5b842 --- /dev/null +++ b/gcc/config/mips/loongson-mmiintrin.h @@ -0,0 +1,691 @@ +/* Intrinsics for Loongson MultiMedia extension Instructions operations. + + Copyright (C) 2008-2018 Free Software Foundation, Inc. + Contributed by CodeSourcery. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + +#ifndef _GCC_LOONGSON_MMIINTRIN_H +#define _GCC_LOONGSON_MMIINTRIN_H + +#if !defined(__mips_loongson_mmi) +# error "You must select -mloongson-mmi or -march=loongson2e/2f/3a to use + loongson-mmiintrin.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* Vectors of unsigned bytes, halfwords and words. */ +typedef uint8_t uint8x8_t __attribute__((vector_size (8))); +typedef uint16_t uint16x4_t __attribute__((vector_size (8))); +typedef uint32_t uint32x2_t __attribute__((vector_size (8))); + +/* Vectors of signed bytes, halfwords and words. */ +typedef int8_t int8x8_t __attribute__((vector_size (8))); +typedef int16_t int16x4_t __attribute__((vector_size (8))); +typedef int32_t int32x2_t __attribute__((vector_size (8))); + +/* SIMD intrinsics. + Unless otherwise noted, calls to the functions below will expand into + precisely one machine instruction, modulo any moves required to + satisfy register allocation constraints. */ + +/* Pack with signed saturation. */ +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +packsswh (int32x2_t s, int32x2_t t) +{ + return __builtin_loongson_packsswh (s, t); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +packsshb (int16x4_t s, int16x4_t t) +{ + return __builtin_loongson_packsshb (s, t); +} + +/* Pack with unsigned saturation. */ +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +packushb (uint16x4_t s, uint16x4_t t) +{ + return __builtin_loongson_packushb (s, t); +} + +/* Vector addition, treating overflow by wraparound. */ +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +paddw_u (uint32x2_t s, uint32x2_t t) +{ + return __builtin_loongson_paddw_u (s, t); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +paddh_u (uint16x4_t s, uint16x4_t t) +{ + return __builtin_loongson_paddh_u (s, t); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +paddb_u (uint8x8_t s, uint8x8_t t) +{ + return __builtin_loongson_paddb_u (s, t); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +paddw_s (int32x2_t s, int32x2_t t) +{ + return __builtin_loongson_paddw_s (s, t); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +paddh_s (int16x4_t s, int16x4_t t) +{ + return __builtin_loongson_paddh_s (s, t); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +paddb_s (int8x8_t s, int8x8_t t) +{ + return __builtin_loongson_paddb_s (s, t); +} + +/* Addition of doubleword integers, treating overflow by wraparound. */ +__extension__ static __inline uint64_t __attribute__ ((__always_inline__)) +paddd_u (uint64_t s, uint64_t t) +{ + return __builtin_loongson_paddd_u (s, t); +} + +__extension__ static __inline int64_t __attribute__ ((__always_inline__)) +paddd_s (int64_t s, int64_t t) +{ + return __builtin_loongson_paddd_s (s, t); +} + +/* Vector addition, treating overflow by signed saturation. */ +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +paddsh (int16x4_t s, int16x4_t t) +{ + return __builtin_loongson_paddsh (s, t); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +paddsb (int8x8_t s, int8x8_t t) +{ + return __builtin_loongson_paddsb (s, t); +} + +/* Vector addition, treating overflow by unsigned saturation. */ +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +paddush (uint16x4_t s, uint16x4_t t) +{ + return __builtin_loongson_paddush (s, t); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +paddusb (uint8x8_t s, uint8x8_t t) +{ + return __builtin_loongson_paddusb (s, t); +} + +/* Logical AND NOT. */ +__extension__ static __inline uint64_t __attribute__ ((__always_inline__)) +pandn_ud (uint64_t s, uint64_t t) +{ + return __builtin_loongson_pandn_ud (s, t); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +pandn_uw (uint32x2_t s, uint32x2_t t) +{ + return __builtin_loongson_pandn_uw (s, t); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +pandn_uh (uint16x4_t s, uint16x4_t t) +{ + return __builtin_loongson_pandn_uh (s, t); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +pandn_ub (uint8x8_t s, uint8x8_t t) +{ + return __builtin_loongson_pandn_ub (s, t); +} + +__extension__ static __inline int64_t __attribute__ ((__always_inline__)) +pandn_sd (int64_t s, int64_t t) +{ + return __builtin_loongson_pandn_sd (s, t); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +pandn_sw (int32x2_t s, int32x2_t t) +{ + return __builtin_loongson_pandn_sw (s, t); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +pandn_sh (int16x4_t s, int16x4_t t) +{ + return __builtin_loongson_pandn_sh (s, t); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +pandn_sb (int8x8_t s, int8x8_t t) +{ + return __builtin_loongson_pandn_sb (s, t); +} + +/* Average. */ +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +pavgh (uint16x4_t s, uint16x4_t t) +{ + return __builtin_loongson_pavgh (s, t); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +pavgb (uint8x8_t s, uint8x8_t t) +{ + return __builtin_loongson_pavgb (s, t); +} + +/* Equality test. */ +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +pcmpeqw_u (uint32x2_t s, uint32x2_t t) +{ + return __builtin_loongson_pcmpeqw_u (s, t); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +pcmpeqh_u (uint16x4_t s, uint16x4_t t) +{ + return __builtin_loongson_pcmpeqh_u (s, t); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +pcmpeqb_u (uint8x8_t s, uint8x8_t t) +{ + return __builtin_loongson_pcmpeqb_u (s, t); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +pcmpeqw_s (int32x2_t s, int32x2_t t) +{ + return __builtin_loongson_pcmpeqw_s (s, t); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +pcmpeqh_s (int16x4_t s, int16x4_t t) +{ + return __builtin_loongson_pcmpeqh_s (s, t); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +pcmpeqb_s (int8x8_t s, int8x8_t t) +{ + return __builtin_loongson_pcmpeqb_s (s, t); +} + +/* Greater-than test. */ +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +pcmpgtw_u (uint32x2_t s, uint32x2_t t) +{ + return __builtin_loongson_pcmpgtw_u (s, t); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +pcmpgth_u (uint16x4_t s, uint16x4_t t) +{ + return __builtin_loongson_pcmpgth_u (s, t); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +pcmpgtb_u (uint8x8_t s, uint8x8_t t) +{ + return __builtin_loongson_pcmpgtb_u (s, t); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +pcmpgtw_s (int32x2_t s, int32x2_t t) +{ + return __builtin_loongson_pcmpgtw_s (s, t); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +pcmpgth_s (int16x4_t s, int16x4_t t) +{ + return __builtin_loongson_pcmpgth_s (s, t); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +pcmpgtb_s (int8x8_t s, int8x8_t t) +{ + return __builtin_loongson_pcmpgtb_s (s, t); +} + +/* Extract halfword. */ +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +pextrh_u (uint16x4_t s, int field /* 0--3. */) +{ + return __builtin_loongson_pextrh_u (s, field); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +pextrh_s (int16x4_t s, int field /* 0--3. */) +{ + return __builtin_loongson_pextrh_s (s, field); +} + +/* Insert halfword. */ +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +pinsrh_0_u (uint16x4_t s, uint16x4_t t) +{ + return __builtin_loongson_pinsrh_0_u (s, t); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +pinsrh_1_u (uint16x4_t s, uint16x4_t t) +{ + return __builtin_loongson_pinsrh_1_u (s, t); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +pinsrh_2_u (uint16x4_t s, uint16x4_t t) +{ + return __builtin_loongson_pinsrh_2_u (s, t); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +pinsrh_3_u (uint16x4_t s, uint16x4_t t) +{ + return __builtin_loongson_pinsrh_3_u (s, t); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +pinsrh_0_s (int16x4_t s, int16x4_t t) +{ + return __builtin_loongson_pinsrh_0_s (s, t); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +pinsrh_1_s (int16x4_t s, int16x4_t t) +{ + return __builtin_loongson_pinsrh_1_s (s, t); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +pinsrh_2_s (int16x4_t s, int16x4_t t) +{ + return __builtin_loongson_pinsrh_2_s (s, t); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +pinsrh_3_s (int16x4_t s, int16x4_t t) +{ + return __builtin_loongson_pinsrh_3_s (s, t); +} + +/* Multiply and add. */ +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +pmaddhw (int16x4_t s, int16x4_t t) +{ + return __builtin_loongson_pmaddhw (s, t); +} + +/* Maximum of signed halfwords. */ +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +pmaxsh (int16x4_t s, int16x4_t t) +{ + return __builtin_loongson_pmaxsh (s, t); +} + +/* Maximum of unsigned bytes. */ +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +pmaxub (uint8x8_t s, uint8x8_t t) +{ + return __builtin_loongson_pmaxub (s, t); +} + +/* Minimum of signed halfwords. */ +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +pminsh (int16x4_t s, int16x4_t t) +{ + return __builtin_loongson_pminsh (s, t); +} + +/* Minimum of unsigned bytes. */ +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +pminub (uint8x8_t s, uint8x8_t t) +{ + return __builtin_loongson_pminub (s, t); +} + +/* Move byte mask. */ +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +pmovmskb_u (uint8x8_t s) +{ + return __builtin_loongson_pmovmskb_u (s); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +pmovmskb_s (int8x8_t s) +{ + return __builtin_loongson_pmovmskb_s (s); +} + +/* Multiply unsigned integers and store high result. */ +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +pmulhuh (uint16x4_t s, uint16x4_t t) +{ + return __builtin_loongson_pmulhuh (s, t); +} + +/* Multiply signed integers and store high result. */ +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +pmulhh (int16x4_t s, int16x4_t t) +{ + return __builtin_loongson_pmulhh (s, t); +} + +/* Multiply signed integers and store low result. */ +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +pmullh (int16x4_t s, int16x4_t t) +{ + return __builtin_loongson_pmullh (s, t); +} + +/* Multiply unsigned word integers. */ +__extension__ static __inline int64_t __attribute__ ((__always_inline__)) +pmuluw (uint32x2_t s, uint32x2_t t) +{ + return __builtin_loongson_pmuluw (s, t); +} + +/* Absolute difference. */ +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +pasubub (uint8x8_t s, uint8x8_t t) +{ + return __builtin_loongson_pasubub (s, t); +} + +/* Sum of unsigned byte integers. */ +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +biadd (uint8x8_t s) +{ + return __builtin_loongson_biadd (s); +} + +/* Sum of absolute differences. + Note that this intrinsic expands into two machine instructions: + PASUBUB followed by BIADD. */ +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +psadbh (uint8x8_t s, uint8x8_t t) +{ + return __builtin_loongson_psadbh (s, t); +} + +/* Shuffle halfwords. */ +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +pshufh_u (uint16x4_t dest, uint16x4_t s, uint8_t order) +{ + return __builtin_loongson_pshufh_u (s, order); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +pshufh_s (int16x4_t dest, int16x4_t s, uint8_t order) +{ + return __builtin_loongson_pshufh_s (s, order); +} + +/* Shift left logical. */ +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +psllh_u (uint16x4_t s, uint8_t amount) +{ + return __builtin_loongson_psllh_u (s, amount); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +psllh_s (int16x4_t s, uint8_t amount) +{ + return __builtin_loongson_psllh_s (s, amount); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +psllw_u (uint32x2_t s, uint8_t amount) +{ + return __builtin_loongson_psllw_u (s, amount); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +psllw_s (int32x2_t s, uint8_t amount) +{ + return __builtin_loongson_psllw_s (s, amount); +} + +/* Shift right logical. */ +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +psrlh_u (uint16x4_t s, uint8_t amount) +{ + return __builtin_loongson_psrlh_u (s, amount); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +psrlh_s (int16x4_t s, uint8_t amount) +{ + return __builtin_loongson_psrlh_s (s, amount); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +psrlw_u (uint32x2_t s, uint8_t amount) +{ + return __builtin_loongson_psrlw_u (s, amount); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +psrlw_s (int32x2_t s, uint8_t amount) +{ + return __builtin_loongson_psrlw_s (s, amount); +} + +/* Shift right arithmetic. */ +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +psrah_u (uint16x4_t s, uint8_t amount) +{ + return __builtin_loongson_psrah_u (s, amount); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +psrah_s (int16x4_t s, uint8_t amount) +{ + return __builtin_loongson_psrah_s (s, amount); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +psraw_u (uint32x2_t s, uint8_t amount) +{ + return __builtin_loongson_psraw_u (s, amount); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +psraw_s (int32x2_t s, uint8_t amount) +{ + return __builtin_loongson_psraw_s (s, amount); +} + +/* Vector subtraction, treating overflow by wraparound. */ +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +psubw_u (uint32x2_t s, uint32x2_t t) +{ + return __builtin_loongson_psubw_u (s, t); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +psubh_u (uint16x4_t s, uint16x4_t t) +{ + return __builtin_loongson_psubh_u (s, t); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +psubb_u (uint8x8_t s, uint8x8_t t) +{ + return __builtin_loongson_psubb_u (s, t); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +psubw_s (int32x2_t s, int32x2_t t) +{ + return __builtin_loongson_psubw_s (s, t); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +psubh_s (int16x4_t s, int16x4_t t) +{ + return __builtin_loongson_psubh_s (s, t); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +psubb_s (int8x8_t s, int8x8_t t) +{ + return __builtin_loongson_psubb_s (s, t); +} + +/* Subtraction of doubleword integers, treating overflow by wraparound. */ +__extension__ static __inline uint64_t __attribute__ ((__always_inline__)) +psubd_u (uint64_t s, uint64_t t) +{ + return __builtin_loongson_psubd_u (s, t); +} + +__extension__ static __inline int64_t __attribute__ ((__always_inline__)) +psubd_s (int64_t s, int64_t t) +{ + return __builtin_loongson_psubd_s (s, t); +} + +/* Vector subtraction, treating overflow by signed saturation. */ +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +psubsh (int16x4_t s, int16x4_t t) +{ + return __builtin_loongson_psubsh (s, t); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +psubsb (int8x8_t s, int8x8_t t) +{ + return __builtin_loongson_psubsb (s, t); +} + +/* Vector subtraction, treating overflow by unsigned saturation. */ +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +psubush (uint16x4_t s, uint16x4_t t) +{ + return __builtin_loongson_psubush (s, t); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +psubusb (uint8x8_t s, uint8x8_t t) +{ + return __builtin_loongson_psubusb (s, t); +} + +/* Unpack high data. */ +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +punpckhwd_u (uint32x2_t s, uint32x2_t t) +{ + return __builtin_loongson_punpckhwd_u (s, t); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +punpckhhw_u (uint16x4_t s, uint16x4_t t) +{ + return __builtin_loongson_punpckhhw_u (s, t); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +punpckhbh_u (uint8x8_t s, uint8x8_t t) +{ + return __builtin_loongson_punpckhbh_u (s, t); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +punpckhwd_s (int32x2_t s, int32x2_t t) +{ + return __builtin_loongson_punpckhwd_s (s, t); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +punpckhhw_s (int16x4_t s, int16x4_t t) +{ + return __builtin_loongson_punpckhhw_s (s, t); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +punpckhbh_s (int8x8_t s, int8x8_t t) +{ + return __builtin_loongson_punpckhbh_s (s, t); +} + +/* Unpack low data. */ +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +punpcklwd_u (uint32x2_t s, uint32x2_t t) +{ + return __builtin_loongson_punpcklwd_u (s, t); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +punpcklhw_u (uint16x4_t s, uint16x4_t t) +{ + return __builtin_loongson_punpcklhw_u (s, t); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +punpcklbh_u (uint8x8_t s, uint8x8_t t) +{ + return __builtin_loongson_punpcklbh_u (s, t); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +punpcklwd_s (int32x2_t s, int32x2_t t) +{ + return __builtin_loongson_punpcklwd_s (s, t); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +punpcklhw_s (int16x4_t s, int16x4_t t) +{ + return __builtin_loongson_punpcklhw_s (s, t); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +punpcklbh_s (int8x8_t s, int8x8_t t) +{ + return __builtin_loongson_punpcklbh_s (s, t); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/gcc/config/mips/loongson.h b/gcc/config/mips/loongson.h index b4a26027c24..3880e4cb77f 100644 --- a/gcc/config/mips/loongson.h +++ b/gcc/config/mips/loongson.h @@ -1,4 +1,4 @@ -/* Intrinsics for ST Microelectronics Loongson-2E/2F SIMD operations. +/* Intrinsics for Loongson MultiMedia extension Instructions operations. Copyright (C) 2008-2018 Free Software Foundation, Inc. Contributed by CodeSourcery. @@ -24,667 +24,10 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see . */ -#ifndef _GCC_LOONGSON_H -#define _GCC_LOONGSON_H - -#if !defined(__mips_loongson_vector_rev) -# error "You must select -march=loongson2e or -march=loongson2f to use loongson.h" -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* Vectors of unsigned bytes, halfwords and words. */ -typedef uint8_t uint8x8_t __attribute__((vector_size (8))); -typedef uint16_t uint16x4_t __attribute__((vector_size (8))); -typedef uint32_t uint32x2_t __attribute__((vector_size (8))); - -/* Vectors of signed bytes, halfwords and words. */ -typedef int8_t int8x8_t __attribute__((vector_size (8))); -typedef int16_t int16x4_t __attribute__((vector_size (8))); -typedef int32_t int32x2_t __attribute__((vector_size (8))); - -/* SIMD intrinsics. - Unless otherwise noted, calls to the functions below will expand into - precisely one machine instruction, modulo any moves required to - satisfy register allocation constraints. */ - -/* Pack with signed saturation. */ -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -packsswh (int32x2_t s, int32x2_t t) -{ - return __builtin_loongson_packsswh (s, t); -} - -__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -packsshb (int16x4_t s, int16x4_t t) -{ - return __builtin_loongson_packsshb (s, t); -} - -/* Pack with unsigned saturation. */ -__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -packushb (uint16x4_t s, uint16x4_t t) -{ - return __builtin_loongson_packushb (s, t); -} - -/* Vector addition, treating overflow by wraparound. */ -__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -paddw_u (uint32x2_t s, uint32x2_t t) -{ - return __builtin_loongson_paddw_u (s, t); -} - -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -paddh_u (uint16x4_t s, uint16x4_t t) -{ - return __builtin_loongson_paddh_u (s, t); -} - -__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -paddb_u (uint8x8_t s, uint8x8_t t) -{ - return __builtin_loongson_paddb_u (s, t); -} - -__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -paddw_s (int32x2_t s, int32x2_t t) -{ - return __builtin_loongson_paddw_s (s, t); -} - -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -paddh_s (int16x4_t s, int16x4_t t) -{ - return __builtin_loongson_paddh_s (s, t); -} - -__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -paddb_s (int8x8_t s, int8x8_t t) -{ - return __builtin_loongson_paddb_s (s, t); -} - -/* Addition of doubleword integers, treating overflow by wraparound. */ -__extension__ static __inline uint64_t __attribute__ ((__always_inline__)) -paddd_u (uint64_t s, uint64_t t) -{ - return __builtin_loongson_paddd_u (s, t); -} - -__extension__ static __inline int64_t __attribute__ ((__always_inline__)) -paddd_s (int64_t s, int64_t t) -{ - return __builtin_loongson_paddd_s (s, t); -} - -/* Vector addition, treating overflow by signed saturation. */ -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -paddsh (int16x4_t s, int16x4_t t) -{ - return __builtin_loongson_paddsh (s, t); -} - -__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -paddsb (int8x8_t s, int8x8_t t) -{ - return __builtin_loongson_paddsb (s, t); -} - -/* Vector addition, treating overflow by unsigned saturation. */ -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -paddush (uint16x4_t s, uint16x4_t t) -{ - return __builtin_loongson_paddush (s, t); -} - -__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -paddusb (uint8x8_t s, uint8x8_t t) -{ - return __builtin_loongson_paddusb (s, t); -} - -/* Logical AND NOT. */ -__extension__ static __inline uint64_t __attribute__ ((__always_inline__)) -pandn_ud (uint64_t s, uint64_t t) -{ - return __builtin_loongson_pandn_ud (s, t); -} - -__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -pandn_uw (uint32x2_t s, uint32x2_t t) -{ - return __builtin_loongson_pandn_uw (s, t); -} - -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -pandn_uh (uint16x4_t s, uint16x4_t t) -{ - return __builtin_loongson_pandn_uh (s, t); -} - -__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -pandn_ub (uint8x8_t s, uint8x8_t t) -{ - return __builtin_loongson_pandn_ub (s, t); -} - -__extension__ static __inline int64_t __attribute__ ((__always_inline__)) -pandn_sd (int64_t s, int64_t t) -{ - return __builtin_loongson_pandn_sd (s, t); -} - -__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -pandn_sw (int32x2_t s, int32x2_t t) -{ - return __builtin_loongson_pandn_sw (s, t); -} - -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -pandn_sh (int16x4_t s, int16x4_t t) -{ - return __builtin_loongson_pandn_sh (s, t); -} - -__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -pandn_sb (int8x8_t s, int8x8_t t) -{ - return __builtin_loongson_pandn_sb (s, t); -} - -/* Average. */ -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -pavgh (uint16x4_t s, uint16x4_t t) -{ - return __builtin_loongson_pavgh (s, t); -} - -__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -pavgb (uint8x8_t s, uint8x8_t t) -{ - return __builtin_loongson_pavgb (s, t); -} - -/* Equality test. */ -__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -pcmpeqw_u (uint32x2_t s, uint32x2_t t) -{ - return __builtin_loongson_pcmpeqw_u (s, t); -} - -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -pcmpeqh_u (uint16x4_t s, uint16x4_t t) -{ - return __builtin_loongson_pcmpeqh_u (s, t); -} - -__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -pcmpeqb_u (uint8x8_t s, uint8x8_t t) -{ - return __builtin_loongson_pcmpeqb_u (s, t); -} - -__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -pcmpeqw_s (int32x2_t s, int32x2_t t) -{ - return __builtin_loongson_pcmpeqw_s (s, t); -} - -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -pcmpeqh_s (int16x4_t s, int16x4_t t) -{ - return __builtin_loongson_pcmpeqh_s (s, t); -} - -__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -pcmpeqb_s (int8x8_t s, int8x8_t t) -{ - return __builtin_loongson_pcmpeqb_s (s, t); -} - -/* Greater-than test. */ -__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -pcmpgtw_u (uint32x2_t s, uint32x2_t t) -{ - return __builtin_loongson_pcmpgtw_u (s, t); -} - -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -pcmpgth_u (uint16x4_t s, uint16x4_t t) -{ - return __builtin_loongson_pcmpgth_u (s, t); -} - -__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -pcmpgtb_u (uint8x8_t s, uint8x8_t t) -{ - return __builtin_loongson_pcmpgtb_u (s, t); -} - -__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -pcmpgtw_s (int32x2_t s, int32x2_t t) -{ - return __builtin_loongson_pcmpgtw_s (s, t); -} - -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -pcmpgth_s (int16x4_t s, int16x4_t t) -{ - return __builtin_loongson_pcmpgth_s (s, t); -} - -__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -pcmpgtb_s (int8x8_t s, int8x8_t t) -{ - return __builtin_loongson_pcmpgtb_s (s, t); -} - -/* Extract halfword. */ -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -pextrh_u (uint16x4_t s, int field /* 0--3 */) -{ - return __builtin_loongson_pextrh_u (s, field); -} - -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -pextrh_s (int16x4_t s, int field /* 0--3 */) -{ - return __builtin_loongson_pextrh_s (s, field); -} - -/* Insert halfword. */ -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -pinsrh_0_u (uint16x4_t s, uint16x4_t t) -{ - return __builtin_loongson_pinsrh_0_u (s, t); -} - -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -pinsrh_1_u (uint16x4_t s, uint16x4_t t) -{ - return __builtin_loongson_pinsrh_1_u (s, t); -} - -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -pinsrh_2_u (uint16x4_t s, uint16x4_t t) -{ - return __builtin_loongson_pinsrh_2_u (s, t); -} - -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -pinsrh_3_u (uint16x4_t s, uint16x4_t t) -{ - return __builtin_loongson_pinsrh_3_u (s, t); -} - -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -pinsrh_0_s (int16x4_t s, int16x4_t t) -{ - return __builtin_loongson_pinsrh_0_s (s, t); -} - -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -pinsrh_1_s (int16x4_t s, int16x4_t t) -{ - return __builtin_loongson_pinsrh_1_s (s, t); -} - -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -pinsrh_2_s (int16x4_t s, int16x4_t t) -{ - return __builtin_loongson_pinsrh_2_s (s, t); -} - -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -pinsrh_3_s (int16x4_t s, int16x4_t t) -{ - return __builtin_loongson_pinsrh_3_s (s, t); -} - -/* Multiply and add. */ -__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -pmaddhw (int16x4_t s, int16x4_t t) -{ - return __builtin_loongson_pmaddhw (s, t); -} - -/* Maximum of signed halfwords. */ -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -pmaxsh (int16x4_t s, int16x4_t t) -{ - return __builtin_loongson_pmaxsh (s, t); -} - -/* Maximum of unsigned bytes. */ -__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -pmaxub (uint8x8_t s, uint8x8_t t) -{ - return __builtin_loongson_pmaxub (s, t); -} - -/* Minimum of signed halfwords. */ -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -pminsh (int16x4_t s, int16x4_t t) -{ - return __builtin_loongson_pminsh (s, t); -} - -/* Minimum of unsigned bytes. */ -__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -pminub (uint8x8_t s, uint8x8_t t) -{ - return __builtin_loongson_pminub (s, t); -} - -/* Move byte mask. */ -__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -pmovmskb_u (uint8x8_t s) -{ - return __builtin_loongson_pmovmskb_u (s); -} - -__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -pmovmskb_s (int8x8_t s) -{ - return __builtin_loongson_pmovmskb_s (s); -} - -/* Multiply unsigned integers and store high result. */ -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -pmulhuh (uint16x4_t s, uint16x4_t t) -{ - return __builtin_loongson_pmulhuh (s, t); -} - -/* Multiply signed integers and store high result. */ -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -pmulhh (int16x4_t s, int16x4_t t) -{ - return __builtin_loongson_pmulhh (s, t); -} - -/* Multiply signed integers and store low result. */ -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -pmullh (int16x4_t s, int16x4_t t) -{ - return __builtin_loongson_pmullh (s, t); -} - -/* Multiply unsigned word integers. */ -__extension__ static __inline int64_t __attribute__ ((__always_inline__)) -pmuluw (uint32x2_t s, uint32x2_t t) -{ - return __builtin_loongson_pmuluw (s, t); -} - -/* Absolute difference. */ -__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -pasubub (uint8x8_t s, uint8x8_t t) -{ - return __builtin_loongson_pasubub (s, t); -} - -/* Sum of unsigned byte integers. */ -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -biadd (uint8x8_t s) -{ - return __builtin_loongson_biadd (s); -} - -/* Sum of absolute differences. - Note that this intrinsic expands into two machine instructions: - PASUBUB followed by BIADD. */ -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -psadbh (uint8x8_t s, uint8x8_t t) -{ - return __builtin_loongson_psadbh (s, t); -} - -/* Shuffle halfwords. */ -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -pshufh_u (uint16x4_t dest, uint16x4_t s, uint8_t order) -{ - return __builtin_loongson_pshufh_u (s, order); -} - -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -pshufh_s (int16x4_t dest, int16x4_t s, uint8_t order) -{ - return __builtin_loongson_pshufh_s (s, order); -} - -/* Shift left logical. */ -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -psllh_u (uint16x4_t s, uint8_t amount) -{ - return __builtin_loongson_psllh_u (s, amount); -} - -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -psllh_s (int16x4_t s, uint8_t amount) -{ - return __builtin_loongson_psllh_s (s, amount); -} - -__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -psllw_u (uint32x2_t s, uint8_t amount) -{ - return __builtin_loongson_psllw_u (s, amount); -} - -__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -psllw_s (int32x2_t s, uint8_t amount) -{ - return __builtin_loongson_psllw_s (s, amount); -} - -/* Shift right logical. */ -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -psrlh_u (uint16x4_t s, uint8_t amount) -{ - return __builtin_loongson_psrlh_u (s, amount); -} - -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -psrlh_s (int16x4_t s, uint8_t amount) -{ - return __builtin_loongson_psrlh_s (s, amount); -} - -__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -psrlw_u (uint32x2_t s, uint8_t amount) -{ - return __builtin_loongson_psrlw_u (s, amount); -} - -__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -psrlw_s (int32x2_t s, uint8_t amount) -{ - return __builtin_loongson_psrlw_s (s, amount); -} - -/* Shift right arithmetic. */ -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -psrah_u (uint16x4_t s, uint8_t amount) -{ - return __builtin_loongson_psrah_u (s, amount); -} - -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -psrah_s (int16x4_t s, uint8_t amount) -{ - return __builtin_loongson_psrah_s (s, amount); -} - -__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -psraw_u (uint32x2_t s, uint8_t amount) -{ - return __builtin_loongson_psraw_u (s, amount); -} - -__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -psraw_s (int32x2_t s, uint8_t amount) -{ - return __builtin_loongson_psraw_s (s, amount); -} - -/* Vector subtraction, treating overflow by wraparound. */ -__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -psubw_u (uint32x2_t s, uint32x2_t t) -{ - return __builtin_loongson_psubw_u (s, t); -} - -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -psubh_u (uint16x4_t s, uint16x4_t t) -{ - return __builtin_loongson_psubh_u (s, t); -} - -__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -psubb_u (uint8x8_t s, uint8x8_t t) -{ - return __builtin_loongson_psubb_u (s, t); -} - -__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -psubw_s (int32x2_t s, int32x2_t t) -{ - return __builtin_loongson_psubw_s (s, t); -} - -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -psubh_s (int16x4_t s, int16x4_t t) -{ - return __builtin_loongson_psubh_s (s, t); -} - -__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -psubb_s (int8x8_t s, int8x8_t t) -{ - return __builtin_loongson_psubb_s (s, t); -} - -/* Subtraction of doubleword integers, treating overflow by wraparound. */ -__extension__ static __inline uint64_t __attribute__ ((__always_inline__)) -psubd_u (uint64_t s, uint64_t t) -{ - return __builtin_loongson_psubd_u (s, t); -} - -__extension__ static __inline int64_t __attribute__ ((__always_inline__)) -psubd_s (int64_t s, int64_t t) -{ - return __builtin_loongson_psubd_s (s, t); -} - -/* Vector subtraction, treating overflow by signed saturation. */ -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -psubsh (int16x4_t s, int16x4_t t) -{ - return __builtin_loongson_psubsh (s, t); -} - -__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -psubsb (int8x8_t s, int8x8_t t) -{ - return __builtin_loongson_psubsb (s, t); -} - -/* Vector subtraction, treating overflow by unsigned saturation. */ -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -psubush (uint16x4_t s, uint16x4_t t) -{ - return __builtin_loongson_psubush (s, t); -} - -__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -psubusb (uint8x8_t s, uint8x8_t t) -{ - return __builtin_loongson_psubusb (s, t); -} - -/* Unpack high data. */ -__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -punpckhwd_u (uint32x2_t s, uint32x2_t t) -{ - return __builtin_loongson_punpckhwd_u (s, t); -} - -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -punpckhhw_u (uint16x4_t s, uint16x4_t t) -{ - return __builtin_loongson_punpckhhw_u (s, t); -} - -__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -punpckhbh_u (uint8x8_t s, uint8x8_t t) -{ - return __builtin_loongson_punpckhbh_u (s, t); -} - -__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -punpckhwd_s (int32x2_t s, int32x2_t t) -{ - return __builtin_loongson_punpckhwd_s (s, t); -} - -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -punpckhhw_s (int16x4_t s, int16x4_t t) -{ - return __builtin_loongson_punpckhhw_s (s, t); -} - -__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -punpckhbh_s (int8x8_t s, int8x8_t t) -{ - return __builtin_loongson_punpckhbh_s (s, t); -} - -/* Unpack low data. */ -__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -punpcklwd_u (uint32x2_t s, uint32x2_t t) -{ - return __builtin_loongson_punpcklwd_u (s, t); -} - -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -punpcklhw_u (uint16x4_t s, uint16x4_t t) -{ - return __builtin_loongson_punpcklhw_u (s, t); -} - -__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -punpcklbh_u (uint8x8_t s, uint8x8_t t) -{ - return __builtin_loongson_punpcklbh_u (s, t); -} - -__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -punpcklwd_s (int32x2_t s, int32x2_t t) -{ - return __builtin_loongson_punpcklwd_s (s, t); -} - -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -punpcklhw_s (int16x4_t s, int16x4_t t) -{ - return __builtin_loongson_punpcklhw_s (s, t); -} - -__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -punpcklbh_s (int8x8_t s, int8x8_t t) -{ - return __builtin_loongson_punpcklbh_s (s, t); -} - -#ifdef __cplusplus -} -#endif +#if !defined(_GCC_LOONGSON_MMIINTRIN_H) +#warning \ + loongson.h will be deprecated without further notice at a future date. \ + Please use loongson-mmiintrin.h instead. +#include "loongson-mmiintrin.h" #endif diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index ea2fae1d6db..a804f7030db 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -12797,8 +12797,9 @@ mips_hard_regno_mode_ok_uncached (unsigned int regno, machine_mode mode) if (mode == CCFmode) return !(TARGET_FLOATXX && (regno & 1) != 0); - /* Allow 64-bit vector modes for Loongson-2E/2F. */ - if (TARGET_LOONGSON_VECTORS + /* Allow 64-bit vector modes for Loongson MultiMedia extensions + Instructions (MMI). */ + if (TARGET_LOONGSON_MMI && (mode == V2SImode || mode == V4HImode || mode == V8QImode @@ -13368,7 +13369,7 @@ mips_vector_mode_supported_p (machine_mode mode) case E_V2SImode: case E_V4HImode: case E_V8QImode: - return TARGET_LOONGSON_VECTORS; + return TARGET_LOONGSON_MMI; default: return MSA_SUPPORTED_MODE_P (mode); @@ -15203,7 +15204,7 @@ AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2) AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP) AVAIL_NON_MIPS16 (dsp_64, TARGET_64BIT && TARGET_DSP) AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2) -AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS) +AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_MMI) AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN) AVAIL_NON_MIPS16 (msa, TARGET_MSA) @@ -20164,6 +20165,19 @@ mips_option_override (void) TARGET_DSPR2 = false; } + /* Make sure that when TARGET_LOONGSON_MMI is true, TARGET_HARD_FLOAT_ABI + is true. In o32 pairs of floating-point registers provide 64-bit + values. */ + if (TARGET_LOONGSON_MMI && !TARGET_HARD_FLOAT_ABI) + error ("%<-mloongson-mmi%> must be used with %<-mhard-float%>"); + + /* Default to enable Loongson MMI on Longson 2e, 2f or 3a target. */ + if ((target_flags_explicit & MASK_LOONGSON_MMI) == 0 + && ((strcmp (mips_arch_info->name, "loongson2e") == 0) + || (strcmp (mips_arch_info->name, "loongson2f") == 0) + || (strcmp (mips_arch_info->name, "loongson3a") == 0))) + target_flags |= MASK_LOONGSON_MMI; + /* .eh_frame addresses should be the same width as a C pointer. Most MIPS ABIs support only one pointer size, so the assembler will usually know exactly how big an .eh_frame address is. @@ -21149,12 +21163,12 @@ void mips_function_profiler (FILE *file) /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default behavior of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even - when TARGET_LOONGSON_VECTORS is true. */ + when TARGET_LOONGSON_MMI is true. */ static unsigned HOST_WIDE_INT mips_shift_truncation_mask (machine_mode mode) { - if (TARGET_LOONGSON_VECTORS && VECTOR_MODE_P (mode)) + if (TARGET_LOONGSON_MMI && VECTOR_MODE_P (mode)) return 0; return GET_MODE_BITSIZE (mode) - 1; @@ -21255,7 +21269,7 @@ mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d *d) unsigned i, odd, nelt = d->nelt; rtx t0, t1, t2, t3; - if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS)) + if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI)) return false; /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */ if (nelt < 4) @@ -21312,7 +21326,7 @@ mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d *d) unsigned i, mask; rtx rmask; - if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS)) + if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI)) return false; if (d->vmode != V4HImode) return false; @@ -21364,7 +21378,7 @@ mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d *d) unsigned i, elt; rtx t0, t1; - if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS)) + if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI)) return false; /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */ if (d->vmode != V8QImode) @@ -21958,7 +21972,7 @@ mips_expand_vector_init (rtx target, rtx vals) } /* Loongson is the only cpu with vectors with more elements. */ - gcc_assert (TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS); + gcc_assert (TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI); /* If all values are identical, broadcast the value. */ if (all_same) diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 6804b792ff1..3563c1d78fe 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -319,13 +319,6 @@ struct mips_cpu_info { #define TUNE_I6400 (mips_tune == PROCESSOR_I6400) #define TUNE_P6600 (mips_tune == PROCESSOR_P6600) -/* Whether vector modes and intrinsics for ST Microelectronics - Loongson-2E/2F processors should be enabled. In o32 pairs of - floating-point registers provide 64-bit values. */ -#define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \ - && (TARGET_LOONGSON_2EF \ - || TARGET_LOONGSON_3A)) - /* True if the pre-reload scheduler should try to create chains of multiply-add or multiply-subtract instructions. For example, suppose we have: @@ -596,9 +589,12 @@ struct mips_cpu_info { if (TARGET_ABICALLS) \ builtin_define ("__mips_abicalls"); \ \ - /* Whether Loongson vector modes are enabled. */ \ - if (TARGET_LOONGSON_VECTORS) \ - builtin_define ("__mips_loongson_vector_rev"); \ + /* Whether Loongson vector modes are enabled. */ \ + if (TARGET_LOONGSON_MMI) \ + { \ + builtin_define ("__mips_loongson_vector_rev"); \ + builtin_define ("__mips_loongson_mmi"); \ + } \ \ /* Historical Octeon macro. */ \ if (TARGET_OCTEON) \ @@ -1358,6 +1354,7 @@ struct mips_cpu_info { %{mcrc} %{mno-crc} \ %{mginv} %{mno-ginv} \ %{mmsa} %{mno-msa} \ +%{mloongson-mmi} %{mno-loongson-mmi} \ %{msmartmips} %{mno-smartmips} \ %{mmt} %{mno-mt} \ %{mfix-rm7000} %{mno-fix-rm7000} \ @@ -2635,9 +2632,9 @@ typedef struct mips_args { #define SLOW_BYTE_ACCESS (!TARGET_MIPS16) /* Standard MIPS integer shifts truncate the shift amount to the - width of the shifted operand. However, Loongson vector shifts + width of the shifted operand. However, Loongson MMI shifts do not truncate the shift amount at all. */ -#define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_VECTORS) +#define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_MMI) /* Specify the machine mode that pointers have. diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index ea5a23be1f7..a88c1c53134 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -834,9 +834,9 @@ (define_mode_iterator MOVE64 [DI DF (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT") - (V2SI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS") - (V4HI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS") - (V8QI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")]) + (V2SI "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI") + (V4HI "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI") + (V8QI "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI")]) ;; 128-bit modes for which we provide move patterns on 64-bit targets. (define_mode_iterator MOVE128 [TI TF]) @@ -863,9 +863,9 @@ [(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT") (DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT") (V2SF "!TARGET_64BIT && TARGET_PAIRED_SINGLE_FLOAT") - (V2SI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS") - (V4HI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS") - (V8QI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS") + (V2SI "!TARGET_64BIT && TARGET_LOONGSON_MMI") + (V4HI "!TARGET_64BIT && TARGET_LOONGSON_MMI") + (V8QI "!TARGET_64BIT && TARGET_LOONGSON_MMI") (TF "TARGET_64BIT && TARGET_FLOAT64")]) ;; In GPR templates, a string like "subu" will expand to "subu" in the @@ -7690,8 +7690,8 @@ ; microMIPS patterns. (include "micromips.md") -; ST-Microelectronics Loongson-2E/2F-specific patterns. -(include "loongson.md") +; Loongson MultiMedia extensions Instructions (MMI) patterns. +(include "loongson-mmi.md") ; The MIPS MSA Instructions. (include "mips-msa.md") diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index 5a9f255fe20..6767c47fa65 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -459,3 +459,7 @@ Enum(mips_cb_setting) String(optimal) Value(MIPS_CB_OPTIMAL) EnumValue Enum(mips_cb_setting) String(always) Value(MIPS_CB_ALWAYS) + +mloongson-mmi +Target Report Mask(LOONGSON_MMI) +Use Loongson MultiMedia extensions Instructions (MMI) instructions. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 802cc642453..79544e2c2b6 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -919,6 +919,7 @@ Objective-C and Objective-C++ Dialects}. -mginv -mno-ginv @gol -mmicromips -mno-micromips @gol -mmsa -mno-msa @gol +-mloongson-mmi -mno-loongson-mmi @gol -mfpu=@var{fpu-type} @gol -msmartmips -mno-smartmips @gol -mpaired-single -mno-paired-single -mdmx -mno-mdmx @gol @@ -21256,6 +21257,12 @@ Use (do not use) the MIPS Cyclic Redundancy Check (CRC) instructions. @opindex mno-ginv Use (do not use) the MIPS Global INValidate (GINV) instructions. +@item -mloongson-mmi +@itemx -mno-loongson-mmi +@opindex mloongson-mmi +@opindex mno-loongson-mmi +Use (do not use) the MIPS Loongson MultiMedia extensions Instructions (MMI). + @item -mlong64 @opindex mlong64 Force @code{long} types to be 64 bits wide. See @option{-mlong32} for diff --git a/gcc/testsuite/gcc.target/mips/loongson-shift-count-truncated-1.c b/gcc/testsuite/gcc.target/mips/loongson-shift-count-truncated-1.c index baed48cf5d5..6e22c0e110b 100644 --- a/gcc/testsuite/gcc.target/mips/loongson-shift-count-truncated-1.c +++ b/gcc/testsuite/gcc.target/mips/loongson-shift-count-truncated-1.c @@ -4,11 +4,11 @@ /* loongson.h does not handle or check for MIPS16ness. There doesn't seem any good reason for it to, given that the Loongson processors do not support MIPS16. */ -/* { dg-options "isa=loongson -mhard-float -mno-mips16 (REQUIRES_STDLIB)" } */ +/* { dg-options "-mloongson-mmi -mhard-float -mno-mips16 (REQUIRES_STDLIB)" } */ /* See PR 52155. */ -/* { dg-options "isa=loongson -mhard-float -mno-mips16 -mlong64" { mips*-*-elf* && ilp32 } } */ +/* { dg-options "-mloongson-mmi -mhard-float -mno-mips16 -mlong64" { mips*-*-elf* && ilp32 } } */ -#include "loongson.h" +#include "loongson-mmiintrin.h" #include typedef union { int32x2_t v; int32_t a[2]; } int32x2_encap_t; diff --git a/gcc/testsuite/gcc.target/mips/loongson-simd.c b/gcc/testsuite/gcc.target/mips/loongson-simd.c index f263b4393e9..34fdcecc6dc 100644 --- a/gcc/testsuite/gcc.target/mips/loongson-simd.c +++ b/gcc/testsuite/gcc.target/mips/loongson-simd.c @@ -26,9 +26,9 @@ along with GCC; see the file COPYING3. If not see because inclusion of some system headers e.g. stdint.h will fail due to not finding stubs-o32_hard.h. */ /* { dg-require-effective-target mips_nanlegacy } */ -/* { dg-options "isa=loongson -mhard-float -mno-micromips -mno-mips16 -flax-vector-conversions (REQUIRES_STDLIB)" } */ +/* { dg-options "-mloongson-mmi -mhard-float -mno-micromips -mno-mips16 -flax-vector-conversions (REQUIRES_STDLIB)" } */ -#include "loongson.h" +#include "loongson-mmiintrin.h" #include #include #include diff --git a/gcc/testsuite/gcc.target/mips/mips.exp b/gcc/testsuite/gcc.target/mips/mips.exp index 9db4fbe29ce..4045c593a6c 100644 --- a/gcc/testsuite/gcc.target/mips/mips.exp +++ b/gcc/testsuite/gcc.target/mips/mips.exp @@ -296,6 +296,7 @@ foreach option { mcount-ra-address odd-spreg msa + loongson-mmi } { lappend mips_option_groups $option "-m(no-|)$option" } @@ -883,6 +884,12 @@ proc mips-dg-init {} { "-mno-msa" #endif + #ifdef __mips_loongson_mmi + "-mloongson-mmi" + #else + "-mno-loongson-mmi" + #endif + 0 }; } 0] diff --git a/gcc/testsuite/gcc.target/mips/umips-store16-1.c b/gcc/testsuite/gcc.target/mips/umips-store16-1.c index 6377e8569d6..f82c837d475 100644 --- a/gcc/testsuite/gcc.target/mips/umips-store16-1.c +++ b/gcc/testsuite/gcc.target/mips/umips-store16-1.c @@ -1,4 +1,4 @@ -/* { dg-options "(-mmicromips)" } */ +/* { dg-options "(-mmicromips) forbid_cpu=loongson3a" } */ /* { dg-do assemble } */ register unsigned int global asm ("$16"); diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index fd74c04d092..47c623ebab8 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -1896,20 +1896,20 @@ proc check_mpaired_single_hw_available { } { # Return 1 if the target supports executing Loongson vector instructions, # 0 otherwise. Cache the result. -proc check_mips_loongson_hw_available { } { - return [check_cached_effective_target mips_loongson_hw_available { +proc check_mips_loongson_mmi_hw_available { } { + return [check_cached_effective_target mips_loongson_mmi_hw_available { # If this is not the right target then we can skip the test. if { !([istarget mips*-*-*]) } { expr 0 } else { - check_runtime_nocache mips_loongson_hw_available { - #include + check_runtime_nocache mips_loongson_mmi_hw_available { + #include int main() { asm volatile ("paddw $f2,$f4,$f6"); return 0; } - } "" + } "-mloongson-mmi" } }] } @@ -1963,9 +1963,9 @@ proc check_effective_target_mpaired_single_runtime { } { # Return 1 if the target supports running Loongson executables, 0 otherwise. -proc check_effective_target_mips_loongson_runtime { } { - if { [check_effective_target_mips_loongson] - && [check_mips_loongson_hw_available] } { +proc check_effective_target_mips_loongson_mmi_runtime { } { + if { [check_effective_target_mips_loongson_mmi] + && [check_mips_loongson_mmi_hw_available] } { return 1 } return 0 @@ -3085,7 +3085,7 @@ proc check_effective_target_vect_int { } { || [istarget aarch64*-*-*] || [is-effective-target arm_neon] || ([istarget mips*-*-*] - && ([et-is-effective-target mips_loongson] + && ([et-is-effective-target mips_loongson_mmi] || [et-is-effective-target mips_msa])) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) @@ -4708,11 +4708,24 @@ proc add_options_for_mips_msa { flags } { return "$flags -mmsa" } +# Add the options needed for MIPS Loongsn MMI Architecture. + +proc add_options_for_mips_loongson_mmi { flags } { + if { ! [check_effective_target_mips_loongson_mmi] } { + return "$flags" + } + return "$flags -mloongson-mmi" +} + + # Return 1 if this a Loongson-2E or -2F target using an ABI that supports # the Loongson vector modes. -proc check_effective_target_mips_loongson { } { +proc check_effective_target_mips_loongson_mmi { } { return [check_no_compiler_messages loongson assembly { + #if !defined(__mips_loongson_mmi) + #error !__mips_loongson_mmi + #endif #if !defined(__mips_loongson_vector_rev) #error !__mips_loongson_vector_rev #endif @@ -5311,7 +5324,7 @@ proc check_effective_target_vect_shift { } { || [is-effective-target arm_neon] || ([istarget mips*-*-*] && ([et-is-effective-target mips_msa] - || [et-is-effective-target mips_loongson])) + || [et-is-effective-target mips_loongson_mmi])) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) }}] } @@ -5324,7 +5337,7 @@ proc check_effective_target_whole_vector_shift { } { || ([is-effective-target arm_neon] && [check_effective_target_arm_little_endian]) || ([istarget mips*-*-*] - && [et-is-effective-target mips_loongson]) + && [et-is-effective-target mips_loongson_mmi]) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) } { set answer 1 @@ -5464,7 +5477,7 @@ proc check_effective_target_vect_no_int_min_max { } { || [istarget spu-*-*] || [istarget alpha*-*-*] || ([istarget mips*-*-*] - && [et-is-effective-target mips_loongson]) }}] + && [et-is-effective-target mips_loongson_mmi]) }}] } # Return 1 if the target plus current options does not support a vector @@ -5933,7 +5946,7 @@ proc check_effective_target_vect_no_align { } { || [check_effective_target_arm_vect_no_misalign] || ([istarget powerpc*-*-*] && [check_p8vector_hw_available]) || ([istarget mips*-*-*] - && [et-is-effective-target mips_loongson]) }}] + && [et-is-effective-target mips_loongson_mmi]) }}] } # Return 1 if the target supports a vector misalign access, 0 otherwise. @@ -6167,7 +6180,7 @@ proc check_effective_target_vect_short_mult { } { || [check_effective_target_arm32] || ([istarget mips*-*-*] && ([et-is-effective-target mips_msa] - || [et-is-effective-target mips_loongson])) + || [et-is-effective-target mips_loongson_mmi])) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) }}] } @@ -8155,8 +8168,8 @@ proc check_vect_support_and_set_flags { } { if { [check_effective_target_mpaired_single] } { lappend EFFECTIVE_TARGETS mpaired_single } - if { [check_effective_target_mips_loongson] } { - lappend EFFECTIVE_TARGETS mips_loongson + if { [check_effective_target_mips_loongson_mmi] } { + lappend EFFECTIVE_TARGETS mips_loongson_mmi } if { [check_effective_target_mips_msa] } { lappend EFFECTIVE_TARGETS mips_msa -- 2.11.0 From patchwork Tue Oct 16 02:50:08 2018 Content-Type: text/plain; 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16 Oct 2018 02:50:24 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-ot1-f46.google.com Received: from mail-ot1-f46.google.com (HELO mail-ot1-f46.google.com) (209.85.210.46) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 16 Oct 2018 02:50:22 +0000 Received: by mail-ot1-f46.google.com with SMTP id o21so20986636otb.13 for ; Mon, 15 Oct 2018 19:50:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to:cc; bh=izxxezyf0qjsKvwy2WMOt0nJsu53XHRBcwYqtDT0Z4A=; b=FcZ9PbIItAfG34D3FGJev5TExiUt69dMRh7aX46iUy7XP2VSSsRjz4vj9p8KaXd+ZB 9vFGjtE5U+k0rOCLX33V/KaG/2U4rDiHf3HyelziVPXXn1ftkbbJTWcyEciL7jFPHUUl wkhPxaUSNtpu3Tn6UPOA5nmWCzRljmiiLNBTU57QjbqeyMXqkL07g0Wef7Zwl/bk0TBq JwMhwOQgSyFuEkf5LL6PZbwiUkVHClK47sKcCopfVHBbIMPSfPeOXVGuE0yOOcQPrIlR aLBbmNDvbwaHVsIOkU1wr9mrKuIoPM9CchukLy6m5w/Q87mBPAYXs1N7hb/WWPrQnQ+P ajZw== MIME-Version: 1.0 From: Paul Hua Date: Tue, 16 Oct 2018 10:50:08 +0800 Message-ID: Subject: [PATCH v3 2/6] [MIPS] Split Loongson EXTensions (EXT) instructions from loongson3a To: gcc-patches Cc: Matthew Fortune , "Jeff Law (law@redhat.com)" X-IsSubscribed: yes From 2e053c832497892c6b8b1b685aaf871d8fc4da76 Mon Sep 17 00:00:00 2001 From: Chenghua Xu Date: Fri, 31 Aug 2018 11:52:33 +0800 Subject: [PATCH 2/6] Add support for Loongson EXT istructions. gcc/ * config/mips/mips.c (mips_option_override): Default enable Loongson EXT on Loongson 3a target. * config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Add __mips_loongson_ext. (ASM_SPEC): Add mloongson-ext and mno-loongson-ext. * config/mips/mips.md (mul3, mul3_mul3_nohilo, div3, mod3, prefetch): Use TARGET_LOONGSON_EXT instead of TARGET_LOONGSON_3A. * config/mips/mips.opt (-mloongson-ext): Add option. * gcc/doc/invoke.texi (-mloongson-ext): Document. gcc/testsuite/ * gcc.target/mips/mips.exp (mips_option_groups): Add -mloongson-ext option. --- gcc/config/mips/mips.c | 5 +++++ gcc/config/mips/mips.h | 7 +++++++ gcc/config/mips/mips.md | 16 ++++++++-------- gcc/config/mips/mips.opt | 4 ++++ gcc/doc/invoke.texi | 7 +++++++ gcc/testsuite/gcc.target/mips/mips.exp | 1 + 6 files changed, 32 insertions(+), 8 deletions(-) diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index a804f7030db..019a6dca752 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -20178,6 +20178,11 @@ mips_option_override (void) || (strcmp (mips_arch_info->name, "loongson3a") == 0))) target_flags |= MASK_LOONGSON_MMI; + /* Default to enable Loongson EXT on Longson 3a target. */ + if ((target_flags_explicit & MASK_LOONGSON_EXT) == 0 + && (strcmp (mips_arch_info->name, "loongson3a") == 0)) + target_flags |= MASK_LOONGSON_EXT; + /* .eh_frame addresses should be the same width as a C pointer. Most MIPS ABIs support only one pointer size, so the assembler will usually know exactly how big an .eh_frame address is. diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 3563c1d78fe..e0e78ba610e 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -596,6 +596,12 @@ struct mips_cpu_info { builtin_define ("__mips_loongson_mmi"); \ } \ \ + /* Whether Loongson EXT modes are enabled. */ \ + if (TARGET_LOONGSON_EXT) \ + { \ + builtin_define ("__mips_loongson_ext"); \ + } \ + \ /* Historical Octeon macro. */ \ if (TARGET_OCTEON) \ builtin_define ("__OCTEON__"); \ @@ -1355,6 +1361,7 @@ struct mips_cpu_info { %{mginv} %{mno-ginv} \ %{mmsa} %{mno-msa} \ %{mloongson-mmi} %{mno-loongson-mmi} \ +%{mloongson-ext} %{mno-loongson-ext} \ %{msmartmips} %{mno-smartmips} \ %{mmt} %{mno-mt} \ %{mfix-rm7000} %{mno-fix-rm7000} \ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index a88c1c53134..4b7a627b7a6 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -1599,7 +1599,7 @@ { rtx lo; - if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6MUL) + if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6MUL) emit_insn (gen_mul3_mul3_nohilo (operands[0], operands[1], operands[2])); else if (ISA_HAS_MUL3) @@ -1622,11 +1622,11 @@ [(set (match_operand:GPR 0 "register_operand" "=d") (mult:GPR (match_operand:GPR 1 "register_operand" "d") (match_operand:GPR 2 "register_operand" "d")))] - "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6MUL" + "TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6MUL" { if (TARGET_LOONGSON_2EF) return "multu.g\t%0,%1,%2"; - else if (TARGET_LOONGSON_3A) + else if (TARGET_LOONGSON_EXT) return "gsmultu\t%0,%1,%2"; else return "mul\t%0,%1,%2"; @@ -3016,11 +3016,11 @@ [(set (match_operand:GPR 0 "register_operand" "=&d") (any_div:GPR (match_operand:GPR 1 "register_operand" "d") (match_operand:GPR 2 "register_operand" "d")))] - "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6DIV" + "TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6DIV" { if (TARGET_LOONGSON_2EF) return mips_output_division ("div.g\t%0,%1,%2", operands); - else if (TARGET_LOONGSON_3A) + else if (TARGET_LOONGSON_EXT) return mips_output_division ("gsdiv\t%0,%1,%2", operands); else return mips_output_division ("div\t%0,%1,%2", operands); @@ -3032,11 +3032,11 @@ [(set (match_operand:GPR 0 "register_operand" "=&d") (any_mod:GPR (match_operand:GPR 1 "register_operand" "d") (match_operand:GPR 2 "register_operand" "d")))] - "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6DIV" + "TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6DIV" { if (TARGET_LOONGSON_2EF) return mips_output_division ("mod.g\t%0,%1,%2", operands); - else if (TARGET_LOONGSON_3A) + else if (TARGET_LOONGSON_EXT) return mips_output_division ("gsmod\t%0,%1,%2", operands); else return mips_output_division ("mod\t%0,%1,%2", operands); @@ -7136,7 +7136,7 @@ (match_operand 2 "const_int_operand" "n"))] "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS" { - if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A) + if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT) { /* Loongson 2[ef] and Loongson 3a use load to $0 for prefetching. */ if (TARGET_64BIT) diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index 6767c47fa65..a8fe8db3c66 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -463,3 +463,7 @@ Enum(mips_cb_setting) String(always) Value(MIPS_CB_ALWAYS) mloongson-mmi Target Report Mask(LOONGSON_MMI) Use Loongson MultiMedia extensions Instructions (MMI) instructions. + +mloongson-ext +Target Report Mask(LOONGSON_EXT) +Use Loongson EXTension (EXT) instructions. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 79544e2c2b6..5f2736b9e09 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -920,6 +920,7 @@ Objective-C and Objective-C++ Dialects}. -mmicromips -mno-micromips @gol -mmsa -mno-msa @gol -mloongson-mmi -mno-loongson-mmi @gol +-mloongson-ext -mno-loongson-ext @gol -mfpu=@var{fpu-type} @gol -msmartmips -mno-smartmips @gol -mpaired-single -mno-paired-single -mdmx -mno-mdmx @gol @@ -21263,6 +21264,12 @@ Use (do not use) the MIPS Global INValidate (GINV) instructions. @opindex mno-loongson-mmi Use (do not use) the MIPS Loongson MultiMedia extensions Instructions (MMI). +@item -mloongson-ext +@itemx -mno-loongson-ext +@opindex mloongson-ext +@opindex mno-loongson-ext +Use (do not use) the MIPS Loongson EXTensions (EXT) instructions. + @item -mlong64 @opindex mlong64 Force @code{long} types to be 64 bits wide. See @option{-mlong32} for diff --git a/gcc/testsuite/gcc.target/mips/mips.exp b/gcc/testsuite/gcc.target/mips/mips.exp index 4045c593a6c..70f7a996f8d 100644 --- a/gcc/testsuite/gcc.target/mips/mips.exp +++ b/gcc/testsuite/gcc.target/mips/mips.exp @@ -297,6 +297,7 @@ foreach option { odd-spreg msa loongson-mmi + loongson-ext } { lappend mips_option_groups $option "-m(no-|)$option" } -- 2.11.0 From patchwork Tue Oct 16 02:50:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Hua X-Patchwork-Id: 984496 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-487609-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="DfdvCxx4"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ukqQGyTA"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42Z0Dp2LkJz9s9J for ; Tue, 16 Oct 2018 13:51:06 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:cc:content-type; q=dns; s=default; b=yeF06b06Sl/1SwZiPWEEZb1u8ex2chSK08aqMlJ0f3+ oR07vRy37ajOfXJTT4QM7OfMQYnPzKCEMbFIwUMmiEFccG6El9vBnqs8/sUYUQ0J dB1UeTA8X1GMYofav0V5NyDLPgVOp7yAAY3Xyrq+xCVRzRKXitb4D+Dvn6lyrzlM = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:cc:content-type; s=default; bh=VLSlD69IvlNE3zwFir1Je78AnZ0=; b=DfdvCxx4gwtiLA7QN wLN4SFRm6yXuYenQzWhBxi/xehmqHoitK8x0dNDy+LtowkF8nJ+4Ia+2elOJWOkj x37tIjycWFpMDR9e8Q3MCvpooyagt6Vzfkx0vnXMjhlLJslXMhfZNFs8QgDa4mFj hZ+WZL74pNhfnd1gUmFFwfB11k= Received: (qmail 91755 invoked by alias); 16 Oct 2018 02:50:35 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 91628 invoked by uid 89); 16 Oct 2018 02:50:34 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-25.6 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-oi1-f179.google.com Received: from mail-oi1-f179.google.com (HELO mail-oi1-f179.google.com) (209.85.167.179) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 16 Oct 2018 02:50:31 +0000 Received: by mail-oi1-f179.google.com with SMTP id s69-v6so16780016oie.10 for ; Mon, 15 Oct 2018 19:50:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to:cc; bh=dcMh0Za79LzXl0RS1VJsQYnHVr6fEZcf3Z18ziPe9rY=; b=ukqQGyTAzQhpuEnz0gnw3MxRfulWB7b3akRGR2JZz7r8u5PyNoGjgoYF6v5KOsOHdP F7OIQhlMq7i+Ctv99JOOIFr7jTvQqv5LOn6kZzERT1efX9o66gqaSkT8IGh7oDSJRdaO 4VTGQ3G1WVrhfS0yJMIHIC5LDs8oTKnpfCWlGkYDerxxIhHEJ65P7mZw+5YbpYV9eX9x yFy8yFjq5eHO89KdAZoXMRozdb9bxLAAqOOB1+ur3QT6Qvamxnuh+Ai2E2VdZwuTEWTk ArGUs4fMv8lLrn0SBqCd5HFWq6FTUR8ngr2OGH4XX5X7p3K3/Ouz82oBn/xWSQqgTuJx TlnQ== MIME-Version: 1.0 From: Paul Hua Date: Tue, 16 Oct 2018 10:50:18 +0800 Message-ID: Subject: [PATCH v3 3/6] [MIPS] Add Loongson EXTensions R2 (EXT2) instructions support To: gcc-patches Cc: Matthew Fortune , "Jeff Law (law@redhat.com)" X-IsSubscribed: yes From 14eabf990f187631cacd47e02342941ddb1b04a0 Mon Sep 17 00:00:00 2001 From: Chenghua Xu Date: Fri, 31 Aug 2018 11:55:48 +0800 Subject: [PATCH 3/6] Add support for Loongson EXT2 istructions. gcc/ * config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Define __mips_loongson_ext2, __mips_loongson_ext_rev=2. (ISA_HAS_CTZ_CTO): New, ture if TARGET_LOONGSON_EXT2. (ASM_SPEC): Add mloongson-ext2 and mno-loongson-ext2. * config/mips/mips.md: Add ctz to "define_attr "type"". (define_insn "ctz2"): New insn pattern. (define_insn "prefetch"): Include TARGET_LOONGSON_EXT2. * config/mips/mips.opt (-mloongson-ext2): Add option. * gcc/doc/invoke.texi (-mloongson-ext2): Document. gcc/testsuite/ * gcc.target/mips/loongson-ctz.c: New test. * gcc.target/mips/loongson-dctz.c: Likewise. * gcc.target/mips/mips.exp (mips_option_groups): Add -mloongson-ext2 option. --- gcc/config/mips/mips.h | 12 +++++++++++ gcc/config/mips/mips.md | 31 ++++++++++++++++++++++----- gcc/config/mips/mips.opt | 4 ++++ gcc/doc/invoke.texi | 7 ++++++ gcc/testsuite/gcc.target/mips/loongson-ctz.c | 11 ++++++++++ gcc/testsuite/gcc.target/mips/loongson-dctz.c | 11 ++++++++++ gcc/testsuite/gcc.target/mips/mips.exp | 1 + 7 files changed, 72 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/mips/loongson-ctz.c create mode 100644 gcc/testsuite/gcc.target/mips/loongson-dctz.c diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index e0e78ba610e..b75646d66ce 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -600,8 +600,16 @@ struct mips_cpu_info { if (TARGET_LOONGSON_EXT) \ { \ builtin_define ("__mips_loongson_ext"); \ + if (TARGET_LOONGSON_EXT2) \ + { \ + builtin_define ("__mips_loongson_ext2"); \ + builtin_define ("__mips_loongson_ext_rev=2"); \ + } \ + else \ + builtin_define ("__mips_loongson_ext_rev=1"); \ } \ \ + \ /* Historical Octeon macro. */ \ if (TARGET_OCTEON) \ builtin_define ("__OCTEON__"); \ @@ -1117,6 +1125,9 @@ struct mips_cpu_info { /* ISA has count leading zeroes/ones instruction (not implemented). */ #define ISA_HAS_CLZ_CLO (mips_isa_rev >= 1 && !TARGET_MIPS16) +/* ISA has count tailing zeroes/ones instruction (not implemented). */ +#define ISA_HAS_CTZ_CTO (TARGET_LOONGSON_EXT2) + /* ISA has three operand multiply instructions that put the high part in an accumulator: mulhi or mulhiu. */ #define ISA_HAS_MULHI ((TARGET_MIPS5400 \ @@ -1362,6 +1373,7 @@ struct mips_cpu_info { %{mmsa} %{mno-msa} \ %{mloongson-mmi} %{mno-loongson-mmi} \ %{mloongson-ext} %{mno-loongson-ext} \ +%{mloongson-ext2} %{mno-loongson-ext2} \ %{msmartmips} %{mno-smartmips} \ %{mmt} %{mno-mt} \ %{mfix-rm7000} %{mno-fix-rm7000} \ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 4b7a627b7a6..c8128d4d530 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -335,6 +335,7 @@ ;; slt set less than instructions ;; signext sign extend instructions ;; clz the clz and clo instructions +;; ctz the ctz and cto instructions ;; pop the pop instruction ;; trap trap if instructions ;; imul integer multiply 2 operands @@ -375,7 +376,7 @@ (define_attr "type" "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore, prefetch,prefetchx,condmove,mtc,mfc,mthi,mtlo,mfhi,mflo,const,arith,logical, - shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move, + shift,slt,signext,clz,ctz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move, fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt, frsqrt,frsqrt1,frsqrt2,dspmac,dspmacsat,accext,accmod,dspalu,dspalusat, multi,atomic,syncloop,nop,ghost,multimem, @@ -3149,6 +3150,23 @@ ;; ;; ................... ;; +;; Count tailing zeroes. +;; +;; ................... +;; + +(define_insn "ctz2" + [(set (match_operand:GPR 0 "register_operand" "=d") + (ctz:GPR (match_operand:GPR 1 "register_operand" "d")))] + "ISA_HAS_CTZ_CTO" + "ctz\t%0,%1" + [(set_attr "type" "ctz") + (set_attr "mode" "")]) + + +;; +;; ................... +;; ;; Count number of set bits. ;; ;; ................... @@ -7136,13 +7154,16 @@ (match_operand 2 "const_int_operand" "n"))] "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS" { - if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT) + if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || TARGET_LOONGSON_EXT2) { - /* Loongson 2[ef] and Loongson 3a use load to $0 for prefetching. */ + /* Loongson ext2 implementation pref insnstructions. */ + if (TARGET_LOONGSON_EXT2) + return "pref\t%1, %a0"; + /* Loongson 2[ef] and Loongson ext use load to $0 for prefetching. */ if (TARGET_64BIT) - return "ld\t$0,%a0"; + return "ld\t$0,%a0"; else - return "lw\t$0,%a0"; + return "lw\t$0,%a0"; } operands[1] = mips_prefetch_cookie (operands[1], operands[2]); return "pref\t%1,%a0"; diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index a8fe8db3c66..c0c8005b025 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -467,3 +467,7 @@ Use Loongson MultiMedia extensions Instructions (MMI) instructions. mloongson-ext Target Report Mask(LOONGSON_EXT) Use Loongson EXTension (EXT) instructions. + +mloongson-ext2 +Target Report Mask(LOONGSON_EXT2) +Use Loongson EXTension R2 (EXT2) instructions. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 5f2736b9e09..2f0c33969c1 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -921,6 +921,7 @@ Objective-C and Objective-C++ Dialects}. -mmsa -mno-msa @gol -mloongson-mmi -mno-loongson-mmi @gol -mloongson-ext -mno-loongson-ext @gol +-mloongson-ext2 -mno-loongson-ext2 @gol -mfpu=@var{fpu-type} @gol -msmartmips -mno-smartmips @gol -mpaired-single -mno-paired-single -mdmx -mno-mdmx @gol @@ -21270,6 +21271,12 @@ Use (do not use) the MIPS Loongson MultiMedia extensions Instructions (MMI). @opindex mno-loongson-ext Use (do not use) the MIPS Loongson EXTensions (EXT) instructions. +@item -mloongson-ext2 +@itemx -mno-loongson-ext2 +@opindex mloongson-ext2 +@opindex mno-loongson-ext2 +Use (do not use) the MIPS Loongson EXTensions r2 (EXT2) instructions. + @item -mlong64 @opindex mlong64 Force @code{long} types to be 64 bits wide. See @option{-mlong32} for diff --git a/gcc/testsuite/gcc.target/mips/loongson-ctz.c b/gcc/testsuite/gcc.target/mips/loongson-ctz.c new file mode 100644 index 00000000000..8df66a00dc1 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/loongson-ctz.c @@ -0,0 +1,11 @@ +/* Test cases for Loongson EXT2 instrutions. */ + +/* { dg-do compile } */ +/* { dg-options "-mloongson-ext2" } */ + +unsigned int foo(unsigned int x) +{ + return __builtin_ctz (x); +} + +/* { dg-final { scan-assembler "ctz\t" } } */ diff --git a/gcc/testsuite/gcc.target/mips/loongson-dctz.c b/gcc/testsuite/gcc.target/mips/loongson-dctz.c new file mode 100644 index 00000000000..8c47433459f --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/loongson-dctz.c @@ -0,0 +1,11 @@ +/* Test cases for Loongson EXT2 instrutions. */ + +/* { dg-do compile } */ +/* { dg-options "-mloongson-ext2" } */ + +unsigned long long foo(unsigned long long x) +{ + return __builtin_ctzl (x); +} + +/* { dg-final { scan-assembler "dctz\t" } } */ diff --git a/gcc/testsuite/gcc.target/mips/mips.exp b/gcc/testsuite/gcc.target/mips/mips.exp index 70f7a996f8d..5b2bf8bd8bb 100644 --- a/gcc/testsuite/gcc.target/mips/mips.exp +++ b/gcc/testsuite/gcc.target/mips/mips.exp @@ -298,6 +298,7 @@ foreach option { msa loongson-mmi loongson-ext + loongson-ext2 } { lappend mips_option_groups $option "-m(no-|)$option" } -- 2.11.0 From patchwork Tue Oct 16 02:50:25 2018 Content-Type: text/plain; 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16 Oct 2018 02:50:43 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=xlr X-HELO: mail-ot1-f43.google.com Received: from mail-ot1-f43.google.com (HELO mail-ot1-f43.google.com) (209.85.210.43) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 16 Oct 2018 02:50:38 +0000 Received: by mail-ot1-f43.google.com with SMTP id x4so19608574otg.3 for ; Mon, 15 Oct 2018 19:50:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to:cc; bh=KUGV9I4zMBxaF9G2ggro3iVyrL+YZTjBuNx4HXpBu/0=; b=Q8fzZrNJHhtI5hsqLP11hJ3ZGdkxHe2dgM1jg3YMs70pIFxmBEu2/SUd2xK1rCYoQ0 EotzUiN4GSFc872JqUEBOFBElEMEg4D9/ALU2m7SKAOH6TALJXoKy5nb63YgvVyJ+plB kUn0fuTCo75qxqDXhgQ7LGPrNqN3rXe52k1XshJbEQpeefm0AP4+GZi/gexGt+G1oB84 bsBt2nhQEvcB7KL+Sph5WaNHRbE4VDcjQTpNwcCMTdON9hC6jQnFjAqElEqcwuapkeA0 x9/fOreRfsDtumCG2vnQLKGhnj+l7qEkEpZEIP396vkVHBlsjFTLSHq9GFSLPAkJXTgQ KFNA== MIME-Version: 1.0 From: Paul Hua Date: Tue, 16 Oct 2018 10:50:25 +0800 Message-ID: Subject: [PATCH v3 4/6] [MIPS] Add Loongson 3A1000 processor support To: gcc-patches Cc: Matthew Fortune , "Jeff Law (law@redhat.com)" X-IsSubscribed: yes From ce950df0f918eb02d15c4287d21e3aecb43bf351 Mon Sep 17 00:00:00 2001 From: Chenghua Xu Date: Fri, 31 Aug 2018 14:08:01 +0800 Subject: [PATCH 4/6] Add support for Loongson 3A1000 proccessor. gcc/ * config/mips/loongson3a.md: Rename to ... * config/mips/gs464.md: ... here. * config/mips/mips-cpus.def: Define gs464; Add loongson3a as an alias of gs464 processor. * config/mips/mips-tables.opt: Regenerate. * config/mips/mips.c (mips_issue_rate): Use PROCESSOR_GS464 instead of ROCESSOR_LOONGSON_3A. (mips_multipass_dfa_lookahead): Use TUNE_GS464 instread of TUNE_LOONGSON_3A. (mips_option_override): Enable MMI and EXT for gs464. * config/mips/mips.h: Rename TARGET_LOONGSON_3A to TARGET_GS464; Rename TUNE_LOONGSON_3A to TUNE_GS464. (MIPS_ISA_LEVEL_SPEC): Infer mips64r2 from gs464. (ISA_HAS_ODD_SPREG, ISA_AVOID_DIV_HILO, ISA_HAS_FUSED_MADD4, ISA_HAS_UNFUSED_MADD4): Use TARGET_GS464 instead of TARGET_LOONGSON_3A. * config/mips/mips.md: Include gs464.md instead of loongson3a.md. (processor): Add gs464; * doc/invoke.texi: Add gs464 to supported architectures. --- gcc/config/mips/gs464.md | 137 ++++++++++++++++++++++++++++++++++++++++ gcc/config/mips/loongson3a.md | 137 ---------------------------------------- gcc/config/mips/mips-cpus.def | 3 +- gcc/config/mips/mips-tables.opt | 19 +++--- gcc/config/mips/mips.c | 16 +++-- gcc/config/mips/mips.h | 15 +++-- gcc/config/mips/mips.md | 4 +- gcc/doc/invoke.texi | 2 +- 8 files changed, 170 insertions(+), 163 deletions(-) create mode 100644 gcc/config/mips/gs464.md delete mode 100644 gcc/config/mips/loongson3a.md diff --git a/gcc/config/mips/gs464.md b/gcc/config/mips/gs464.md new file mode 100644 index 00000000000..82efb66786f --- /dev/null +++ b/gcc/config/mips/gs464.md @@ -0,0 +1,137 @@ +;; Pipeline model for Loongson gs464 cores. + +;; Copyright (C) 2011-2018 Free Software Foundation, Inc. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 3, or (at your +;; option) any later version. +;; +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +;; Uncomment the following line to output automata for debugging. +;; (automata_option "v") + +;; Automaton for integer instructions. +(define_automaton "gs464_a_alu") + +;; Automaton for floating-point instructions. +(define_automaton "gs464_a_falu") + +;; Automaton for memory operations. +(define_automaton "gs464_a_mem") + +;; Describe the resources. + +(define_cpu_unit "gs464_alu1" "gs464_a_alu") +(define_cpu_unit "gs464_alu2" "gs464_a_alu") +(define_cpu_unit "gs464_mem" "gs464_a_mem") +(define_cpu_unit "gs464_falu1" "gs464_a_falu") +(define_cpu_unit "gs464_falu2" "gs464_a_falu") + +;; Describe instruction reservations. + +(define_insn_reservation "gs464_arith" 1 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "arith,clz,const,logical, + move,nop,shift,signext,slt")) + "gs464_alu1 | gs464_alu2") + +(define_insn_reservation "gs464_branch" 1 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "branch,jump,call,condmove,trap")) + "gs464_alu1") + +(define_insn_reservation "gs464_mfhilo" 1 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "mfhi,mflo,mthi,mtlo")) + "gs464_alu2") + +;; Operation imul3nc is fully pipelined. +(define_insn_reservation "gs464_imul3nc" 5 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "imul3nc")) + "gs464_alu2") + +(define_insn_reservation "gs464_imul" 7 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "imul,imadd")) + "gs464_alu2 * 7") + +(define_insn_reservation "gs464_idiv_si" 12 + (and (eq_attr "cpu" "gs464") + (and (eq_attr "type" "idiv") + (eq_attr "mode" "SI"))) + "gs464_alu2 * 12") + +(define_insn_reservation "gs464_idiv_di" 25 + (and (eq_attr "cpu" "gs464") + (and (eq_attr "type" "idiv") + (eq_attr "mode" "DI"))) + "gs464_alu2 * 25") + +(define_insn_reservation "gs464_load" 3 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "load")) + "gs464_mem") + +(define_insn_reservation "gs464_fpload" 4 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "load,mfc,mtc")) + "gs464_mem") + +(define_insn_reservation "gs464_prefetch" 0 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "prefetch,prefetchx")) + "gs464_mem") + +(define_insn_reservation "gs464_store" 0 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "store,fpstore,fpidxstore")) + "gs464_mem") + +;; All the fp operations can be executed in FALU1. Only fp add, +;; sub, mul, madd can be executed in FALU2. Try FALU2 firstly. +(define_insn_reservation "gs464_fadd" 6 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "fadd,fmul,fmadd")) + "gs464_falu2 | gs464_falu1") + +(define_insn_reservation "gs464_fcmp" 2 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "fabs,fcmp,fmove,fneg")) + "gs464_falu1") + +(define_insn_reservation "gs464_fcvt" 4 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "fcvt")) + "gs464_falu1") + +(define_insn_reservation "gs464_fdiv_sf" 12 + (and (eq_attr "cpu" "gs464") + (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt") + (eq_attr "mode" "SF"))) + "gs464_falu1 * 12") + +(define_insn_reservation "gs464_fdiv_df" 19 + (and (eq_attr "cpu" "gs464") + (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt") + (eq_attr "mode" "DF"))) + "gs464_falu1 * 19") + +;; Force single-dispatch for unknown or multi. +(define_insn_reservation "gs464_unknown" 1 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "unknown,multi,atomic,syncloop")) + "gs464_alu1 + gs464_alu2 + gs464_falu1 + gs464_falu2 + gs464_mem") + +;; End of DFA-based pipeline description for gs464 diff --git a/gcc/config/mips/loongson3a.md b/gcc/config/mips/loongson3a.md deleted file mode 100644 index 2ebde6824cd..00000000000 --- a/gcc/config/mips/loongson3a.md +++ /dev/null @@ -1,137 +0,0 @@ -;; Pipeline model for Loongson-3A cores. - -;; Copyright (C) 2011-2018 Free Software Foundation, Inc. -;; -;; This file is part of GCC. -;; -;; GCC is free software; you can redistribute it and/or modify it -;; under the terms of the GNU General Public License as published -;; by the Free Software Foundation; either version 3, or (at your -;; option) any later version. -;; -;; GCC is distributed in the hope that it will be useful, but WITHOUT -;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -;; License for more details. -;; -;; You should have received a copy of the GNU General Public License -;; along with GCC; see the file COPYING3. If not see -;; . - -;; Uncomment the following line to output automata for debugging. -;; (automata_option "v") - -;; Automaton for integer instructions. -(define_automaton "ls3a_a_alu") - -;; Automaton for floating-point instructions. -(define_automaton "ls3a_a_falu") - -;; Automaton for memory operations. -(define_automaton "ls3a_a_mem") - -;; Describe the resources. - -(define_cpu_unit "ls3a_alu1" "ls3a_a_alu") -(define_cpu_unit "ls3a_alu2" "ls3a_a_alu") -(define_cpu_unit "ls3a_mem" "ls3a_a_mem") -(define_cpu_unit "ls3a_falu1" "ls3a_a_falu") -(define_cpu_unit "ls3a_falu2" "ls3a_a_falu") - -;; Describe instruction reservations. - -(define_insn_reservation "ls3a_arith" 1 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "arith,clz,const,logical, - move,nop,shift,signext,slt")) - "ls3a_alu1 | ls3a_alu2") - -(define_insn_reservation "ls3a_branch" 1 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "branch,jump,call,condmove,trap")) - "ls3a_alu1") - -(define_insn_reservation "ls3a_mfhilo" 1 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "mfhi,mflo,mthi,mtlo")) - "ls3a_alu2") - -;; Operation imul3nc is fully pipelined. -(define_insn_reservation "ls3a_imul3nc" 5 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "imul3nc")) - "ls3a_alu2") - -(define_insn_reservation "ls3a_imul" 7 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "imul,imadd")) - "ls3a_alu2 * 7") - -(define_insn_reservation "ls3a_idiv_si" 12 - (and (eq_attr "cpu" "loongson_3a") - (and (eq_attr "type" "idiv") - (eq_attr "mode" "SI"))) - "ls3a_alu2 * 12") - -(define_insn_reservation "ls3a_idiv_di" 25 - (and (eq_attr "cpu" "loongson_3a") - (and (eq_attr "type" "idiv") - (eq_attr "mode" "DI"))) - "ls3a_alu2 * 25") - -(define_insn_reservation "ls3a_load" 3 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "load")) - "ls3a_mem") - -(define_insn_reservation "ls3a_fpload" 4 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "load,mfc,mtc")) - "ls3a_mem") - -(define_insn_reservation "ls3a_prefetch" 0 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "prefetch,prefetchx")) - "ls3a_mem") - -(define_insn_reservation "ls3a_store" 0 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "store,fpstore,fpidxstore")) - "ls3a_mem") - -;; All the fp operations can be executed in FALU1. Only fp add, -;; sub, mul, madd can be executed in FALU2. Try FALU2 firstly. -(define_insn_reservation "ls3a_fadd" 6 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "fadd,fmul,fmadd")) - "ls3a_falu2 | ls3a_falu1") - -(define_insn_reservation "ls3a_fcmp" 2 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "fabs,fcmp,fmove,fneg")) - "ls3a_falu1") - -(define_insn_reservation "ls3a_fcvt" 4 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "fcvt")) - "ls3a_falu1") - -(define_insn_reservation "ls3a_fdiv_sf" 12 - (and (eq_attr "cpu" "loongson_3a") - (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt") - (eq_attr "mode" "SF"))) - "ls3a_falu1 * 12") - -(define_insn_reservation "ls3a_fdiv_df" 19 - (and (eq_attr "cpu" "loongson_3a") - (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt") - (eq_attr "mode" "DF"))) - "ls3a_falu1 * 19") - -;; Force single-dispatch for unknown or multi. -(define_insn_reservation "ls3a_unknown" 1 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "unknown,multi,atomic,syncloop")) - "ls3a_alu1 + ls3a_alu2 + ls3a_falu1 + ls3a_falu2 + ls3a_mem") - -;; End of DFA-based pipeline description for loongson_3a diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def index 6a545634417..eabe045cf39 100644 --- a/gcc/config/mips/mips-cpus.def +++ b/gcc/config/mips/mips-cpus.def @@ -162,7 +162,8 @@ MIPS_CPU ("sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("xlr", PROCESSOR_XLR, 64, PTF_AVOID_BRANCHLIKELY_SPEED) /* MIPS64 Release 2 processors. */ -MIPS_CPU ("loongson3a", PROCESSOR_LOONGSON_3A, 65, PTF_AVOID_BRANCHLIKELY_SPEED) +MIPS_CPU ("loongson3a", PROCESSOR_GS464, 65, PTF_AVOID_BRANCHLIKELY_SPEED) +MIPS_CPU ("gs464", PROCESSOR_GS464, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("octeon+", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("octeon2", PROCESSOR_OCTEON2, 65, PTF_AVOID_BRANCHLIKELY_SPEED) diff --git a/gcc/config/mips/mips-tables.opt b/gcc/config/mips/mips-tables.opt index 11be4639fc3..3114fce7c70 100644 --- a/gcc/config/mips/mips-tables.opt +++ b/gcc/config/mips/mips-tables.opt @@ -679,26 +679,29 @@ EnumValue Enum(mips_arch_opt_value) String(loongson3a) Value(96) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon) Value(97) Canonical +Enum(mips_arch_opt_value) String(gs464) Value(97) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon+) Value(98) Canonical +Enum(mips_arch_opt_value) String(octeon) Value(98) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon2) Value(99) Canonical +Enum(mips_arch_opt_value) String(octeon+) Value(99) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon3) Value(100) Canonical +Enum(mips_arch_opt_value) String(octeon2) Value(100) Canonical EnumValue -Enum(mips_arch_opt_value) String(xlp) Value(101) Canonical +Enum(mips_arch_opt_value) String(octeon3) Value(101) Canonical EnumValue -Enum(mips_arch_opt_value) String(i6400) Value(102) Canonical +Enum(mips_arch_opt_value) String(xlp) Value(102) Canonical EnumValue -Enum(mips_arch_opt_value) String(i6500) Value(103) Canonical +Enum(mips_arch_opt_value) String(i6400) Value(103) Canonical EnumValue -Enum(mips_arch_opt_value) String(p6600) Value(104) Canonical +Enum(mips_arch_opt_value) String(i6500) Value(104) Canonical + +EnumValue +Enum(mips_arch_opt_value) String(p6600) Value(105) Canonical diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 019a6dca752..51ae7f83e79 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -836,7 +836,7 @@ static const struct mips_rtx_cost_data { /* Loongson-2F */ DEFAULT_COSTS }, - { /* Loongson-3A */ + { /* Loongson gs464. */ DEFAULT_COSTS }, { /* M4k */ @@ -14614,7 +14614,7 @@ mips_issue_rate (void) case PROCESSOR_LOONGSON_2E: case PROCESSOR_LOONGSON_2F: - case PROCESSOR_LOONGSON_3A: + case PROCESSOR_GS464: case PROCESSOR_P5600: case PROCESSOR_P6600: return 4; @@ -14746,7 +14746,7 @@ mips_multipass_dfa_lookahead (void) if (TUNE_SB1) return 4; - if (TUNE_LOONGSON_2EF || TUNE_LOONGSON_3A) + if (TUNE_LOONGSON_2EF || TUNE_GS464) return 4; if (TUNE_OCTEON) @@ -20171,16 +20171,18 @@ mips_option_override (void) if (TARGET_LOONGSON_MMI && !TARGET_HARD_FLOAT_ABI) error ("%<-mloongson-mmi%> must be used with %<-mhard-float%>"); - /* Default to enable Loongson MMI on Longson 2e, 2f or 3a target. */ + /* Default to enable Loongson MMI on Longson 2e, 2f or gs464 target. */ if ((target_flags_explicit & MASK_LOONGSON_MMI) == 0 && ((strcmp (mips_arch_info->name, "loongson2e") == 0) || (strcmp (mips_arch_info->name, "loongson2f") == 0) - || (strcmp (mips_arch_info->name, "loongson3a") == 0))) + || (strcmp (mips_arch_info->name, "loongson3a") == 0) + || (strcmp (mips_arch_info->name, "gs464") == 0))) target_flags |= MASK_LOONGSON_MMI; - /* Default to enable Loongson EXT on Longson 3a target. */ + /* Default to enable Loongson EXT on Longson gs464 target. */ if ((target_flags_explicit & MASK_LOONGSON_EXT) == 0 - && (strcmp (mips_arch_info->name, "loongson3a") == 0)) + && ((strcmp (mips_arch_info->name, "loongson3a") == 0) + || (strcmp (mips_arch_info->name, "gs464") == 0))) target_flags |= MASK_LOONGSON_EXT; /* .eh_frame addresses should be the same width as a C pointer. diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index b75646d66ce..6d27c3da9fd 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -266,7 +266,7 @@ struct mips_cpu_info { #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E) #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F) #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F) -#define TARGET_LOONGSON_3A (mips_arch == PROCESSOR_LOONGSON_3A) +#define TARGET_GS464 (mips_arch == PROCESSOR_GS464) #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900) #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000) #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120) @@ -298,7 +298,7 @@ struct mips_cpu_info { || mips_tune == PROCESSOR_74KF3_2) #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \ || mips_tune == PROCESSOR_LOONGSON_2F) -#define TUNE_LOONGSON_3A (mips_tune == PROCESSOR_LOONGSON_3A) +#define TUNE_GS464 (mips_tune == PROCESSOR_GS464) #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000) #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900) #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000) @@ -790,7 +790,8 @@ struct mips_cpu_info { %{march=mips32r6: -mips32r6} \ %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \ |march=xlr: -mips64} \ - %{march=mips64r2|march=loongson3a|march=octeon|march=xlp: -mips64r2} \ + %{march=mips64r2|march=loongson3a|march=gs464|march=octeon \ + |march=xlp: -mips64r2} \ %{march=mips64r3: -mips64r3} \ %{march=mips64r5: -mips64r5} \ %{march=mips64r6|march=i6400|march=i6500|march=p6600: -mips64r6}}" @@ -946,7 +947,7 @@ struct mips_cpu_info { /* ISA has 32 single-precision registers. */ #define ISA_HAS_ODD_SPREG ((mips_isa_rev >= 1 \ - && !TARGET_LOONGSON_3A) \ + && !TARGET_GS464) \ || TARGET_FLOAT64 \ || TARGET_MIPS5900) @@ -989,7 +990,7 @@ struct mips_cpu_info { because the former are faster and can also have the effect of reducing code size. */ #define ISA_AVOID_DIV_HILO ((TARGET_LOONGSON_2EF \ - || TARGET_LOONGSON_3A) \ + || TARGET_GS464) \ && !TARGET_MIPS16) /* ISA supports instructions DDIV and DDIVU. */ @@ -1082,14 +1083,14 @@ struct mips_cpu_info { 'd = [+-] (a * b [+-] c)'. */ #define ISA_HAS_FUSED_MADD4 (mips_madd4 \ && (TARGET_MIPS8000 \ - || TARGET_LOONGSON_3A)) + || TARGET_GS464)) /* ISA has 4 operand unfused madd instructions of the form 'd = [+-] (a * b [+-] c)'. */ #define ISA_HAS_UNFUSED_MADD4 (mips_madd4 \ && ISA_HAS_FP4 \ && !TARGET_MIPS8000 \ - && !TARGET_LOONGSON_3A) + && !TARGET_GS464) /* ISA has 3 operand r6 fused madd instructions of the form 'c = c [+-] (a * b)'. */ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index c8128d4d530..1ae8f73ff37 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -37,7 +37,7 @@ 74kf3_2 loongson_2e loongson_2f - loongson_3a + gs464 m4k octeon octeon2 @@ -1174,7 +1174,7 @@ (include "9000.md") (include "10000.md") (include "loongson2ef.md") -(include "loongson3a.md") +(include "gs464.md") (include "octeon.md") (include "sb1.md") (include "sr71k.md") diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 2f0c33969c1..151d4378478 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -20768,7 +20768,7 @@ The processor names are: @samp{1004kc}, @samp{1004kf2_1}, @samp{1004kf1_1}, @samp{i6400}, @samp{i6500}, @samp{interaptiv}, -@samp{loongson2e}, @samp{loongson2f}, @samp{loongson3a}, +@samp{loongson2e}, @samp{loongson2f}, @samp{gs464}, @samp{m4k}, @samp{m14k}, @samp{m14kc}, @samp{m14ke}, @samp{m14kec}, @samp{m5100}, @samp{m5101}, -- 2.11.0 From patchwork Tue Oct 16 02:50:30 2018 Content-Type: text/plain; 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16 Oct 2018 02:50:48 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.0 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=1647 X-HELO: mail-oi1-f177.google.com Received: from mail-oi1-f177.google.com (HELO mail-oi1-f177.google.com) (209.85.167.177) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 16 Oct 2018 02:50:43 +0000 Received: by mail-oi1-f177.google.com with SMTP id k64-v6so16786344oia.13 for ; Mon, 15 Oct 2018 19:50:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to:cc; bh=FWZfGH43DJcIyeLt39VEzFPG/8wjai8r+pcZ5HFQYlU=; b=aPfd1ivC0ydj5RoneRryGEJpU8qKb+gfPpVcGtbYel3Zx3+Q9CT4/yoYbZvMppXNMR 4ITRYNcm3pmmG2HLkKRZQjfrHc8w3t0FuBpp1/TFyNvxNj5rBQesUV+y/h/egkKGq9I6 RFqV4MYAV2gSWhym89M8EUyjL6Uo1m4RIrEJvhuKxQfIhTXa0TLk5RLbg27ZHNTneiJf pLZQ+gFyjmEiDZz393hsgkkYYUZO2WvgyERe1G2Csn46FtD9zS6YOtRbGtNe5XJRqTpX rh9XTCpjAq+J87kCre386zHcZJuKN6RA8bBuTWn0DNSAXLnGH9sSCDE/kAfq10shueDP xA4g== MIME-Version: 1.0 From: Paul Hua Date: Tue, 16 Oct 2018 10:50:30 +0800 Message-ID: Subject: [PATCH v3 5/6] [MIPS] Add Loongson 3A2000/3A3000 processor support To: gcc-patches Cc: Matthew Fortune , "Jeff Law (law@redhat.com)" X-IsSubscribed: yes From 55047aa22e40de2637fbab4b5e246dfc4ca191f8 Mon Sep 17 00:00:00 2001 From: Chenghua Xu Date: Mon, 3 Sep 2018 19:45:15 +0800 Subject: [PATCH 5/6] Add support for Loongson 3A2000/3A3000 proccessor. gcc/ * config/mips/gs464e.md: New. * config/mips/mips-cpus.def: Define gs464e. * config/mips/mips-tables.opt: Regenerate. * config/mips/mips.c (mips_rtx_cost_data): Add DEFAULT_COSTS for gs464e. (mips_issue_rate): Add support for gs464e. (mips_multipass_dfa_lookahead): Likewise. (mips_option_override): Enable MMI, EXT and EXT2 for gs464e. * config/mips/mips.h: Define TARGET_GS464E and TUNE_GS464E. (MIPS_ISA_LEVEL_SPEC): Infer mips64r2 from gs464e. (ISA_HAS_FUSED_MADD4): Enable for TARGET_GS464E. (ISA_HAS_UNFUSED_MADD4): Exclude TARGET_GS464E. * config/mips/mips.md: Include gs464e.md. (processor): Add gs464e. * doc/invoke.texi: Add gs464e to supported architectures. --- gcc/config/mips/gs464e.md | 137 ++++++++++++++++++++++++++++++++++++++++ gcc/config/mips/mips-cpus.def | 1 + gcc/config/mips/mips-tables.opt | 19 +++--- gcc/config/mips/mips.c | 22 +++++-- gcc/config/mips/mips.h | 10 ++- gcc/config/mips/mips.md | 2 + gcc/doc/invoke.texi | 2 +- 7 files changed, 176 insertions(+), 17 deletions(-) create mode 100644 gcc/config/mips/gs464e.md diff --git a/gcc/config/mips/gs464e.md b/gcc/config/mips/gs464e.md new file mode 100644 index 00000000000..60e0e6b0463 --- /dev/null +++ b/gcc/config/mips/gs464e.md @@ -0,0 +1,137 @@ +;; Pipeline model for Loongson gs464e cores. + +;; Copyright (C) 2018 Free Software Foundation, Inc. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 3, or (at your +;; option) any later version. +;; +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +;; Uncomment the following line to output automata for debugging. +;; (automata_option "v") + +;; Automaton for integer instructions. +(define_automaton "gs464e_a_alu") + +;; Automaton for floating-point instructions. +(define_automaton "gs464e_a_falu") + +;; Automaton for memory operations. +(define_automaton "gs464e_a_mem") + +;; Describe the resources. + +(define_cpu_unit "gs464e_alu1" "gs464e_a_alu") +(define_cpu_unit "gs464e_alu2" "gs464e_a_alu") +(define_cpu_unit "gs464e_mem1" "gs464e_a_mem") +(define_cpu_unit "gs464e_mem2" "gs464e_a_mem") +(define_cpu_unit "gs464e_falu1" "gs464e_a_falu") +(define_cpu_unit "gs464e_falu2" "gs464e_a_falu") + +;; Describe instruction reservations. + +(define_insn_reservation "gs464e_arith" 1 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "arith,clz,const,logical, + move,nop,shift,signext,slt")) + "gs464e_alu1 | gs464e_alu2") + +(define_insn_reservation "gs464e_branch" 1 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "branch,jump,call,condmove,trap")) + "gs464e_alu1 | gs464e_alu2") + +(define_insn_reservation "gs464e_mfhilo" 1 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "mfhi,mflo,mthi,mtlo")) + "gs464e_alu1 | gs464e_alu2") + +;; Operation imul3nc is fully pipelined. +(define_insn_reservation "gs464e_imul3nc" 5 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "imul3nc")) + "gs464e_alu1 | gs464e_alu2") + +(define_insn_reservation "gs464e_imul" 7 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "imul,imadd")) + "gs464e_alu1 | gs464e_alu2") + +(define_insn_reservation "gs464e_idiv_si" 12 + (and (eq_attr "cpu" "gs464e") + (and (eq_attr "type" "idiv") + (eq_attr "mode" "SI"))) + "gs464e_alu1 | gs464e_alu2") + +(define_insn_reservation "gs464e_idiv_di" 25 + (and (eq_attr "cpu" "gs464e") + (and (eq_attr "type" "idiv") + (eq_attr "mode" "DI"))) + "gs464e_alu1 | gs464e_alu2") + +(define_insn_reservation "gs464e_load" 4 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "load")) + "gs464e_mem1 | gs464e_mem2") + +(define_insn_reservation "gs464e_fpload" 5 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "load,mfc,mtc")) + "gs464e_mem1 | gs464e_mem2") + +(define_insn_reservation "gs464e_prefetch" 0 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "prefetch,prefetchx")) + "gs464e_mem1 | gs464e_mem2") + +(define_insn_reservation "gs464e_store" 0 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "store,fpstore,fpidxstore")) + "gs464e_mem1 | gs464e_mem2") + +(define_insn_reservation "gs464e_fadd" 4 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "fadd,fmul,fmadd")) + "gs464e_falu1 | gs464e_falu2") + +(define_insn_reservation "gs464e_fcmp" 2 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "fabs,fcmp,fmove,fneg")) + "gs464e_falu1 | gs464e_falu2") + +(define_insn_reservation "gs464e_fcvt" 4 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "fcvt")) + "gs464e_falu1 | gs464e_falu2") + +(define_insn_reservation "gs464e_fdiv_sf" 12 + (and (eq_attr "cpu" "gs464e") + (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt") + (eq_attr "mode" "SF"))) + "gs464e_falu1 | gs464e_falu2") + +(define_insn_reservation "gs464e_fdiv_df" 19 + (and (eq_attr "cpu" "gs464e") + (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt") + (eq_attr "mode" "DF"))) + "gs464e_falu1 | gs464e_falu2") + +;; Force single-dispatch for unknown or multi. +(define_insn_reservation "gs464e_unknown" 1 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "unknown,multi,atomic,syncloop")) + "gs464e_alu1 + gs464e_alu2 + gs464e_falu1 + + gs464e_falu2 + gs464e_mem1 + gs464e_mem2") + +;; End of DFA-based pipeline description for gs464e diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def index eabe045cf39..b05b455c3c5 100644 --- a/gcc/config/mips/mips-cpus.def +++ b/gcc/config/mips/mips-cpus.def @@ -164,6 +164,7 @@ MIPS_CPU ("xlr", PROCESSOR_XLR, 64, PTF_AVOID_BRANCHLIKELY_SPEED) /* MIPS64 Release 2 processors. */ MIPS_CPU ("loongson3a", PROCESSOR_GS464, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("gs464", PROCESSOR_GS464, 65, PTF_AVOID_BRANCHLIKELY_SPEED) +MIPS_CPU ("gs464e", PROCESSOR_GS464E, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("octeon+", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("octeon2", PROCESSOR_OCTEON2, 65, PTF_AVOID_BRANCHLIKELY_SPEED) diff --git a/gcc/config/mips/mips-tables.opt b/gcc/config/mips/mips-tables.opt index 3114fce7c70..539266aec89 100644 --- a/gcc/config/mips/mips-tables.opt +++ b/gcc/config/mips/mips-tables.opt @@ -682,26 +682,29 @@ EnumValue Enum(mips_arch_opt_value) String(gs464) Value(97) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon) Value(98) Canonical +Enum(mips_arch_opt_value) String(gs464e) Value(98) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon+) Value(99) Canonical +Enum(mips_arch_opt_value) String(octeon) Value(99) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon2) Value(100) Canonical +Enum(mips_arch_opt_value) String(octeon+) Value(100) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon3) Value(101) Canonical +Enum(mips_arch_opt_value) String(octeon2) Value(101) Canonical EnumValue -Enum(mips_arch_opt_value) String(xlp) Value(102) Canonical +Enum(mips_arch_opt_value) String(octeon3) Value(102) Canonical EnumValue -Enum(mips_arch_opt_value) String(i6400) Value(103) Canonical +Enum(mips_arch_opt_value) String(xlp) Value(103) Canonical EnumValue -Enum(mips_arch_opt_value) String(i6500) Value(104) Canonical +Enum(mips_arch_opt_value) String(i6400) Value(104) Canonical EnumValue -Enum(mips_arch_opt_value) String(p6600) Value(105) Canonical +Enum(mips_arch_opt_value) String(i6500) Value(105) Canonical + +EnumValue +Enum(mips_arch_opt_value) String(p6600) Value(106) Canonical diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 51ae7f83e79..e6fd0ca4a41 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -839,6 +839,9 @@ static const struct mips_rtx_cost_data { /* Loongson gs464. */ DEFAULT_COSTS }, + { /* Loongson gs464e. */ + DEFAULT_COSTS + }, { /* M4k */ DEFAULT_COSTS }, @@ -14615,6 +14618,7 @@ mips_issue_rate (void) case PROCESSOR_LOONGSON_2E: case PROCESSOR_LOONGSON_2F: case PROCESSOR_GS464: + case PROCESSOR_GS464E: case PROCESSOR_P5600: case PROCESSOR_P6600: return 4; @@ -14746,7 +14750,7 @@ mips_multipass_dfa_lookahead (void) if (TUNE_SB1) return 4; - if (TUNE_LOONGSON_2EF || TUNE_GS464) + if (TUNE_LOONGSON_2EF || TUNE_GS464 || TUNE_GS464E) return 4; if (TUNE_OCTEON) @@ -20171,20 +20175,28 @@ mips_option_override (void) if (TARGET_LOONGSON_MMI && !TARGET_HARD_FLOAT_ABI) error ("%<-mloongson-mmi%> must be used with %<-mhard-float%>"); - /* Default to enable Loongson MMI on Longson 2e, 2f or gs464 target. */ + /* Default to enable Loongson MMI on Longson 2e, 2f, gs464 + * or gs464e target. */ if ((target_flags_explicit & MASK_LOONGSON_MMI) == 0 && ((strcmp (mips_arch_info->name, "loongson2e") == 0) || (strcmp (mips_arch_info->name, "loongson2f") == 0) || (strcmp (mips_arch_info->name, "loongson3a") == 0) - || (strcmp (mips_arch_info->name, "gs464") == 0))) + || (strcmp (mips_arch_info->name, "gs464") == 0) + || (strcmp (mips_arch_info->name, "gs464e") == 0))) target_flags |= MASK_LOONGSON_MMI; - /* Default to enable Loongson EXT on Longson gs464 target. */ + /* Default to enable Loongson EXT on Longson gs464 or gs464e target. */ if ((target_flags_explicit & MASK_LOONGSON_EXT) == 0 && ((strcmp (mips_arch_info->name, "loongson3a") == 0) - || (strcmp (mips_arch_info->name, "gs464") == 0))) + || (strcmp (mips_arch_info->name, "gs464") == 0) + || (strcmp (mips_arch_info->name, "gs464e") == 0))) target_flags |= MASK_LOONGSON_EXT; + /* Default to enable Loongson EXT2 on gs464e target. */ + if ((target_flags_explicit & MASK_LOONGSON_EXT2) == 0 + && (strcmp (mips_arch_info->name, "gs464e") == 0)) + target_flags |= MASK_LOONGSON_EXT2; + /* .eh_frame addresses should be the same width as a C pointer. Most MIPS ABIs support only one pointer size, so the assembler will usually know exactly how big an .eh_frame address is. diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 6d27c3da9fd..b4bb4498572 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -267,6 +267,7 @@ struct mips_cpu_info { #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F) #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F) #define TARGET_GS464 (mips_arch == PROCESSOR_GS464) +#define TARGET_GS464E (mips_arch == PROCESSOR_GS464E) #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900) #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000) #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120) @@ -299,6 +300,7 @@ struct mips_cpu_info { #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \ || mips_tune == PROCESSOR_LOONGSON_2F) #define TUNE_GS464 (mips_tune == PROCESSOR_GS464) +#define TUNE_GS464E (mips_tune == PROCESSOR_GS464E) #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000) #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900) #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000) @@ -790,7 +792,7 @@ struct mips_cpu_info { %{march=mips32r6: -mips32r6} \ %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \ |march=xlr: -mips64} \ - %{march=mips64r2|march=loongson3a|march=gs464|march=octeon \ + %{march=mips64r2|march=loongson3a|march=gs464|march=gs464e|march=octeon \ |march=xlp: -mips64r2} \ %{march=mips64r3: -mips64r3} \ %{march=mips64r5: -mips64r5} \ @@ -1083,14 +1085,16 @@ struct mips_cpu_info { 'd = [+-] (a * b [+-] c)'. */ #define ISA_HAS_FUSED_MADD4 (mips_madd4 \ && (TARGET_MIPS8000 \ - || TARGET_GS464)) + || TARGET_GS464 \ + || TARGET_GS464E)) /* ISA has 4 operand unfused madd instructions of the form 'd = [+-] (a * b [+-] c)'. */ #define ISA_HAS_UNFUSED_MADD4 (mips_madd4 \ && ISA_HAS_FP4 \ && !TARGET_MIPS8000 \ - && !TARGET_GS464) + && !TARGET_GS464 \ + && !TARGET_GS464E) /* ISA has 3 operand r6 fused madd instructions of the form 'c = c [+-] (a * b)'. */ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 1ae8f73ff37..15f0e479552 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -38,6 +38,7 @@ loongson_2e loongson_2f gs464 + gs464e m4k octeon octeon2 @@ -1175,6 +1176,7 @@ (include "10000.md") (include "loongson2ef.md") (include "gs464.md") +(include "gs464e.md") (include "octeon.md") (include "sb1.md") (include "sr71k.md") diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 151d4378478..ed97bc9ac0b 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -20768,7 +20768,7 @@ The processor names are: @samp{1004kc}, @samp{1004kf2_1}, @samp{1004kf1_1}, @samp{i6400}, @samp{i6500}, @samp{interaptiv}, -@samp{loongson2e}, @samp{loongson2f}, @samp{gs464}, +@samp{loongson2e}, @samp{loongson2f}, @samp{gs464}, @samp{gs464e}, @samp{m4k}, @samp{m14k}, @samp{m14kc}, @samp{m14ke}, @samp{m14kec}, @samp{m5100}, @samp{m5101}, -- 2.11.0 From patchwork Tue Oct 16 02:50:35 2018 Content-Type: text/plain; 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16 Oct 2018 02:50:53 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-ot1-f43.google.com Received: from mail-ot1-f43.google.com (HELO mail-ot1-f43.google.com) (209.85.210.43) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 16 Oct 2018 02:50:49 +0000 Received: by mail-ot1-f43.google.com with SMTP id l1so21001893otj.5 for ; Mon, 15 Oct 2018 19:50:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to:cc; bh=zj1PB5487OVp6u/ucjigGzsI80BWJvXlnU8eIAijGYY=; b=PpIXp1LfG/w+w98OxuERrI4vRzgfvKZPTcS77gqCB8ZHomMacw7sJ8GvZTpxJPIk21 u5VNy7+B/xwo/5KK1qCFetKsVJ3luY4jKdXVTkvZKDHGGjDChfLqlu0XU/5cSToR3ItJ zPUqoLXKm4/3zQhESM+sgGBT/vcichcGptRbEvNsOTeabNN9Pu/oH5o+XS5LtT2qfQFB ZaWsazCllyyEU2xsSMMJfNrEPMtVKNrf3uAKIaU/mRmYJz/yslhxlW0rebP8bE0A7v+X DfvdQbrCs6l+wuDAGjt4wgjXKk4gy6CqkIytW//9tqwk63NTJkGYnGe+Qtckvb4YzgEA AaUg== MIME-Version: 1.0 From: Paul Hua Date: Tue, 16 Oct 2018 10:50:35 +0800 Message-ID: Subject: [PATCH v3 6/6] [MIPS] Add Loongson 2K1000 processor support To: gcc-patches Cc: Matthew Fortune , "Jeff Law (law@redhat.com)" X-IsSubscribed: yes From 0df9c46bea628086ca2c4b5db24c28cec912d319 Mon Sep 17 00:00:00 2001 From: Chenghua Xu Date: Mon, 3 Sep 2018 20:01:54 +0800 Subject: [PATCH 6/6] Add support for Loongson 2K1000 proccessor. gcc/ * config/mips/gs264e.md: New. * config/mips/mips-cpus.def: Define gs264e. * config/mips/mips-tables.opt: Regenerate. * config/mips/mips.c (mips_rtx_cost_data): Add DEFAULT_COSTS for gs264e. (mips_issue_rate): Add support for gs264e. (mips_multipass_dfa_lookahead): Likewise. (mips_option_override): Enable MMI, EXT, EXT2 and MSA for gs264e. * config/mips/mips.h: Define TARGET_GS264E and TUNE_GS264E. (MIPS_ISA_LEVEL_SPEC): Infer mips64r2 from gs264e. (ISA_HAS_FUSED_MADD4): Enable for TARGET_GS264E. (ISA_HAS_UNFUSED_MADD4): Exclude TARGET_GS264E. * config/mips/mips.md: Include gs264e.md. (processor): Add gs264e. * config/mips/mips.opt (MSA): Use Mask instead of Var. * doc/invoke.texi: Add gs264e to supported architectures. --- gcc/config/mips/gs264e.md | 133 ++++++++++++++++++++++++++++++++++++++++ gcc/config/mips/mips-cpus.def | 1 + gcc/config/mips/mips-tables.opt | 19 +++--- gcc/config/mips/mips.c | 29 ++++++--- gcc/config/mips/mips.h | 12 ++-- gcc/config/mips/mips.md | 2 + gcc/config/mips/mips.opt | 2 +- gcc/doc/invoke.texi | 1 + 8 files changed, 178 insertions(+), 21 deletions(-) create mode 100644 gcc/config/mips/gs264e.md diff --git a/gcc/config/mips/gs264e.md b/gcc/config/mips/gs264e.md new file mode 100644 index 00000000000..8f1f9e17e08 --- /dev/null +++ b/gcc/config/mips/gs264e.md @@ -0,0 +1,133 @@ +;; Pipeline model for Loongson gs264e cores. + +;; Copyright (C) 2018 Free Software Foundation, Inc. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 3, or (at your +;; option) any later version. +;; +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +;; Uncomment the following line to output automata for debugging. +;; (automata_option "v") + +;; Automaton for integer instructions. +(define_automaton "gs264e_a_alu") + +;; Automaton for floating-point instructions. +(define_automaton "gs264e_a_falu") + +;; Automaton for memory operations. +(define_automaton "gs264e_a_mem") + +;; Describe the resources. + +(define_cpu_unit "gs264e_alu1" "gs264e_a_alu") +(define_cpu_unit "gs264e_mem1" "gs264e_a_mem") +(define_cpu_unit "gs264e_falu1" "gs264e_a_falu") + +;; Describe instruction reservations. + +(define_insn_reservation "gs264e_arith" 1 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "arith,clz,const,logical, + move,nop,shift,signext,slt")) + "gs264e_alu1") + +(define_insn_reservation "gs264e_branch" 1 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "branch,jump,call,condmove,trap")) + "gs264e_alu1") + +(define_insn_reservation "gs264e_mfhilo" 1 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "mfhi,mflo,mthi,mtlo")) + "gs264e_alu1") + +;; Operation imul3nc is fully pipelined. +(define_insn_reservation "gs264e_imul3nc" 7 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "imul3nc")) + "gs264e_alu1") + +(define_insn_reservation "gs264e_imul" 7 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "imul,imadd")) + "gs264e_alu1") + +(define_insn_reservation "gs264e_idiv_si" 12 + (and (eq_attr "cpu" "gs264e") + (and (eq_attr "type" "idiv") + (eq_attr "mode" "SI"))) + "gs264e_alu1") + +(define_insn_reservation "gs264e_idiv_di" 25 + (and (eq_attr "cpu" "gs264e") + (and (eq_attr "type" "idiv") + (eq_attr "mode" "DI"))) + "gs264e_alu1") + +(define_insn_reservation "gs264e_load" 4 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "load")) + "gs264e_mem1") + +(define_insn_reservation "gs264e_fpload" 4 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "load,mfc,mtc")) + "gs264e_mem1") + +(define_insn_reservation "gs264e_prefetch" 0 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "prefetch,prefetchx")) + "gs264e_mem1") + +(define_insn_reservation "gs264e_store" 0 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "store,fpstore,fpidxstore")) + "gs264e_mem1") + +(define_insn_reservation "gs264e_fadd" 4 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "fadd,fmul,fmadd")) + "gs264e_falu1") + +(define_insn_reservation "gs264e_fcmp" 2 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "fabs,fcmp,fmove,fneg")) + "gs264e_falu1") + +(define_insn_reservation "gs264e_fcvt" 4 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "fcvt")) + "gs264e_falu1") + +(define_insn_reservation "gs264e_fdiv_sf" 12 + (and (eq_attr "cpu" "gs264e") + (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt") + (eq_attr "mode" "SF"))) + "gs264e_falu1") + +(define_insn_reservation "gs264e_fdiv_df" 19 + (and (eq_attr "cpu" "gs264e") + (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt") + (eq_attr "mode" "DF"))) + "gs264e_falu1") + +;; Force single-dispatch for unknown or multi. +(define_insn_reservation "gs264e_unknown" 1 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "unknown,multi,atomic,syncloop")) + "gs264e_alu1 + gs264e_falu1 + gs264e_mem1") + +;; End of DFA-based pipeline description for gs264e diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def index b05b455c3c5..747739f4b90 100644 --- a/gcc/config/mips/mips-cpus.def +++ b/gcc/config/mips/mips-cpus.def @@ -165,6 +165,7 @@ MIPS_CPU ("xlr", PROCESSOR_XLR, 64, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("loongson3a", PROCESSOR_GS464, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("gs464", PROCESSOR_GS464, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("gs464e", PROCESSOR_GS464E, 65, PTF_AVOID_BRANCHLIKELY_SPEED) +MIPS_CPU ("gs264e", PROCESSOR_GS264E, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("octeon+", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("octeon2", PROCESSOR_OCTEON2, 65, PTF_AVOID_BRANCHLIKELY_SPEED) diff --git a/gcc/config/mips/mips-tables.opt b/gcc/config/mips/mips-tables.opt index 539266aec89..7ab2cf5414b 100644 --- a/gcc/config/mips/mips-tables.opt +++ b/gcc/config/mips/mips-tables.opt @@ -685,26 +685,29 @@ EnumValue Enum(mips_arch_opt_value) String(gs464e) Value(98) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon) Value(99) Canonical +Enum(mips_arch_opt_value) String(gs264e) Value(99) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon+) Value(100) Canonical +Enum(mips_arch_opt_value) String(octeon) Value(100) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon2) Value(101) Canonical +Enum(mips_arch_opt_value) String(octeon+) Value(101) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon3) Value(102) Canonical +Enum(mips_arch_opt_value) String(octeon2) Value(102) Canonical EnumValue -Enum(mips_arch_opt_value) String(xlp) Value(103) Canonical +Enum(mips_arch_opt_value) String(octeon3) Value(103) Canonical EnumValue -Enum(mips_arch_opt_value) String(i6400) Value(104) Canonical +Enum(mips_arch_opt_value) String(xlp) Value(104) Canonical EnumValue -Enum(mips_arch_opt_value) String(i6500) Value(105) Canonical +Enum(mips_arch_opt_value) String(i6400) Value(105) Canonical EnumValue -Enum(mips_arch_opt_value) String(p6600) Value(106) Canonical +Enum(mips_arch_opt_value) String(i6500) Value(106) Canonical + +EnumValue +Enum(mips_arch_opt_value) String(p6600) Value(107) Canonical diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index e6fd0ca4a41..cf157776d2d 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -842,6 +842,9 @@ static const struct mips_rtx_cost_data { /* Loongson gs464e. */ DEFAULT_COSTS }, + { /* Loongson gs264e. */ + DEFAULT_COSTS + }, { /* M4k */ DEFAULT_COSTS }, @@ -14605,6 +14608,7 @@ mips_issue_rate (void) case PROCESSOR_OCTEON2: case PROCESSOR_OCTEON3: case PROCESSOR_I6400: + case PROCESSOR_GS264E: return 2; case PROCESSOR_SB1: @@ -14753,7 +14757,7 @@ mips_multipass_dfa_lookahead (void) if (TUNE_LOONGSON_2EF || TUNE_GS464 || TUNE_GS464E) return 4; - if (TUNE_OCTEON) + if (TUNE_OCTEON || TUNE_GS264E) return 2; if (TUNE_P5600 || TUNE_P6600 || TUNE_I6400) @@ -20175,28 +20179,37 @@ mips_option_override (void) if (TARGET_LOONGSON_MMI && !TARGET_HARD_FLOAT_ABI) error ("%<-mloongson-mmi%> must be used with %<-mhard-float%>"); - /* Default to enable Loongson MMI on Longson 2e, 2f, gs464 - * or gs464e target. */ + /* Default to enable Loongson MMI on Longson 2e, 2f, gs464, gs464e + * or gs264e target. */ if ((target_flags_explicit & MASK_LOONGSON_MMI) == 0 && ((strcmp (mips_arch_info->name, "loongson2e") == 0) || (strcmp (mips_arch_info->name, "loongson2f") == 0) || (strcmp (mips_arch_info->name, "loongson3a") == 0) || (strcmp (mips_arch_info->name, "gs464") == 0) - || (strcmp (mips_arch_info->name, "gs464e") == 0))) + || (strcmp (mips_arch_info->name, "gs464e") == 0) + || (strcmp (mips_arch_info->name, "gs264e") == 0))) target_flags |= MASK_LOONGSON_MMI; - /* Default to enable Loongson EXT on Longson gs464 or gs464e target. */ + /* Default to enable Loongson EXT on Longson gs464, gs464e + * or gs264e target. */ if ((target_flags_explicit & MASK_LOONGSON_EXT) == 0 && ((strcmp (mips_arch_info->name, "loongson3a") == 0) || (strcmp (mips_arch_info->name, "gs464") == 0) - || (strcmp (mips_arch_info->name, "gs464e") == 0))) + || (strcmp (mips_arch_info->name, "gs464e") == 0) + || (strcmp (mips_arch_info->name, "gs264e") == 0))) target_flags |= MASK_LOONGSON_EXT; - /* Default to enable Loongson EXT2 on gs464e target. */ + /* Default to enable Loongson EXT2 on gs464e or gs264e target. */ if ((target_flags_explicit & MASK_LOONGSON_EXT2) == 0 - && (strcmp (mips_arch_info->name, "gs464e") == 0)) + && ((strcmp (mips_arch_info->name, "gs464e") == 0) + || (strcmp (mips_arch_info->name, "gs264e") == 0))) target_flags |= MASK_LOONGSON_EXT2; + /* Default to enable MSA on gs264e target. */ + if ((target_flags_explicit & MASK_MSA) == 0 + && (strcmp (mips_arch_info->name, "gs264e") == 0)) + target_flags |= MASK_MSA; + /* .eh_frame addresses should be the same width as a C pointer. Most MIPS ABIs support only one pointer size, so the assembler will usually know exactly how big an .eh_frame address is. diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index b4bb4498572..5953594af0b 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -268,6 +268,7 @@ struct mips_cpu_info { #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F) #define TARGET_GS464 (mips_arch == PROCESSOR_GS464) #define TARGET_GS464E (mips_arch == PROCESSOR_GS464E) +#define TARGET_GS264E (mips_arch == PROCESSOR_GS264E) #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900) #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000) #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120) @@ -301,6 +302,7 @@ struct mips_cpu_info { || mips_tune == PROCESSOR_LOONGSON_2F) #define TUNE_GS464 (mips_tune == PROCESSOR_GS464) #define TUNE_GS464E (mips_tune == PROCESSOR_GS464E) +#define TUNE_GS264E (mips_tune == PROCESSOR_GS264E) #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000) #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900) #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000) @@ -792,8 +794,8 @@ struct mips_cpu_info { %{march=mips32r6: -mips32r6} \ %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \ |march=xlr: -mips64} \ - %{march=mips64r2|march=loongson3a|march=gs464|march=gs464e|march=octeon \ - |march=xlp: -mips64r2} \ + %{march=mips64r2|march=loongson3a|march=gs464|march=gs464e|march=gs264e \ + |march=octeon|march=xlp: -mips64r2} \ %{march=mips64r3: -mips64r3} \ %{march=mips64r5: -mips64r5} \ %{march=mips64r6|march=i6400|march=i6500|march=p6600: -mips64r6}}" @@ -1086,7 +1088,8 @@ struct mips_cpu_info { #define ISA_HAS_FUSED_MADD4 (mips_madd4 \ && (TARGET_MIPS8000 \ || TARGET_GS464 \ - || TARGET_GS464E)) + || TARGET_GS464E \ + || TARGET_GS264E)) /* ISA has 4 operand unfused madd instructions of the form 'd = [+-] (a * b [+-] c)'. */ @@ -1094,7 +1097,8 @@ struct mips_cpu_info { && ISA_HAS_FP4 \ && !TARGET_MIPS8000 \ && !TARGET_GS464 \ - && !TARGET_GS464E) + && !TARGET_GS464E \ + && !TARGET_GS264E) /* ISA has 3 operand r6 fused madd instructions of the form 'c = c [+-] (a * b)'. */ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 15f0e479552..6ff75ea9c81 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -39,6 +39,7 @@ loongson_2f gs464 gs464e + gs264e m4k octeon octeon2 @@ -1177,6 +1178,7 @@ (include "loongson2ef.md") (include "gs464.md") (include "gs464e.md") +(include "gs264e.md") (include "octeon.md") (include "sb1.md") (include "sr71k.md") diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index c0c8005b025..16c33d12e22 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -300,7 +300,7 @@ Target Report Mask(MICROMIPS) Use microMIPS instructions. mmsa -Target Report Var(TARGET_MSA) +Target Report Mask(MSA) Use MIPS MSA Extension instructions. mmt diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index ed97bc9ac0b..5b5dd8aac6e 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -20769,6 +20769,7 @@ The processor names are: @samp{i6400}, @samp{i6500}, @samp{interaptiv}, @samp{loongson2e}, @samp{loongson2f}, @samp{gs464}, @samp{gs464e}, +@samp{gs264e}, @samp{m4k}, @samp{m14k}, @samp{m14kc}, @samp{m14ke}, @samp{m14kec}, @samp{m5100}, @samp{m5101}, -- 2.11.0