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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 10 Oct 2018 11:14:23 -0400 Received: from b01ledav003.gho.pok.ibm.com (b01ledav003.gho.pok.ibm.com [9.57.199.108]) by b01cxnp22033.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w9AFEML446465056 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 10 Oct 2018 15:14:22 GMT Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DE0BBB2067; Wed, 10 Oct 2018 11:12:23 -0400 (EDT) Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 94CE0B205F; Wed, 10 Oct 2018 11:12:23 -0400 (EDT) Received: from [9.10.86.107] (unknown [9.10.86.107]) by b01ledav003.gho.pok.ibm.com (Postfix) with ESMTP; Wed, 10 Oct 2018 11:12:23 -0400 (EDT) Subject: [PATCH, rs6000] testcase coverage for vec_sel builtins From: Will Schmidt Reply-To: will_schmidt@vnet.ibm.com To: Segher Boessenkool , Bill Schmidt , David Edelsohn Cc: GCC Patches Date: Wed, 10 Oct 2018 10:14:21 -0500 Mime-Version: 1.0 x-cbid: 18101015-2213-0000-0000-000003012374 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00009854; HX=3.00000242; KW=3.00000007; PH=3.00000004; SC=3.00000268; SDB=6.01100666; UDB=6.00569489; IPR=6.00880714; MB=3.00023695; MTD=3.00000008; XFM=3.00000015; UTC=2018-10-10 15:14:24 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18101015-2214-0000-0000-00005BD8ED55 Message-Id: <1539184461.16697.56.camel@brimstone.rchland.ibm.com> X-IsSubscribed: yes Hi, Add testcase coverage for the vec_sel builtins. Tested across assorted Linux platforms. OK for trunk? Thanks, -Will [testsuite] 2018-10-10 Will Schmidt * gcc.target/powerpc/fold-vec-select-char.c: New. * gcc.target/powerpc/fold-vec-select-double.c: New. * gcc.target/powerpc/fold-vec-select-float.c: New. * gcc.target/powerpc/fold-vec-select-int.c: New. * gcc.target/powerpc/fold-vec-select-longlong.c: New. * gcc.target/powerpc/fold-vec-select-short.c: New. diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-select-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-select-char.c new file mode 100644 index 0000000..5c82b39 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-select-char.c @@ -0,0 +1,46 @@ +/* Verify that overloaded built-ins for vec_sel with char + inputs produce the right code. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2" } */ + +#include + +vector bool char +test1_0 (vector bool char x, vector bool char y, vector bool char z) +{ + return vec_sel (x, y, z); +} + +vector bool char +test1_1 (vector bool char x,vector bool char y, vector unsigned char z) +{ + return vec_sel (x, y, z); +} + +vector signed char +test3_0 (vector signed char x,vector signed char y, vector bool char z) +{ + return vec_sel (x, y, z); +} + +vector signed char +test3_1 (vector signed char x,vector signed char y, vector unsigned char z) +{ + return vec_sel (x, y, z); +} + +vector unsigned char +test6_0 (vector unsigned char x,vector unsigned char y,vector bool char z) +{ + return vec_sel (x, y, z); +} + +vector unsigned char +test6_1 (vector unsigned char x,vector unsigned char y, vector unsigned char z) +{ + return vec_sel (x, y, z); +} + +/* { dg-final { scan-assembler-times {\mxxsel\M|\mvsel\M} 6 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-select-double.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-select-double.c new file mode 100644 index 0000000..02ae63a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-select-double.c @@ -0,0 +1,22 @@ +/* Verify that overloaded built-ins for vec_sel with + double inputs for VSX produce the right code. */ + +/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mvsx -mpower8-vector -O2" } */ + +#include + +vector double +test2_0 (vector double x, vector double y, vector bool long long z) +{ + return vec_sel (x, y, z); +} + +vector double +test2_1 (vector double x, vector double y, vector unsigned long z) +{ + return vec_sel (x, y, z); +} + +/* { dg-final { scan-assembler-times "xxsel" 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-select-float.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-select-float.c new file mode 100644 index 0000000..085ba8a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-select-float.c @@ -0,0 +1,22 @@ +/* Verify that overloaded built-ins for vec_sel with float + inputs for VSX produce the right code. */ + +/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2" } */ + +#include + +vector float +test1_0 (vector float x, vector float y, vector bool int z) +{ + return vec_sel (x, y, z); +} + +vector float +test1_1 (vector float x, vector float y, vector unsigned int z) +{ + return vec_sel (x, y, z); +} + +/* { dg-final { scan-assembler-times {\mxxsel\M|\mvsel\M} 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-select-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-select-int.c new file mode 100644 index 0000000..d62c06d --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-select-int.c @@ -0,0 +1,46 @@ +/* Verify that overloaded built-ins for vec_sel with int + inputs produce the right code. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2" } */ + +#include + +vector bool int +test1_0 (vector bool int x, vector bool int y, vector bool int z) +{ + return vec_sel (x, y, z); +} + +vector bool int +test1_1 (vector bool int x, vector bool int y, vector unsigned int z) +{ + return vec_sel (x, y, z); +} + +vector signed int +test3_0 (vector signed int x, vector signed int y, vector bool int z) +{ + return vec_sel (x, y, z); +} + +vector signed int +test3_1 (vector signed int x, vector signed int y, vector unsigned int z) +{ + return vec_sel (x, y, z); +} + +vector unsigned int +test6_0 (vector unsigned int x, vector unsigned int y, vector bool int z) +{ + return vec_sel (x, y, z); +} + +vector unsigned int +test6_1 (vector unsigned int x, vector unsigned int y, vector unsigned int z) +{ + return vec_sel (x, y, z); +} + +/* { dg-final { scan-assembler-times {\mxxsel\M|\mvsel\M} 6 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-select-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-select-longlong.c new file mode 100644 index 0000000..449c0f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-select-longlong.c @@ -0,0 +1,34 @@ +/* Verify that overloaded built-ins for vec_sel with long long + inputs produce the right code. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ + +#include + +vector bool long long +test1_0 (vector bool long long x,vector bool long long y, vector bool long long z) +{ + return vec_sel (x, y, z); +} + +vector bool long long +test1_1 (vector bool long long x, vector bool long long y, vector unsigned long long z) +{ + return vec_sel (x, y, z); +} + +vector signed long long +test3_0 (vector signed long long x, vector signed long long y, vector bool long long z) +{ + return vec_sel (x, y, z); +} + +vector unsigned long long +test3_1 (vector unsigned long long x, vector unsigned long long y, vector bool long long z) +{ + return vec_sel (x, y, z); +} + +/* { dg-final { scan-assembler-times "xxsel" 4 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-select-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-select-short.c new file mode 100644 index 0000000..baeeac0 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-select-short.c @@ -0,0 +1,46 @@ +/* Verify that overloaded built-ins for vec_sel with short + inputs produce the right code. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2" } */ + +#include + +vector bool short +test1_0 (vector bool short x, vector bool short y, vector bool short z) +{ + return vec_sel (x, y, z); +} + +vector bool short +test1_1 (vector bool short x, vector bool short y, vector unsigned short z) +{ + return vec_sel (x, y, z); +} + +vector signed short +test3_0 (vector signed short x, vector signed short y, vector bool short z) +{ + return vec_sel (x, y, z); +} + +vector signed short +test3_1 (vector signed short x, vector signed short y, vector unsigned short z) +{ + return vec_sel (x, y, z); +} + +vector unsigned short +test6_0 (vector unsigned short x, vector unsigned short y, vector bool short z) +{ + return vec_sel (x, y, z); +} + +vector unsigned short +test6_1 (vector unsigned short x, vector unsigned short y, vector unsigned short z) +{ + return vec_sel (x, y, z); +} + +/* { dg-final { scan-assembler-times {\mxxsel\M|\mvsel\M} 6 } } */