From patchwork Wed Sep 26 12:27:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 975060 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="FqFOdIJw"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42Ky016rs6z9s55 for ; Wed, 26 Sep 2018 22:28:17 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728101AbeIZSkd (ORCPT ); Wed, 26 Sep 2018 14:40:33 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:8707 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726880AbeIZSkc (ORCPT ); Wed, 26 Sep 2018 14:40:32 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 26 Sep 2018 05:27:52 -0700 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 26 Sep 2018 05:27:46 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 26 Sep 2018 05:27:46 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 26 Sep 2018 12:27:46 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Wed, 26 Sep 2018 12:27:46 +0000 Received: from moonraker.nvidia.com (Not Verified[10.21.132.143]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 26 Sep 2018 05:27:45 -0700 From: Jon Hunter To: Rob Herring , Mark Rutland , "Rafael J . Wysocki" , Kevin Hilman , Ulf Hansson , Greg Kroah-Hartman , Mathias Nyman , Thierry Reding CC: , , , Jon Hunter Subject: [PATCH 1/5] PM / Domains: Export symbol for genpd_dev_pm_attach_by_name Date: Wed, 26 Sep 2018 13:27:34 +0100 Message-ID: <1537964858-30332-2-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1537964858-30332-1-git-send-email-jonathanh@nvidia.com> References: <1537964858-30332-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1537964872; bh=1w1JFpmw3dg1UHjssFK9Cip16Tg6vgXkahZhvVTfVP0=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=FqFOdIJwfOG4t2aZW/hofstETrf5NITRLFU70HW0Dxo6bO+tSB4pDqbDJ6Xc5rZp6 cIHjDbgQuH1UiN7/10yxsQT3FLeHhGPjq4uOUdAwdcuwTiUtA5lv9IyFrPZJxL1Pad OEzZHbP0lRQEFeXS2jeFHPTLim+KAAHxYcrtWMeEFDWpPucISOJ2/V+5HIkn0cQVGU Bs0CXHvDoYHt7+abVFcdHlAjZZBGB0R+vIatSd3IoAsHuaAgWfEYkgLEY1mcY6XKWq Z/QsYdchGWBu84FZIjSKldhYVe/S0CAHDYOnwzGDX5v51SK8exC6HmkwrqasW49xIS KwZ8dlTh6Pl5g== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Export the symbol for genpd_dev_pm_attach_by_name() so that drivers built as modules can call this function. Signed-off-by: Jon Hunter --- drivers/base/power/domain.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/base/power/domain.c b/drivers/base/power/domain.c index 4b5714199490..b2bbe0d848d2 100644 --- a/drivers/base/power/domain.c +++ b/drivers/base/power/domain.c @@ -2397,6 +2397,7 @@ struct device *genpd_dev_pm_attach_by_name(struct device *dev, char *name) return genpd_dev_pm_attach_by_id(dev, index); } +EXPORT_SYMBOL_GPL(genpd_dev_pm_attach_by_name); static const struct of_device_id idle_state_match[] = { { .compatible = "domain-idle-state", }, From patchwork Wed Sep 26 12:27:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 975059 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="Ca2l7yhC"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42Kxzy41YCz9s1c for ; Wed, 26 Sep 2018 22:28:14 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728299AbeIZSkf (ORCPT ); Wed, 26 Sep 2018 14:40:35 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:12102 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726880AbeIZSke (ORCPT ); Wed, 26 Sep 2018 14:40:34 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 26 Sep 2018 05:27:13 -0700 Received: from HQMAIL103.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Wed, 26 Sep 2018 05:27:48 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Wed, 26 Sep 2018 05:27:48 -0700 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 26 Sep 2018 12:27:48 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Wed, 26 Sep 2018 12:27:48 +0000 Received: from moonraker.nvidia.com (Not Verified[10.21.132.143]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 26 Sep 2018 05:27:48 -0700 From: Jon Hunter To: Rob Herring , Mark Rutland , "Rafael J . Wysocki" , Kevin Hilman , Ulf Hansson , Greg Kroah-Hartman , Mathias Nyman , Thierry Reding CC: , , , Jon Hunter Subject: [PATCH 2/5] dt-bindings: usb: xhci-tegra: Add power-domain details Date: Wed, 26 Sep 2018 13:27:35 +0100 Message-ID: <1537964858-30332-3-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1537964858-30332-1-git-send-email-jonathanh@nvidia.com> References: <1537964858-30332-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1537964833; bh=QiCY1OBjJA8jzGGo2BTTCq8k6o92/xxPDihoF/PByhg=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=Ca2l7yhCYKP6ACSOjYSaPvGV01Pw/azoKFyaMCyIagbZYqksjfFPcvDWl8xangSAK 6FQ3qiGxY74oiess7VvoAqsLXl4tGnLoUYvSKEcEpuuik1CLLwEH1EZFiCJnSs4NXI SSLbtAFxMxUCk+t+13Acinlr5aY7QXnSEH5SO3CN9or/8HVZX255AGVC1t/y2N3m9n MBIvAPXDZK9X/P4GvmiJQfhpVATB0Xvi2r+W2nwYDRnEdrKYHZzQvpCOJlslWFF4Uv cI1rfgdwWE9d6iV5Ehg6fItiVvQZraLpWpGPlxzItBhg+GPNPQ8jbTCB7TNH5U2ecv eQRGLiCLPUb5Q== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add details for power-domains to the Tegra xHCI bindings so that generic power-domains can be used for inconjunction with the xHCI driver. Signed-off-by: Jon Hunter --- Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt index 3eee9e505400..4156c3e181c5 100644 --- a/Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt @@ -59,6 +59,14 @@ For Tegra210: - avdd-pll-uerefe-supply: PLLE reference PLL power supply. Must supply 1.05 V. - dvdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V. - hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 1.8 V. +- power-domains: A list of PM domain specifiers that reference each power-domain + used by the xHCI controller. This list must comprise of a specifier for the + XUSBA and XUSBC power-domains. See ../power/power_domain.txt and + ../arm/tegra/nvidia,tegra20-pmc.txt for details. +- power-domain-names: A list of names that represent each of the specifiers in + the 'power-domains' property. Must include 'xusb_ss' and 'xusb_host' which + represent the power-domains XUSBA and XUSBC, respectively. See + ../power/power_domain.txt for details. Optional properties: -------------------- From patchwork Wed Sep 26 12:27:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 975057 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="PLNsrCU0"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42Kxzv6TrRz9s1c for ; Wed, 26 Sep 2018 22:28:10 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727555AbeIZSki (ORCPT ); Wed, 26 Sep 2018 14:40:38 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:8717 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726880AbeIZSkh (ORCPT ); Wed, 26 Sep 2018 14:40:37 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 26 Sep 2018 05:27:57 -0700 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 26 Sep 2018 05:27:51 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 26 Sep 2018 05:27:51 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 26 Sep 2018 12:27:50 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Wed, 26 Sep 2018 12:27:50 +0000 Received: from moonraker.nvidia.com (Not Verified[10.21.132.143]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 26 Sep 2018 05:27:50 -0700 From: Jon Hunter To: Rob Herring , Mark Rutland , "Rafael J . Wysocki" , Kevin Hilman , Ulf Hansson , Greg Kroah-Hartman , Mathias Nyman , Thierry Reding CC: , , , Jon Hunter Subject: [PATCH 3/5] usb: xhci: tegra: Add genpd support Date: Wed, 26 Sep 2018 13:27:36 +0100 Message-ID: <1537964858-30332-4-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1537964858-30332-1-git-send-email-jonathanh@nvidia.com> References: <1537964858-30332-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1537964877; bh=giZuUhM0b93UuF5gB6Xr0pPtEo+PpYnYftQnrHzMNDo=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=PLNsrCU0XpIE0TmUd/oGEYm1DnHEYbTvV92NuzTP97ylP8HuS9VKwtjkVWRaO4VXK w1HUG+YkxHfiDl4aeFATrHwycxjLNQNrA7+/iB4QsA8Z6yUEoBNqxsDjbOtq+p0kPa tICwPHvizq70D7kLtBAvacivZS3Mtj/n2Q7en4Iu/09AoX6JmILh06/H6Dd5eFdZnn VybGBNSk1DD4UuAGTQb9yNcYSYqwk0UhwANg+AKyrodpYPCPAWZCxlGX5SRMVJG34l 5thqsZmbZymj0kaGXPPSnmsSNF15RswopyvQZ6GdF5s+Pap13ocT2quXsQcq/Zcpc0 PnBLNo2v6lOmw== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The generic power-domain framework has been updated to allow devices that require more than one power-domain to create a new device for each power-domain required and then link these new power-domain devices to the consumer device. Update the Tegra xHCI driver to use the new APIs provided by the generic power-domain framework so we can use the generic power-domain framework for managing the xHCI controllers power-domains. Please note that to maintain backward compatibility with older device-tree blobs these new generic power-domain APIs are only used if the 'power-domains' property is present and otherwise we fall back to using the legacy Tegra APIs for managing the power-domains. Signed-off-by: Jon Hunter --- drivers/usb/host/xhci-tegra.c | 88 +++++++++++++++++++++++++++++++++++++------ 1 file changed, 77 insertions(+), 11 deletions(-) diff --git a/drivers/usb/host/xhci-tegra.c b/drivers/usb/host/xhci-tegra.c index 4b463e5202a4..335d9d7e515e 100644 --- a/drivers/usb/host/xhci-tegra.c +++ b/drivers/usb/host/xhci-tegra.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -194,6 +195,11 @@ struct tegra_xusb { struct reset_control *host_rst; struct reset_control *ss_rst; + struct device *genpd_dev_host; + struct device *genpd_dev_ss; + struct device_link *genpd_dl_host; + struct device_link *genpd_dl_ss; + struct phy **phys; unsigned int num_phys; @@ -928,6 +934,60 @@ static int tegra_xusb_load_firmware(struct tegra_xusb *tegra) return 0; } +static void tegra_xusb_powerdomain_remove(struct device *dev, + struct tegra_xusb *tegra) +{ + if (tegra->genpd_dl_ss) + device_link_del(tegra->genpd_dl_ss); + if (tegra->genpd_dl_host) + device_link_del(tegra->genpd_dl_host); + if (tegra->genpd_dev_ss) + dev_pm_domain_detach(tegra->genpd_dev_ss, true); + if (tegra->genpd_dev_host) + dev_pm_domain_detach(tegra->genpd_dev_host, true); +} + +static int tegra_xusb_powerdomain_init(struct device *dev, + struct tegra_xusb *tegra) +{ + int err; + + tegra->genpd_dev_host = genpd_dev_pm_attach_by_name(dev, "xusb_host"); + if (IS_ERR(tegra->genpd_dev_host)) { + err = PTR_ERR(tegra->genpd_dev_host); + dev_err(dev, "failed to get host pm-domain: %d\n", err); + return err; + } + + tegra->genpd_dev_ss = genpd_dev_pm_attach_by_name(dev, "xusb_ss"); + if (IS_ERR(tegra->genpd_dev_ss)) { + tegra_xusb_powerdomain_remove(dev, tegra); + err = PTR_ERR(tegra->genpd_dev_ss); + dev_err(dev, "failed to get superspeed pm-domain: %d\n", err); + return err; + } + + tegra->genpd_dl_host = device_link_add(dev, tegra->genpd_dev_host, + DL_FLAG_PM_RUNTIME | + DL_FLAG_STATELESS); + if (!tegra->genpd_dl_host) { + tegra_xusb_powerdomain_remove(dev, tegra); + dev_err(dev, "adding host device link failed!\n"); + return -ENODEV; + } + + tegra->genpd_dl_ss = device_link_add(dev, tegra->genpd_dev_ss, + DL_FLAG_PM_RUNTIME | + DL_FLAG_STATELESS); + if (!tegra->genpd_dl_ss) { + tegra_xusb_powerdomain_remove(dev, tegra); + dev_err(dev, "adding superspeed device link failed!\n"); + return -ENODEV; + } + + return 0; +} + static int tegra_xusb_probe(struct platform_device *pdev) { struct tegra_xusb_mbox_msg msg; @@ -1038,7 +1098,11 @@ static int tegra_xusb_probe(struct platform_device *pdev) goto put_padctl; } - if (!pdev->dev.pm_domain) { + if (of_property_read_bool(pdev->dev.of_node, "power-domains")) { + err = tegra_xusb_powerdomain_init(&pdev->dev, tegra); + if (err) + goto put_padctl; + } else { tegra->host_rst = devm_reset_control_get(&pdev->dev, "xusb_host"); if (IS_ERR(tegra->host_rst)) { @@ -1069,9 +1133,10 @@ static int tegra_xusb_probe(struct platform_device *pdev) tegra->host_clk, tegra->host_rst); if (err) { + tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA); dev_err(&pdev->dev, "failed to enable XUSBC domain: %d\n", err); - goto disable_xusba; + goto put_padctl; } } @@ -1079,7 +1144,7 @@ static int tegra_xusb_probe(struct platform_device *pdev) sizeof(*tegra->supplies), GFP_KERNEL); if (!tegra->supplies) { err = -ENOMEM; - goto disable_xusbc; + goto put_powerdomains; } for (i = 0; i < tegra->soc->num_supplies; i++) @@ -1089,7 +1154,7 @@ static int tegra_xusb_probe(struct platform_device *pdev) tegra->supplies); if (err) { dev_err(&pdev->dev, "failed to get regulators: %d\n", err); - goto disable_xusbc; + goto put_powerdomains; } for (i = 0; i < tegra->soc->num_types; i++) @@ -1099,7 +1164,7 @@ static int tegra_xusb_probe(struct platform_device *pdev) sizeof(*tegra->phys), GFP_KERNEL); if (!tegra->phys) { err = -ENOMEM; - goto disable_xusbc; + goto put_powerdomains; } for (i = 0, k = 0; i < tegra->soc->num_types; i++) { @@ -1115,7 +1180,7 @@ static int tegra_xusb_probe(struct platform_device *pdev) "failed to get PHY %s: %ld\n", prop, PTR_ERR(phy)); err = PTR_ERR(phy); - goto disable_xusbc; + goto put_powerdomains; } tegra->phys[k++] = phy; @@ -1126,7 +1191,7 @@ static int tegra_xusb_probe(struct platform_device *pdev) dev_name(&pdev->dev)); if (!tegra->hcd) { err = -ENOMEM; - goto disable_xusbc; + goto put_powerdomains; } /* @@ -1222,12 +1287,13 @@ static int tegra_xusb_probe(struct platform_device *pdev) disable_rpm: pm_runtime_disable(&pdev->dev); usb_put_hcd(tegra->hcd); -disable_xusbc: - if (!pdev->dev.pm_domain) +put_powerdomains: + if (of_property_read_bool(pdev->dev.of_node, "power-domains")) { + tegra_xusb_powerdomain_remove(&pdev->dev, tegra); + } else { tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC); -disable_xusba: - if (!pdev->dev.pm_domain) tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA); + } put_padctl: tegra_xusb_padctl_put(tegra->padctl); return err; From patchwork Wed Sep 26 12:27:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 975056 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="BxDZW0S+"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42Kxzq2LFnz9s55 for ; Wed, 26 Sep 2018 22:28:07 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727299AbeIZSkj (ORCPT ); Wed, 26 Sep 2018 14:40:39 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:12113 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726880AbeIZSkj (ORCPT ); Wed, 26 Sep 2018 14:40:39 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 26 Sep 2018 05:27:18 -0700 Received: from HQMAIL105.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 26 Sep 2018 05:27:53 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 26 Sep 2018 05:27:53 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 26 Sep 2018 12:27:53 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Wed, 26 Sep 2018 12:27:53 +0000 Received: from moonraker.nvidia.com (Not Verified[10.21.132.143]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 26 Sep 2018 05:27:53 -0700 From: Jon Hunter To: Rob Herring , Mark Rutland , "Rafael J . Wysocki" , Kevin Hilman , Ulf Hansson , Greg Kroah-Hartman , Mathias Nyman , Thierry Reding CC: , , , Jon Hunter Subject: [PATCH 4/5] soc/tegra: pmc: Don't power-up XUSB power-domains Date: Wed, 26 Sep 2018 13:27:37 +0100 Message-ID: <1537964858-30332-5-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1537964858-30332-1-git-send-email-jonathanh@nvidia.com> References: <1537964858-30332-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1537964838; bh=qy5cYZy2tUNDZUCDXLLRF30Px9H2650Lc8nDv7ApZRE=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=BxDZW0S+F3UjFLXDZ/fnzBt78BEHLaHALlIifLn4heeI0p/9LqmTry1tMZ7j7XZHf eZmthZUICt7ALTKZX2kFRQPoSemUXwF3SljcrjxbkBYSvVXnapfXtMrlIOOI6ttyfn HQJ0+rvYBtlLxzA++Lj8E8SPxyTc906JURshJR9LPvascX4K0vsDBYzO5n2kDdNR+7 X1VHWzCyhNNa4/l2oTO2REJ7E6fG/XY71rIwhhRh/Fs3Jxs2/zL89MOcxCFJjp1GEU BdOE4JBGB3xZ1A+Omcf+W5L0YrSV7a2RPTCpmb7t2VVQjK/fewrzCKUSIDCx6aKCxT a6u6tlEOPfQEg== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Now that the Tegra xHCI driver manages the XUSB power-domains itself, remove the code to power-up the power-domains used by the xHCI device from the PMC driver on boot. Signed-off-by: Jon Hunter --- drivers/soc/tegra/pmc.c | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index ab719fa90150..a68b4476b4ee 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -847,22 +847,6 @@ static void tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) goto remove_resets; } - /* - * FIXME: If XHCI is enabled for Tegra, then power-up the XUSB - * host and super-speed partitions. Once the XHCI driver - * manages the partitions itself this code can be removed. Note - * that we don't register these partitions with the genpd core - * to avoid it from powering down the partitions as they appear - * to be unused. - */ - if (IS_ENABLED(CONFIG_USB_XHCI_TEGRA) && - (id == TEGRA_POWERGATE_XUSBA || id == TEGRA_POWERGATE_XUSBC)) { - if (off) - WARN_ON(tegra_powergate_power_up(pg, true)); - - goto remove_resets; - } - err = pm_genpd_init(&pg->genpd, NULL, off); if (err < 0) { pr_err("failed to initialise PM domain %s: %d\n", np->name, From patchwork Wed Sep 26 12:27:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 975055 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="B1iMeDVV"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42Kxzm3rTTz9s1c for ; Wed, 26 Sep 2018 22:28:04 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727549AbeIZSkm (ORCPT ); Wed, 26 Sep 2018 14:40:42 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:8729 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726880AbeIZSkl (ORCPT ); Wed, 26 Sep 2018 14:40:41 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 26 Sep 2018 05:28:02 -0700 Received: from HQMAIL106.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 26 Sep 2018 05:27:56 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 26 Sep 2018 05:27:56 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 26 Sep 2018 12:27:55 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Wed, 26 Sep 2018 12:27:55 +0000 Received: from moonraker.nvidia.com (Not Verified[10.21.132.143]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 26 Sep 2018 05:27:55 -0700 From: Jon Hunter To: Rob Herring , Mark Rutland , "Rafael J . Wysocki" , Kevin Hilman , Ulf Hansson , Greg Kroah-Hartman , Mathias Nyman , Thierry Reding CC: , , , Jon Hunter Subject: [PATCH 5/5] arm64: dts: tegra210: Add power-domains for xHCI Date: Wed, 26 Sep 2018 13:27:38 +0100 Message-ID: <1537964858-30332-6-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1537964858-30332-1-git-send-email-jonathanh@nvidia.com> References: <1537964858-30332-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1537964882; bh=A5+LaSIS2MtAbQ6Lm1NQ7m3punvjkIxzOXDsA/lzCpo=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=B1iMeDVVdOnmP13Sf3GIS2mFOtDfLOYBUD3rr+TwU/zyL3JGXYSOMvzCupVApcW05 ucoF9ZmD2NRan+4B3uV1DiwGJ5Ptv50+82di9vZXnq/O8zfARM/RwvXX1OklWVVp26 VfDt5sdEqfpvMRa3Vi1U6puPLfiU2yc699EjI7/NwVNMG2FR4awqneT0k/qtv4RT3W nCoVv48ojxrFSN/oNfA2BF6zHUWAdR6/I1eP8c2Q1YhyjGxuYnStZQhe8Ktmz7dA4D jOOfsdRAimxPSFvC3XocoD/zZHQ6Lh/4c598KH2iCXXCHDfRnv9QBdSr/75MMqat4M yxi/AQn8CLwcw== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Populate the power-domain properties for the xHCI device for Tegra210. Signed-off-by: Jon Hunter --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 8fe47d6445a5..2205d66b0443 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -879,6 +879,8 @@ resets = <&tegra_car 89>, <&tegra_car 156>, <&tegra_car 143>; reset-names = "xusb_host", "xusb_ss", "xusb_src"; + power-domains = <&pd_xusbhost>, <&pd_xusbss>; + power-domain-names = "xusb_host", "xusb_ss"; nvidia,xusb-padctl = <&padctl>;