From patchwork Wed Sep 19 21:02:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= X-Patchwork-Id: 971937 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="D/E5P2nu"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42FslC5PcPz9sBs for ; Thu, 20 Sep 2018 07:03:03 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728181AbeITCmo (ORCPT ); Wed, 19 Sep 2018 22:42:44 -0400 Received: from mail-lj1-f194.google.com ([209.85.208.194]:35126 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728124AbeITCmo (ORCPT ); Wed, 19 Sep 2018 22:42:44 -0400 Received: by mail-lj1-f194.google.com with SMTP id p10-v6so6376970ljg.2; Wed, 19 Sep 2018 14:03:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=SjLfIVY+ZSAHdXuluR8I+iIHKz6Dk5sattt8USRnDkw=; b=D/E5P2nuP5J7hnYo6Ou6oz+p1OEJB885Bn06MLO8fdAX3i3AxYGFG79XbdArPNec8u wXg1D+BE1Qvh9nPEUK49EgCH9Eb0rd8INyTI/2nLtuLXW1nu//3x/OQOmEME0PVpsH6W ABNm8pKmNQf3mGFH4wT1dM/038SYvZdGjv2hMT58Or/3tBS1wQgq9wulNCBgsveh81RH Ryc2hitbMey/L1J/aMUW7tBnNFwvPoOdH/UhCUc+z/RuQb4AtHoohUv0fzF3AyN7UycN kPwp5Tk4C+ZCCVbp3pv7fHV4lOdHoZnewR5c1hPYRc935CcfsSTYEX38AlZIcz7dtmuT TNxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=SjLfIVY+ZSAHdXuluR8I+iIHKz6Dk5sattt8USRnDkw=; b=Fw7k61WsL841gVKyYxacQpslghH0zrqdjvPPjRJlb9Sq4KVDIGfZvj5CQOtPnq3ByH hQPU2WeaJxvQhARbymQJmAqqDYmgew7OhgI78NTEUsCvWOFY943iooDV4RHAXkWU7nXc bIOwWIRsXZVpV43UnVNAFSCRXrhh7Qu0Ion3JfP0nrWCh/9Tz4O6C9CcdWi9SZuoJCTH 0XGMAMBBwYQ7N/iWcme+01Tx6oD3uaJN9Q4BkapEVjYfMN5Hd1yqZBjGqsQ2jmhnLJvI LPVj/ubC/aro6sSbCi8Qx6PWpcuEjXXL7f8DelJUaKafiMPet1O+z0X1uYyEm/7+Unlr I9mA== X-Gm-Message-State: APzg51Dv6L51sQ5hxU+vZ8yFAIRkdi7MW5QOZi6i7HWKYEpRjjLiztHX KhSD8imCDiBCqQDYlC2E2mlnkrUB X-Google-Smtp-Source: ANB0Vdbjzi7/8FcUGxsJWqezWqmrSWLCyhYDLGv6fhKHMT2eloAPptAA7WilHVP4yw0QGKKsiI5KCA== X-Received: by 2002:a2e:9ec9:: with SMTP id h9-v6mr17069561ljk.133.1537390979771; Wed, 19 Sep 2018 14:02:59 -0700 (PDT) Received: from linux-veee.lan (ip-194-187-74-233.konfederacka.maverick.com.pl. [194.187.74.233]) by smtp.gmail.com with ESMTPSA id a27-v6sm1263743lfi.59.2018.09.19.14.02.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 19 Sep 2018 14:02:58 -0700 (PDT) From: =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= To: Linus Walleij , linux-gpio@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org Cc: Mark Rutland , Ray Jui , Scott Branden , Jon Mason , bcm-kernel-feedback-list@broadcom.com, linux-arm-kernel@lists.infradead.org, =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= Subject: [PATCH 1/2] dt-bindings: pinctrl: document Broadcom Northstar pin mux controller Date: Wed, 19 Sep 2018 23:02:18 +0200 Message-Id: <20180919210219.21921-1-zajec5@gmail.com> X-Mailer: git-send-email 2.13.7 MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Rafał Miłecki Northstar has mux controller just like Northstar Plus and Northstar2. It's a bit different though (different registers & pins) so it requires its own binding. It's needed to allow other block bindings specify required mux setup. Signed-off-by: Rafał Miłecki Reviewed-by: Florian Fainelli --- .../devicetree/bindings/pinctrl/brcm,ns-pinmux.txt | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,ns-pinmux.txt diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,ns-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/brcm,ns-pinmux.txt new file mode 100644 index 000000000000..0e913721ae9e --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,ns-pinmux.txt @@ -0,0 +1,29 @@ +Broadcom Northstar pins mux controller + +Some of Northstar SoCs's pins can be used for various purposes thanks to the mux +controller. This binding allows describing mux controller and listing available +functions. They can be referenced later by other bindings to let system +configure controller correctly. + +Required properties: +- compatible: brcm,ns-pinmux +- reg: iomem address range of CRU (Central Resource Unit) pin registers +- reg-names: "cru_pins_control" - the only needed & supported reg right now + +List of supported functions and their groups: +- "spi": "spi_grp" + +For documentation of subnodes see: +Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt + +Example: + pinctrl@1800c1c0 { + compatible = "brcm,ns-pinmux"; + reg = <0x1800c1c0 0x24>; + reg-names = "cru_pins_control"; + + spi { + function = "spi"; + groups = "spi_grp"; + }; + }; From patchwork Wed Sep 19 21:02:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= X-Patchwork-Id: 971939 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="kPcGldbC"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42FslG3fj3z9sBs for ; Thu, 20 Sep 2018 07:03:06 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731738AbeITCms (ORCPT ); Wed, 19 Sep 2018 22:42:48 -0400 Received: from mail-lf1-f65.google.com ([209.85.167.65]:34926 "EHLO mail-lf1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728124AbeITCms (ORCPT ); Wed, 19 Sep 2018 22:42:48 -0400 Received: by mail-lf1-f65.google.com with SMTP id x20-v6so6401267lfg.2; Wed, 19 Sep 2018 14:03:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0M0nr6ChDfGwKYHG45b4AilQjj63vyytvhfSldZmRUo=; b=kPcGldbCTYIfnUVWbqyEz1fxaM9rVQ4bzodmuZaS0ME6lO2DuK8Gysem8PwAp4oI3a cM0jYg/cQDXcSsnCFg/RTm30cjW6wTSeS4w7DImSk6Uay72s4eF+P6hNdF8Wvyr+HIzH cU9dkbxw89sb9uWabmVqgOQtnMfmY6w3Ax6Msy+VzPv2ZE1X6RQNjJ4NPC3LF0EJNHpW FDjGNlW4u2mLRuIk42mnjAs3zK6KPLR3DlahcVdI0UQ5MDSnE7Q20KdoST0JV0O3TbFX zLsylQjbV1zxdd7kd4jn8ol1n6Y8UR/p4nPkzONTDaa6kBtjc6Bi1bmxOxe/thbayr/Z i3MQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0M0nr6ChDfGwKYHG45b4AilQjj63vyytvhfSldZmRUo=; b=I1ymUCs0PWhE1eSET2YFYqn5r4o0bXsS3rTdnQ2PcHkU8+3LoH7TCVXsASH8gTuhCY 5pAoxEoJ/vp5HTwJ49Kh1yPVPQ1OixBbV9XBeY8X+RwawGJeBUe2iNjCZL1LufpmqC3w 8xKjBl3eXDogGEq7Ls/6PBK+hniqPJ/arKmIBvtdaTV6vyHogReFt5lRV+k5tiVm9ERv lz/aR8I+Ssuu2ye9HHlAwQ+4Q2q0+/elPb45V+bo5l1QLZsxIsbqXA9CY1O6BpfzF0rf FKO+/sgKQPXs6d9riiNbMICgCYrWYmPUtfk0mzQOFqCLnnCFTLF9idgwgBtunLBxD7Cc Ta8Q== X-Gm-Message-State: APzg51C3kzuNsOgW0j6IRqeJQjWEQM8TNxF43aheh2W9avn887wJvndB UHvBcxT5AhoEGfILfm2L+Vw= X-Google-Smtp-Source: ANB0VdZIM1t84uJCACQMKB65lXyVkQcD1zJJ6HYQFc1nW2wRlHieJ2PS6DBIqNgZ/hkp9Qbwco7jzw== X-Received: by 2002:a19:5e5d:: with SMTP id z29-v6mr641293lfi.110.1537390983123; Wed, 19 Sep 2018 14:03:03 -0700 (PDT) Received: from linux-veee.lan (ip-194-187-74-233.konfederacka.maverick.com.pl. [194.187.74.233]) by smtp.gmail.com with ESMTPSA id a27-v6sm1263743lfi.59.2018.09.19.14.03.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 19 Sep 2018 14:03:02 -0700 (PDT) From: =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= To: Linus Walleij , linux-gpio@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org Cc: Mark Rutland , Ray Jui , Scott Branden , Jon Mason , bcm-kernel-feedback-list@broadcom.com, linux-arm-kernel@lists.infradead.org, =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= Subject: [PATCH 2/2] pinctrl: bcm: add Northstar driver Date: Wed, 19 Sep 2018 23:02:19 +0200 Message-Id: <20180919210219.21921-2-zajec5@gmail.com> X-Mailer: git-send-email 2.13.7 In-Reply-To: <20180919210219.21921-1-zajec5@gmail.com> References: <20180919210219.21921-1-zajec5@gmail.com> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Rafał Miłecki This driver provides support for Northstar mux controller. It differs from Northstar Plus one so a new binding and driver were needed. Right now it includes support for SPI pins only which is caused by a lack of access to Broadcom's datasheet. SPI pins info was extracted from the Broadcom's SDK. Once more pins are discovered they can be added to the driver without breaking any existing setups. Signed-off-by: Rafał Miłecki --- drivers/pinctrl/bcm/Kconfig | 13 +++ drivers/pinctrl/bcm/Makefile | 1 + drivers/pinctrl/bcm/pinctrl-ns.c | 246 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 260 insertions(+) create mode 100644 drivers/pinctrl/bcm/pinctrl-ns.c diff --git a/drivers/pinctrl/bcm/Kconfig b/drivers/pinctrl/bcm/Kconfig index 0f38d51f47c6..c8575399d6f7 100644 --- a/drivers/pinctrl/bcm/Kconfig +++ b/drivers/pinctrl/bcm/Kconfig @@ -73,6 +73,19 @@ config PINCTRL_CYGNUS_MUX configuration, with the exception that certain individual pins can be overridden to GPIO function +config PINCTRL_NS + bool "Broadcom Northstar pins driver" + depends on OF && (ARCH_BCM_5301X || COMPILE_TEST) + select PINMUX + select GENERIC_PINCONF + default ARCH_BCM_5301X + help + Say yes here to enable the Broadcom NS SoC pins driver. + + The Broadcom Northstar pins driver supports muxing multi-purpose pins + that can be used for various functions (e.g. SPI, I2C, UART) as well + as GPIOs. + config PINCTRL_NSP_GPIO bool "Broadcom NSP GPIO (with PINCONF) driver" depends on OF_GPIO && (ARCH_BCM_NSP || COMPILE_TEST) diff --git a/drivers/pinctrl/bcm/Makefile b/drivers/pinctrl/bcm/Makefile index 80ceb9dae944..79d5e49fdd9a 100644 --- a/drivers/pinctrl/bcm/Makefile +++ b/drivers/pinctrl/bcm/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o obj-$(CONFIG_PINCTRL_IPROC_GPIO) += pinctrl-iproc-gpio.o obj-$(CONFIG_PINCTRL_CYGNUS_MUX) += pinctrl-cygnus-mux.o +obj-$(CONFIG_PINCTRL_NS) += pinctrl-ns.o obj-$(CONFIG_PINCTRL_NSP_GPIO) += pinctrl-nsp-gpio.o obj-$(CONFIG_PINCTRL_NS2_MUX) += pinctrl-ns2-mux.o obj-$(CONFIG_PINCTRL_NSP_MUX) += pinctrl-nsp-mux.o diff --git a/drivers/pinctrl/bcm/pinctrl-ns.c b/drivers/pinctrl/bcm/pinctrl-ns.c new file mode 100644 index 000000000000..bf7703c4a2e3 --- /dev/null +++ b/drivers/pinctrl/bcm/pinctrl-ns.c @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Rafał Miłecki + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct ns_pinctrl { + struct pinctrl_dev *pctldev; + struct device *dev; + void __iomem *base; +}; + +/* + * Pins + */ + +struct ns_pin_data { + unsigned int reg; + unsigned int bit; +}; + +static const struct ns_pin_data ns_pins_data[] = { + [0] = { 0, 0 }, + [1] = { 0, 1 }, + [2] = { 0, 2 }, + [3] = { 0, 3 }, +}; + +static const struct pinctrl_pin_desc ns_pinctrl_pins[] = { + { 0, "spi_clk" }, + { 1, "spi_ss" }, + { 2, "spi_mosi" }, + { 3, "spi_miso" }, +}; + +/* + * Groups + */ + +struct ns_pinctrl_group { + const char *name; + const unsigned int *pins; + const unsigned int num_pins; +}; + +static const unsigned int spi_pins[] = { 0, 1, 2, 3 }; + +#define NS_GROUP(_name, _pins) \ +{ \ + .name = _name, \ + .pins = _pins, \ + .num_pins = ARRAY_SIZE(_pins), \ +} + +static const struct ns_pinctrl_group ns_pinctrl_groups[] = { + NS_GROUP("spi_grp", spi_pins), +}; + +/* + * Functions + */ + +struct ns_pinctrl_function { + const char *name; + const char * const *groups; + const unsigned int num_groups; +}; + +static const char * const spi_groups[] = { "spi_grp" }; + +#define NS_FUNCTION(_name, _groups) \ +{ \ + .name = _name, \ + .groups = _groups, \ + .num_groups = ARRAY_SIZE(_groups), \ +} + +static const struct ns_pinctrl_function ns_pinctrl_functions[] = { + NS_FUNCTION("spi", spi_groups), +}; + +/* + * Groups code + */ + +static int ns_pinctrl_get_groups_count(struct pinctrl_dev *pctrl_dev) +{ + return ARRAY_SIZE(ns_pinctrl_groups); +} + +static const char *ns_pinctrl_get_group_name(struct pinctrl_dev *pctrl_dev, + unsigned int selector) +{ + return ns_pinctrl_groups[selector].name; +} + +static int ns_pinctrl_get_group_pins(struct pinctrl_dev *pctrl_dev, + unsigned int selector, + const unsigned int **pins, + unsigned int *num_pins) +{ + *pins = ns_pinctrl_groups[selector].pins; + *num_pins = ns_pinctrl_groups[selector].num_pins; + + return 0; +} + +static const struct pinctrl_ops ns_pinctrl_ops = { + .get_groups_count = ns_pinctrl_get_groups_count, + .get_group_name = ns_pinctrl_get_group_name, + .get_group_pins = ns_pinctrl_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_group, + .dt_free_map = pinconf_generic_dt_free_map, +}; + +/* + * Functions code + */ + +static int ns_pinctrl_get_functions_count(struct pinctrl_dev *pctrl_dev) +{ + return ARRAY_SIZE(ns_pinctrl_functions); +} + +static const char *ns_pinctrl_get_function_name(struct pinctrl_dev *pctrl_dev, + unsigned int selector) +{ + return ns_pinctrl_functions[selector].name; +} + +static int ns_pinctrl_get_function_groups(struct pinctrl_dev *pctrl_dev, + unsigned int selector, + const char * const **groups, + unsigned * const num_groups) +{ + *groups = ns_pinctrl_functions[selector].groups; + *num_groups = ns_pinctrl_functions[selector].num_groups; + + return 0; +} + +static int ns_pinctrl_set_mux(struct pinctrl_dev *pctrl_dev, + unsigned int func_select, + unsigned int grp_select) +{ + struct ns_pinctrl *ns_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); + u32 unset[9] = { }; + int i; + + for (i = 0; i < ns_pinctrl_groups[grp_select].num_pins; i++) { + int pin_number = ns_pinctrl_groups[grp_select].pins[i]; + const struct ns_pin_data *data = &ns_pins_data[pin_number]; + + unset[data->reg] |= BIT(data->bit); + } + + for (i = 0; i < ARRAY_SIZE(unset); i++) { + u32 tmp; + + if (!unset[i]) + continue; + + tmp = readl(ns_pinctrl->base + i); + tmp &= ~unset[i]; + writel(tmp, ns_pinctrl->base + i); + } + + return 0; +} + +static const struct pinmux_ops ns_pinctrl_pmxops = { + .get_functions_count = ns_pinctrl_get_functions_count, + .get_function_name = ns_pinctrl_get_function_name, + .get_function_groups = ns_pinctrl_get_function_groups, + .set_mux = ns_pinctrl_set_mux, +}; + +/* + * Controller code + */ + +static struct pinctrl_desc ns_pinctrl_desc = { + .name = "pinctrl-ns", + .pins = ns_pinctrl_pins, + .npins = ARRAY_SIZE(ns_pinctrl_pins), + .pctlops = &ns_pinctrl_ops, + .pmxops = &ns_pinctrl_pmxops, +}; + +static int ns_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct ns_pinctrl *ns_pinctrl; + struct resource *res; + + ns_pinctrl = devm_kzalloc(dev, sizeof(*ns_pinctrl), GFP_KERNEL); + if (!ns_pinctrl) + return -ENOMEM; + ns_pinctrl->dev = dev; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "cru_pins_control"); + ns_pinctrl->base = devm_ioremap_resource(dev, res); + if (IS_ERR(ns_pinctrl->base)) { + dev_err(dev, "Failed to map pinctrl regs\n"); + return PTR_ERR(ns_pinctrl->base); + } + + platform_set_drvdata(pdev, ns_pinctrl); + + ns_pinctrl->pctldev = devm_pinctrl_register(dev, &ns_pinctrl_desc, + ns_pinctrl); + if (IS_ERR(ns_pinctrl->pctldev)) { + dev_err(dev, "Failed to register pinctrl\n"); + return PTR_ERR(ns_pinctrl->pctldev); + } + + return 0; +} + +static const struct of_device_id ns_pinctrl_of_match_table[] = { + { .compatible = "brcm,ns-pinmux" }, + { } +}; + +static struct platform_driver ns_pinctrl_driver = { + .probe = ns_pinctrl_probe, + .driver = { + .name = "ns-pinmux", + .of_match_table = ns_pinctrl_of_match_table, + }, +}; + +module_platform_driver(ns_pinctrl_driver); + +MODULE_AUTHOR("Rafał Miłecki"); +MODULE_LICENSE("GPL v2");