From patchwork Sat Sep 15 14:39:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaibhav Jain X-Patchwork-Id: 970234 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42CFR76Jtdz9sBJ for ; Sun, 16 Sep 2018 00:40:03 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 42CFR74V2nzF1fF for ; Sun, 16 Sep 2018 00:40:03 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=vaibhav@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 42CFR20k0xzF1WK for ; Sun, 16 Sep 2018 00:39:57 +1000 (AEST) Received: from pps.filterd (m0098419.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w8FEdSaH103498 for ; Sat, 15 Sep 2018 10:39:55 -0400 Received: from e06smtp03.uk.ibm.com (e06smtp03.uk.ibm.com [195.75.94.99]) by mx0b-001b2d01.pphosted.com with ESMTP id 2mgu17entu-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Sat, 15 Sep 2018 10:39:55 -0400 Received: from localhost by e06smtp03.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Sat, 15 Sep 2018 15:39:51 +0100 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w8FEdn7D65601648 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Sat, 15 Sep 2018 14:39:49 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9DE5552050; Sat, 15 Sep 2018 17:39:36 +0100 (BST) Received: from vajain21.in.ibm.com.com (unknown [9.199.55.137]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 743485204E; Sat, 15 Sep 2018 17:39:33 +0100 (BST) From: Vaibhav Jain To: Oliver , Michael Neuling , Stewart Smith , Frederic Barrat , Andrew Donnellan , Christophe Lombard , Philippe Bergheaud Date: Sat, 15 Sep 2018 20:09:20 +0530 X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180915143926.12870-1-vaibhav@linux.ibm.com> References: <20180915143926.12870-1-vaibhav@linux.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 18091514-0012-0000-0000-000002A9346B X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18091514-0013-0000-0000-000020DD828B Message-Id: <20180915143926.12870-2-vaibhav@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-09-15_06:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1807170000 definitions=main-1809150161 Subject: [Skiboot] [PATCH 1/7] phb4/capp: Update and re-factor phb4_set_capi_mode() X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Presently phb4_set_capi_mode() performs certain CAPP checks like, checking of CAPP ucode loaded or checks if CAPP is still in recovery, even when the requested mode is to switch to PCI mode. Hence this patch updates and re-factors phb4_set_capi_mode() to make sure CAPP related checks are only performed when request to enable CAPP is made by mode==OPAL_PHB_CAPI_MODE_CAPI/DMA_TVT1. We also update other possible modes requests to return a more appropriate status code based on if CAPP is activated or not. Signed-off-by: Vaibhav Jain --- hw/phb4.c | 93 +++++++++++++++++++++++++++++++++++-------------------- 1 file changed, 59 insertions(+), 34 deletions(-) diff --git a/hw/phb4.c b/hw/phb4.c index 94e741e0..4284c467 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -4322,54 +4322,79 @@ static int64_t phb4_set_capi_mode(struct phb *phb, uint64_t mode, { struct phb4 *p = phb_to_phb4(phb); struct proc_chip *chip = get_chip(p->chip_id); + uint32_t offset = PHB4_CAPP_REG_OFFSET(p); uint64_t reg, ret; - uint32_t offset; - - - if (!capp_ucode_loaded(chip, p->index)) { - PHBERR(p, "CAPP: ucode not loaded\n"); - return OPAL_RESOURCE; - } + bool attached; + /* No one else fiddle with capp while we modify its state */ lock(&capi_lock); - chip->capp_phb4_attached_mask |= 1 << p->index; - unlock(&capi_lock); - offset = PHB4_CAPP_REG_OFFSET(p); - xscom_read(p->chip_id, CAPP_ERR_STATUS_CTRL + offset, ®); - if ((reg & PPC_BIT(5))) { - PHBERR(p, "CAPP: recovery failed (%016llx)\n", reg); - return OPAL_HARDWARE; - } else if ((reg & PPC_BIT(0)) && (!(reg & PPC_BIT(1)))) { - PHBDBG(p, "CAPP: recovery in progress\n"); - return OPAL_BUSY; - } + /* Check if CAPP are already attached to PHB */ + attached = chip->capp_phb4_attached_mask & (1 << p->index); switch (mode) { - case OPAL_PHB_CAPI_MODE_CAPI: - ret = enable_capi_mode(p, pe_number, - CAPP_MAX_STQ_ENGINES | - CAPP_MIN_DMA_READ_ENGINES); - disable_fast_reboot("CAPP being enabled"); + + case OPAL_PHB_CAPI_MODE_DMA: /* Enabled by default on p9 */ + case OPAL_PHB_CAPI_MODE_SNOOP_ON: + /* nothing to do on P9 if CAPP is alreay enabled */ + ret = attached ? OPAL_SUCCESS : OPAL_UNSUPPORTED; break; + + case OPAL_PHB_CAPI_MODE_SNOOP_OFF: + case OPAL_PHB_CAPI_MODE_PCIE: /* Not supported at the moment */ + ret = !attached ? OPAL_SUCCESS : OPAL_UNSUPPORTED; + break; + + case OPAL_PHB_CAPI_MODE_CAPI: /* Fall Through */ case OPAL_PHB_CAPI_MODE_DMA_TVT1: + /* Check if ucode is available */ + if (!capp_ucode_loaded(chip, p->index)) { + PHBERR(p, "CAPP: ucode not loaded\n"); + ret = OPAL_RESOURCE; + break; + } + + xscom_read(p->chip_id, CAPP_ERR_STATUS_CTRL + offset, ®); + if ((reg & PPC_BIT(5))) { + PHBERR(p, "CAPP: recovery failed (%016llx)\n", reg); + ret = OPAL_HARDWARE; + break; + } else if ((reg & PPC_BIT(0)) && (!(reg & PPC_BIT(1)))) { + PHBDBG(p, "CAPP: recovery in progress\n"); + ret = OPAL_BUSY; + break; + } + + /* + * Mark the CAPP attached to the PHB right away so that + * if a MCE happens during CAPP init we can handle it. + * In case of an error in CAPP init we remove the PHB + * from the attached_mask later. + */ + chip->capp_phb4_attached_mask |= 1 << p->index; ret = enable_capi_mode(p, pe_number, - CAPP_MIN_STQ_ENGINES | - CAPP_MAX_DMA_READ_ENGINES); - disable_fast_reboot("CAPP being enabled"); - break; - case OPAL_PHB_CAPI_MODE_SNOOP_ON: - /* nothing to do P9 if CAPP is alreay enabled */ - ret = OPAL_SUCCESS; + (mode == OPAL_PHB_CAPI_MODE_DMA_TVT1 ? + /* Max perf for DMA */ + (CAPP_MIN_STQ_ENGINES | + CAPP_MAX_DMA_READ_ENGINES) : + /* Max perf for CAPP STQ */ + (CAPP_MAX_STQ_ENGINES | + CAPP_MIN_DMA_READ_ENGINES))); + + if (ret == OPAL_SUCCESS) + /* Disable fast reboot for CAPP */ + disable_fast_reboot("CAPP being enabled"); + else + /* In case of an error mark the PHB detached */ + chip->capp_phb4_attached_mask ^= 1 << p->index; break; - case OPAL_PHB_CAPI_MODE_PCIE: /* shouldn't be called on p9*/ - case OPAL_PHB_CAPI_MODE_DMA: /* Enabled by default on p9 */ - case OPAL_PHB_CAPI_MODE_SNOOP_OFF: /* shouldn't be called on p9*/ default: ret = OPAL_UNSUPPORTED; - } + break; + }; + unlock(&capi_lock); return ret; } From patchwork Sat Sep 15 14:39:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaibhav Jain X-Patchwork-Id: 970235 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42CFRX0hmHz9sBJ for ; Sun, 16 Sep 2018 00:40:24 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 42CFRW3w2ZzF22T for ; Sun, 16 Sep 2018 00:40:23 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=vaibhav@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 42CFR62xsBzF0RH for ; Sun, 16 Sep 2018 00:40:01 +1000 (AEST) Received: from pps.filterd (m0098404.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w8FEdT4V004856 for ; Sat, 15 Sep 2018 10:40:00 -0400 Received: from e06smtp01.uk.ibm.com (e06smtp01.uk.ibm.com [195.75.94.97]) by mx0a-001b2d01.pphosted.com with ESMTP id 2mgx5w9f7a-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Sat, 15 Sep 2018 10:39:59 -0400 Received: from localhost by e06smtp01.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Sat, 15 Sep 2018 15:39:56 +0100 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w8FEds3955902316 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Sat, 15 Sep 2018 14:39:54 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 700985204F; Sat, 15 Sep 2018 17:39:41 +0100 (BST) Received: from vajain21.in.ibm.com.com (unknown [9.199.55.137]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 1B95A52050; Sat, 15 Sep 2018 17:39:37 +0100 (BST) From: Vaibhav Jain To: Oliver , Michael Neuling , Stewart Smith , Frederic Barrat , Andrew Donnellan , Christophe Lombard , Philippe Bergheaud Date: Sat, 15 Sep 2018 20:09:21 +0530 X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180915143926.12870-1-vaibhav@linux.ibm.com> References: <20180915143926.12870-1-vaibhav@linux.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 18091514-4275-0000-0000-000002BABAE2 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18091514-4276-0000-0000-000037C3FB38 Message-Id: <20180915143926.12870-3-vaibhav@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-09-15_06:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1807170000 definitions=main-1809150161 Subject: [Skiboot] [PATCH 2/7] opal: Introduce opal_del_host_sync_notifier_with_data() X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Current implementation of opal_del_host_sync_notifier() will only delete the first entry of the 'notify' callback found from opal_syners list irrespective of the 'data' of list-node. This is problematic when multiple notifiers with same callback function but different 'data' are registered. In this case when the cleanup code will call opal_del_host_sync_notifier() it cannot be sure if correct opal_syncer is removed. Hence we introduce a new function named opal_del_host_sync_notifier_with_data() that iterates over the opal_syncers list and only removes the first node node having the matching value for 'notify' callback and 'data'. Signed-off-by: Vaibhav Jain Reviewed-by: Andrew Donnellan --- core/opal.c | 18 ++++++++++++++++++ include/opal-internal.h | 2 ++ 2 files changed, 20 insertions(+) diff --git a/core/opal.c b/core/opal.c index 63a08510..4a3b4a61 100644 --- a/core/opal.c +++ b/core/opal.c @@ -687,6 +687,24 @@ void opal_del_host_sync_notifier(bool (*notify)(void *data)) } } + +/* + * Remove a host sync notifier for given callback and data + */ +void opal_del_host_sync_notifier_with_data(bool (*notify)(void *data), + void *data) +{ + struct opal_sync_entry *ent; + + list_for_each(&opal_syncers, ent, link) { + if (ent->notify == notify && ent->data == data) { + list_del(&ent->link); + free(ent); + return; + } + } +} + /* * OPAL call to handle host kexec'ing scenario */ diff --git a/include/opal-internal.h b/include/opal-internal.h index 40bad457..4ed62997 100644 --- a/include/opal-internal.h +++ b/include/opal-internal.h @@ -77,6 +77,8 @@ extern void opal_run_pollers(void); */ extern void opal_add_host_sync_notifier(bool (*notify)(void *data), void *data); extern void opal_del_host_sync_notifier(bool (*notify)(void *data)); +extern void opal_del_host_sync_notifier_with_data(bool (*notify)(void *data), + void *data); /* * Opal internal function prototype From patchwork Sat Sep 15 14:39:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaibhav Jain X-Patchwork-Id: 970236 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42CFRw682mz9sBJ for ; Sun, 16 Sep 2018 00:40:44 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 42CFRw2m69zF0RH for ; Sun, 16 Sep 2018 00:40:44 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=vaibhav@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 42CFR936vvzF33P for ; Sun, 16 Sep 2018 00:40:05 +1000 (AEST) Received: from pps.filterd (m0098404.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w8FEdP9I004524 for ; Sat, 15 Sep 2018 10:40:04 -0400 Received: from e06smtp01.uk.ibm.com (e06smtp01.uk.ibm.com [195.75.94.97]) by mx0a-001b2d01.pphosted.com with ESMTP id 2mgx5w9f8c-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Sat, 15 Sep 2018 10:40:03 -0400 Received: from localhost by e06smtp01.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Sat, 15 Sep 2018 15:40:00 +0100 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w8FEdwEe66650366 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Sat, 15 Sep 2018 14:39:58 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id CA9F55204F; Sat, 15 Sep 2018 17:39:45 +0100 (BST) Received: from vajain21.in.ibm.com.com (unknown [9.199.55.137]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id C0E265204E; Sat, 15 Sep 2018 17:39:42 +0100 (BST) From: Vaibhav Jain To: Oliver , Michael Neuling , Stewart Smith , Frederic Barrat , Andrew Donnellan , Christophe Lombard , Philippe Bergheaud Date: Sat, 15 Sep 2018 20:09:22 +0530 X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180915143926.12870-1-vaibhav@linux.ibm.com> References: <20180915143926.12870-1-vaibhav@linux.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 18091514-4275-0000-0000-000002BABAE4 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18091514-4276-0000-0000-000037C3FB3A Message-Id: <20180915143926.12870-4-vaibhav@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-09-15_06:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=982 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1807170000 definitions=main-1809150161 Subject: [Skiboot] [PATCH 3/7] core/pci: Introduce a new pci_slot_op named completed_sm_run() X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" At times we need to perform some cleanup activities when the Opal PCI state machine that perform creset/freset/hreset (driven by pci_slot_ops->run_sm which) of a slot completes. One example can be to mark CAPP attached to a PHB, as deactivated when creset/freset of a CAPI card slot is completed. However the calls to pci_slot_ops->run_sm() is scattered through out the code and patching each call site to check for the return value and perform custom cleanup tacks is difficult. Hence this patch introduces a new pci_slot_ops named completed_sm_run() which should be called when pci_slot_ops->run_sm() determines that the reset state machine is complete. This provides a more centralized way to handle slot related cleanup activities. Signed-off-by: Vaibhav Jain Reviewed-by: Andrew Donnellan --- core/pci-slot.c | 6 +++++- include/pci-slot.h | 1 + 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/core/pci-slot.c b/core/pci-slot.c index 71d2769e..497d0a47 100644 --- a/core/pci-slot.c +++ b/core/pci-slot.c @@ -104,9 +104,13 @@ static int64_t pci_slot_run_sm(struct pci_slot *slot) prlog(PR_ERR, PCI_SLOT_PREFIX "Invalid state %08x\n", slot->id, slot->state); pci_slot_set_state(slot, PCI_SLOT_STATE_NORMAL); - return OPAL_HARDWARE; + ret = OPAL_HARDWARE; } + /* Notify about the pci slot state machine completion */ + if (ret <= 0 && slot->ops.completed_sm_run) + slot->ops.completed_sm_run(slot, ret); + return ret; } diff --git a/include/pci-slot.h b/include/pci-slot.h index cd757535..f3fe0d1d 100644 --- a/include/pci-slot.h +++ b/include/pci-slot.h @@ -110,6 +110,7 @@ struct pci_slot_ops { int64_t (*freset)(struct pci_slot *slot); int64_t (*hreset)(struct pci_slot *slot); int64_t (*run_sm)(struct pci_slot *slot); + void (*completed_sm_run)(struct pci_slot *slot, uint64_t err); /* Auxillary functions */ void (*add_properties)(struct pci_slot *slot, struct dt_node *np); From patchwork Sat Sep 15 14:39:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaibhav Jain X-Patchwork-Id: 970237 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42CFSD17hjz9sBJ for ; Sun, 16 Sep 2018 00:41:00 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 42CFSC6TnJzF1ZS for ; Sun, 16 Sep 2018 00:40:59 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=vaibhav@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 42CFRJ2rqyzF35Q for ; Sun, 16 Sep 2018 00:40:12 +1000 (AEST) Received: from pps.filterd (m0098417.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w8FEdWE8009789 for ; Sat, 15 Sep 2018 10:40:09 -0400 Received: from e06smtp04.uk.ibm.com (e06smtp04.uk.ibm.com [195.75.94.100]) by mx0a-001b2d01.pphosted.com with ESMTP id 2mgwyc1hpb-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Sat, 15 Sep 2018 10:40:09 -0400 Received: from localhost by e06smtp04.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Sat, 15 Sep 2018 15:40:05 +0100 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w8FEe3ee64356476 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Sat, 15 Sep 2018 14:40:03 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8C4E15204E; Sat, 15 Sep 2018 17:39:50 +0100 (BST) Received: from vajain21.in.ibm.com.com (unknown [9.199.55.137]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 3D4D552050; Sat, 15 Sep 2018 17:39:47 +0100 (BST) From: Vaibhav Jain To: Oliver , Michael Neuling , Stewart Smith , Frederic Barrat , Andrew Donnellan , Christophe Lombard , Philippe Bergheaud Date: Sat, 15 Sep 2018 20:09:23 +0530 X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180915143926.12870-1-vaibhav@linux.ibm.com> References: <20180915143926.12870-1-vaibhav@linux.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 18091514-0016-0000-0000-00000205C0F5 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18091514-0017-0000-0000-0000325C9B18 Message-Id: <20180915143926.12870-5-vaibhav@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-09-15_06:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1807170000 definitions=main-1809150161 Subject: [Skiboot] [PATCH 4/7] capp/phb4: Force CAPP to PCIe mode during kernel shutdown X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This patch introduces a new opal syncer for PHB4 named phb4_host_sync_reset(). We register this opal syncer when CAPP is activated successfully in phb4_set_capi_mode() so that it will be called at kernel shutdown during fast-reset. The function will then repeatedly call phb->ops->set_capi_mode() to switch switch CAPP to PCIe mode. In case set_capi_mode() indicates its OPAL_BUSY. It calls slot->ops.run_sm() to ensure that Opal slot reset state machine makes forward progress. Signed-off-by: Vaibhav Jain Reviewed-by: Andrew Donnellan --- hw/phb4.c | 36 +++++++++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/hw/phb4.c b/hw/phb4.c index 4284c467..615cda66 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -2747,6 +2747,36 @@ static void phb4_training_trace(struct phb4 *p) } } +/* + * Trigger a creset to disable CAPI mode on kernel shutdown. + * + * This helper is called repeatedly by the host sync notifier mechanism, which + * relies on the kernel to regularly poll the OPAL_SYNC_HOST_REBOOT call as it + * shuts down. + */ +static bool phb4_host_sync_reset(void *data) +{ + struct phb4 *p = (struct phb4 *)data; + struct phb *phb = &p->phb; + struct pci_slot *slot = p->phb.slot; + int64_t rc = 0; + + /* Make sure no-one modifies the phb flags while we are active */ + phb_lock(phb); + + /* Call phb ops to disable capi */ + rc = phb->ops->set_capi_mode(phb, OPAL_PHB_CAPI_MODE_PCIE, + phb->ops->get_reserved_pe_number(phb)); + if (rc == OPAL_BUSY) { + /* Run the phb reset state machine */ + rc = slot->ops.run_sm(slot); + } + + phb_unlock(phb); + + return rc <= OPAL_SUCCESS; +} + static int64_t phb4_poll_link(struct pci_slot *slot) { struct phb4 *p = phb_to_phb4(slot->phb); @@ -4381,9 +4411,13 @@ static int64_t phb4_set_capi_mode(struct phb *phb, uint64_t mode, (CAPP_MAX_STQ_ENGINES | CAPP_MIN_DMA_READ_ENGINES))); - if (ret == OPAL_SUCCESS) + if (ret == OPAL_SUCCESS) { + /* register notification on system shutdown */ + opal_add_host_sync_notifier(&phb4_host_sync_reset, p); + /* Disable fast reboot for CAPP */ disable_fast_reboot("CAPP being enabled"); + } else /* In case of an error mark the PHB detached */ chip->capp_phb4_attached_mask ^= 1 << p->index; From patchwork Sat Sep 15 14:39:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaibhav Jain X-Patchwork-Id: 970238 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42CFSV31Pkz9sBJ for ; Sun, 16 Sep 2018 00:41:14 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 42CFSV1dRdzF35L for ; Sun, 16 Sep 2018 00:41:14 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=vaibhav@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 42CFRQ2bPgzF2QL for ; Sun, 16 Sep 2018 00:40:18 +1000 (AEST) Received: from pps.filterd (m0098396.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w8FEdRSa111476 for ; Sat, 15 Sep 2018 10:40:16 -0400 Received: from e06smtp01.uk.ibm.com (e06smtp01.uk.ibm.com [195.75.94.97]) by mx0a-001b2d01.pphosted.com with ESMTP id 2mgvdrvdy7-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Sat, 15 Sep 2018 10:40:15 -0400 Received: from localhost by e06smtp01.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Sat, 15 Sep 2018 15:40:09 +0100 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w8FEe8Dm63045656 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Sat, 15 Sep 2018 14:40:08 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5E65C52052; Sat, 15 Sep 2018 17:39:55 +0100 (BST) Received: from vajain21.in.ibm.com.com (unknown [9.199.55.137]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 0FB5452051; Sat, 15 Sep 2018 17:39:51 +0100 (BST) From: Vaibhav Jain To: Oliver , Michael Neuling , Stewart Smith , Frederic Barrat , Andrew Donnellan , Christophe Lombard , Philippe Bergheaud Date: Sat, 15 Sep 2018 20:09:24 +0530 X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180915143926.12870-1-vaibhav@linux.ibm.com> References: <20180915143926.12870-1-vaibhav@linux.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 18091514-4275-0000-0000-000002BABAE8 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18091514-4276-0000-0000-000037C3FB3C Message-Id: <20180915143926.12870-6-vaibhav@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-09-15_06:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1807170000 definitions=main-1809150161 Subject: [Skiboot] [PATCH 5/7] capp/phb4: Introduce PHB4 flag, PHB4_CAPP_DISABLE to disable CAPP X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This patch introduces a PHB4 flag PHB4_CAPP_DISABLE and scaffolding necessary to handle it during CRESET flow. The flag is set when CAPP is request to switch to PCIe mode via call to phb4_set_capi_mode() with mode OPAL_PHB_CAPI_MODE_PCIE. This starts the below sequence that ultimately ends in newly introduced phb4_slot_sm_run_completed() 1. Set PHB4_CAPP_DISABLE to phb4->flags. 2. Start a CRESET on the phb slot. This also starts the opal pci reset state machine. 3. Wait for slot state to be PHB4_SLOT_CRESET_WAIT_CQ. 4. Perform CAPP recovery as PHB is still fenced, by calling do_capp_recovery_scoms(). 5. Call newly introduced 'disable_capi_mode()' to disable CAPP. 6. Wait for slot reset to complete while it transitions to PHB4_SLOT_FRESET and optionally to PHB4_SLOT_LINK_START. 7. Once slot reset is complete opal pci-core state machine will call slot->ops.completed_sm_run(). 8. For PHB4 this branches newly introduced 'phb4_slot_sm_run_completed()'. 9. Inside this function we mark the CAPP as disabled and un-register the opal syncer phb4_host_sync_reset(). 10. Optionally if the slot reset was unsuccessful disable fast-reboot. **************************** Notes: **************************** a. Function 'disable_capi_mode()' performs various sanity tests on CAPP to to determine if its ok to disable it and perform necessary xscoms to disable it. However the current implementation proposed in this patch is a skeleton one that just does sanity tests. A followup patch will be proposed that implements the xscoms necessary to disable CAPP. b. The sequence expects that Opal PCI reset state machine makes forward progress hence needs someone to call slot->ops.run_sm(). This can be either from phb4_host_sync_reset() or opal_pci_poll(). Signed-off-by: Vaibhav Jain --- hw/phb4.c | 101 ++++++++++++++++++++++++++++++++++++++++++++++++- include/phb4.h | 1 + 2 files changed, 101 insertions(+), 1 deletion(-) diff --git a/hw/phb4.c b/hw/phb4.c index 615cda66..16a4a62a 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -2777,6 +2777,38 @@ static bool phb4_host_sync_reset(void *data) return rc <= OPAL_SUCCESS; } +/* + * Notification from the pci-core that a pci slot state machine completed. + * We use this callback to mark the CAPP disabled if we were waiting for it. + */ +static void phb4_slot_sm_run_completed(struct pci_slot *slot, uint64_t err) +{ + struct phb4 *p = phb_to_phb4(slot->phb); + struct proc_chip *chip = get_chip(p->chip_id); + + /* Check if we are disabling the capp */ + if (p->flags & PHB4_CAPP_DISABLE) { + /* Make sure we done stomp on some else's req to enable capp */ + lock(&capi_lock); + + /* Unset the flags so that we dont fall into a creset loop */ + p->flags &= ~(PHB4_CAPP_DISABLE); + chip->capp_phb4_attached_mask &= ~(1 << p->index); + + /* Remove the host sync notifier is we are done.*/ + opal_del_host_sync_notifier_with_data(phb4_host_sync_reset, + p); + if (err) { + /* Force a CEC ipl reboot */ + disable_fast_reboot("CAPP: reset failed"); + PHBERR(p, "CAPP: Unable to reset. Error=%lld\n", err); + } else { + PHBINF(p, "CAPP: reset complete\n"); + } + unlock(&capi_lock); + } +} + static int64_t phb4_poll_link(struct pci_slot *slot) { struct phb4 *p = phb_to_phb4(slot->phb); @@ -3116,6 +3148,44 @@ static int do_capp_recovery_scoms(struct phb4 *p) return rc; } +/* + * Disable CAPI mode on a PHB. Must be done while PHB is fenced and + * not in recovery. + */ +static void disable_capi_mode(struct phb4 *p) +{ + struct proc_chip *chip = get_chip(p->chip_id); + uint64_t reg; + uint32_t offset = PHB4_CAPP_REG_OFFSET(p); + + PHBINF(p, "CAPP: Deactivating\n"); + + /* Check if CAPP attached to the PHB and active */ + if (!(chip->capp_phb4_attached_mask & (1 << p->index))) { + PHBERR(p, "CAPP: Not attached to this PHB!\n"); + return; + } + + xscom_read(p->chip_id, p->pe_xscom + XPEC_NEST_CAPP_CNTL, ®); + if (!(reg & PPC_BIT(0))) { + /* Not in CAPI mode, no action required */ + PHBDBG(p, "CAPP: Not enabled!\n"); + return; + } + + /* CAPP should already be out of recovery in this function */ + xscom_read(p->chip_id, CAPP_ERR_STATUS_CTRL + offset, ®); + if (reg & PPC_BIT(0)) { + PHBERR(p, "CAPP: Cant disable while still in recovery!\n"); + return; + } + + PHBINF(p, "CAPP: Disabling CAPI mode\n"); + + /* Implement procedure to disable CAPP based on h/w sequence */ +} + + static int64_t phb4_creset(struct pci_slot *slot) { struct phb4 *p = phb_to_phb4(slot->phb); @@ -3176,6 +3246,9 @@ static int64_t phb4_creset(struct pci_slot *slot) (do_capp_recovery_scoms(p) != OPAL_SUCCESS)) goto error; + if (p->flags & PHB4_CAPP_DISABLE) + disable_capi_mode(p); + /* Clear errors in PFIR and NFIR */ xscom_write(p->chip_id, p->pci_stk_xscom + 0x1, ~p->pfir_cache); @@ -3260,6 +3333,7 @@ static struct pci_slot *phb4_slot_create(struct phb *phb) slot->ops.hreset = phb4_hreset; slot->ops.freset = phb4_freset; slot->ops.creset = phb4_creset; + slot->ops.completed_sm_run = phb4_slot_sm_run_completed; slot->link_retries = PHB4_LINK_LINK_RETRIES; return slot; @@ -4371,12 +4445,36 @@ static int64_t phb4_set_capi_mode(struct phb *phb, uint64_t mode, break; case OPAL_PHB_CAPI_MODE_SNOOP_OFF: - case OPAL_PHB_CAPI_MODE_PCIE: /* Not supported at the moment */ ret = !attached ? OPAL_SUCCESS : OPAL_UNSUPPORTED; break; + case OPAL_PHB_CAPI_MODE_PCIE: + if (p->flags & PHB4_CAPP_DISABLE) { + /* We are in middle of a CAPP disable */ + ret = OPAL_BUSY; + + } else if (attached) { + p->flags |= PHB4_CAPP_DISABLE; + PHBINF(p, "CAPP: PCIE mode needs a cold-reset\n"); + /* Kick off the pci state machine */ + ret = phb4_creset(phb->slot); + ret = ret > 0 ? OPAL_BUSY : ret; + + } else { + /* PHB already in PCI mode */ + ret = OPAL_SUCCESS; + } + break; + case OPAL_PHB_CAPI_MODE_CAPI: /* Fall Through */ case OPAL_PHB_CAPI_MODE_DMA_TVT1: + /* Make sure that PHB is not disabling CAPP */ + if (p->flags & PHB4_CAPP_DISABLE) { + PHBERR(p, "CAPP: Disable in progress\n"); + ret = OPAL_BUSY; + break; + } + /* Check if ucode is available */ if (!capp_ucode_loaded(chip, p->index)) { PHBERR(p, "CAPP: ucode not loaded\n"); @@ -4389,6 +4487,7 @@ static int64_t phb4_set_capi_mode(struct phb *phb, uint64_t mode, PHBERR(p, "CAPP: recovery failed (%016llx)\n", reg); ret = OPAL_HARDWARE; break; + } else if ((reg & PPC_BIT(0)) && (!(reg & PPC_BIT(1)))) { PHBDBG(p, "CAPP: recovery in progress\n"); ret = OPAL_BUSY; diff --git a/include/phb4.h b/include/phb4.h index d78bc317..050548be 100644 --- a/include/phb4.h +++ b/include/phb4.h @@ -164,6 +164,7 @@ struct phb4_err { #define PHB4_CFG_USE_ASB 0x00000002 #define PHB4_CFG_BLOCKED 0x00000004 #define PHB4_CAPP_RECOVERY 0x00000008 +#define PHB4_CAPP_DISABLE 0x00000010 struct phb4 { unsigned int index; /* 0..5 index inside p9 */ From patchwork Sat Sep 15 14:39:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaibhav Jain X-Patchwork-Id: 970240 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42CFT30tTWz9sBJ for ; Sun, 16 Sep 2018 00:41:43 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 42CFT26TRWzF34W for ; Sun, 16 Sep 2018 00:41:42 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=vaibhav@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 42CFRT6bVYzF2QL for ; Sun, 16 Sep 2018 00:40:21 +1000 (AEST) Received: from pps.filterd (m0098396.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w8FEdQad111449 for ; Sat, 15 Sep 2018 10:40:20 -0400 Received: from e06smtp01.uk.ibm.com (e06smtp01.uk.ibm.com [195.75.94.97]) by mx0a-001b2d01.pphosted.com with ESMTP id 2mgvdrve10-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Sat, 15 Sep 2018 10:40:20 -0400 Received: from localhost by e06smtp01.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Sat, 15 Sep 2018 15:40:14 +0100 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w8FEeDhE64749612 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Sat, 15 Sep 2018 14:40:13 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4E0D05204F; Sat, 15 Sep 2018 17:40:00 +0100 (BST) Received: from vajain21.in.ibm.com.com (unknown [9.199.55.137]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id D60475204E; Sat, 15 Sep 2018 17:39:56 +0100 (BST) From: Vaibhav Jain To: Oliver , Michael Neuling , Stewart Smith , Frederic Barrat , Andrew Donnellan , Christophe Lombard , Philippe Bergheaud Date: Sat, 15 Sep 2018 20:09:25 +0530 X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180915143926.12870-1-vaibhav@linux.ibm.com> References: <20180915143926.12870-1-vaibhav@linux.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 18091514-4275-0000-0000-000002BABAEC X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18091514-4276-0000-0000-000037C3FB42 Message-Id: <20180915143926.12870-7-vaibhav@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-09-15_06:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1807170000 definitions=main-1809150161 Subject: [Skiboot] [PATCH 6/7] phb4/capp: Implement sequence to disable CAPP and enable fast-reset X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" We implement h/w sequence to disable CAPP in disable_capi_mode() and with it also enable fast-reset for CAPI mode in phb4_set_capi_mode(). Sequence to disable CAPP is executed in three phases. The first two phase is implemented in disable_capi_mode() where we reset the CAPP registers followed by PEC registers to their init values. The final third final phase is to reset the PHB CAPI Compare/Mask Register and is done in phb4_init_ioda3(). The reason to move the PHB reset to phb4_init_ioda3() is because by the time Opal PCI reset state machine reaches this function the PHB is already un-fenced and its configuration registers accessible via mmio. Signed-off-by: Vaibhav Jain --- hw/phb4.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 66 insertions(+), 6 deletions(-) diff --git a/hw/phb4.c b/hw/phb4.c index 16a4a62a..2e0ed191 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -3182,7 +3182,68 @@ static void disable_capi_mode(struct phb4 *p) PHBINF(p, "CAPP: Disabling CAPI mode\n"); - /* Implement procedure to disable CAPP based on h/w sequence */ + /* First Phase Reset CAPP Registers */ + /* CAPP about to be disabled mark TLBI_FENCED and tlbi_psl_is_dead */ + xscom_write(p->chip_id, CAPP_ERR_STATUS_CTRL + offset, PPC_BIT(3)| + PPC_BIT(4)); + + /* Flush SUE uOP1 Register */ + if (!(p->rev == PHB4_REV_NIMBUS_DD10)) + xscom_write(p->chip_id, FLUSH_SUE_UOP1 + offset, 0); + + /* Release DMA/STQ engines */ + xscom_write(p->chip_id, APC_FSM_READ_MASK + offset, 0ull); + xscom_write(p->chip_id, XPT_FSM_RMM + offset, 0ull); + + /* Disable snoop */ + xscom_write(p->chip_id, SNOOP_CAPI_CONFIG + offset, 0); + + /* Clear flush SUE state map register */ + xscom_write(p->chip_id, FLUSH_SUE_STATE_MAP + offset, 0); + + /* Disable epoch timer */ + xscom_write(p->chip_id, EPOCH_RECOVERY_TIMERS_CTRL + offset, 0); + + /* CAPP Transport Control Register */ + xscom_write(p->chip_id, TRANSPORT_CONTROL + offset, PPC_BIT(15)); + + /* Disable snooping */ + xscom_write(p->chip_id, SNOOP_CONTROL + offset, 0); + xscom_write(p->chip_id, SNOOP_CAPI_CONFIG + offset, 0); + + /* APC Master PB Control Register - disable examining cResps */ + xscom_write(p->chip_id, APC_MASTER_PB_CTRL + offset, 0); + + /* APC Master Config Register - de-select PHBs */ + xscom_write_mask(p->chip_id, APC_MASTER_CAPI_CTRL + offset, 0, + PPC_BITMASK(2, 3)); + + /* Clear all error registers */ + xscom_write(p->chip_id, CAPP_ERR_RPT_CLR + offset, 0); + xscom_write(p->chip_id, CAPP_FIR + offset, 0); + xscom_write(p->chip_id, CAPP_FIR_ACTION0 + offset, 0); + xscom_write(p->chip_id, CAPP_FIR_ACTION1 + offset, 0); + xscom_write(p->chip_id, CAPP_FIR_MASK + offset, 0); + + /* Second Phase Reset PEC/PHB Registers */ + + /* Reset the stack overrides if any */ + xscom_write(p->chip_id, p->pci_xscom + XPEC_PCI_PRDSTKOVR, 0); + xscom_write(p->chip_id, p->pe_xscom + + XPEC_NEST_READ_STACK_OVERRIDE, 0); + + /* PE Bus AIB Mode Bits. Disable Tracing. Leave HOL Blocking as it is */ + if (!(p->rev == PHB4_REV_NIMBUS_DD10) && p->index == CAPP1_PHB_INDEX) + xscom_write_mask(p->chip_id, + p->pci_xscom + XPEC_PCI_PBAIB_HW_CONFIG, 0, + PPC_BIT(30)); + + /* Reset for PCI to PB data movement */ + xscom_write_mask(p->chip_id, p->pe_xscom + XPEC_NEST_PBCQ_HW_CONFIG, + 0, XPEC_NEST_PBCQ_HW_CONFIG_PBINIT); + + /* Disable CAPP mode in PEC CAPP Control Register */ + xscom_write(p->chip_id, p->pe_xscom + XPEC_NEST_CAPP_CNTL, 0ull); } @@ -4510,13 +4571,9 @@ static int64_t phb4_set_capi_mode(struct phb *phb, uint64_t mode, (CAPP_MAX_STQ_ENGINES | CAPP_MIN_DMA_READ_ENGINES))); - if (ret == OPAL_SUCCESS) { + if (ret == OPAL_SUCCESS) /* register notification on system shutdown */ opal_add_host_sync_notifier(&phb4_host_sync_reset, p); - - /* Disable fast reboot for CAPP */ - disable_fast_reboot("CAPP being enabled"); - } else /* In case of an error mark the PHB detached */ chip->capp_phb4_attached_mask ^= 1 << p->index; @@ -4731,6 +4788,9 @@ static void phb4_init_ioda3(struct phb4 *p) /* Init_26 - CAPI Compare/Mask */ /* See enable_capi_mode() */ + /* if CAPP being disabled then reset CAPI Compare/Mask Register */ + if (p->flags & PHB4_CAPP_DISABLE) + out_be64(p->regs + PHB_CAPI_CMPM, 0); /* Init_27 - PCIE Outbound upper address */ out_be64(p->regs + PHB_M64_UPPER_BITS, 0); From patchwork Sat Sep 15 14:39:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaibhav Jain X-Patchwork-Id: 970241 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42CFTL48j1z9sBJ for ; Sun, 16 Sep 2018 00:41:58 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 42CFTL2x72zF1nv for ; Sun, 16 Sep 2018 00:41:58 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=vaibhav@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 42CFRZ17rzzF26K for ; Sun, 16 Sep 2018 00:40:25 +1000 (AEST) Received: from pps.filterd (m0098409.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w8FEdbMQ061674 for ; Sat, 15 Sep 2018 10:40:23 -0400 Received: from e06smtp07.uk.ibm.com (e06smtp07.uk.ibm.com [195.75.94.103]) by mx0a-001b2d01.pphosted.com with ESMTP id 2mgwd3jmrq-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Sat, 15 Sep 2018 10:40:23 -0400 Received: from localhost by e06smtp07.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Sat, 15 Sep 2018 15:40:21 +0100 Received: from b06cxnps3075.portsmouth.uk.ibm.com (9.149.109.195) by e06smtp07.uk.ibm.com (192.168.101.137) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Sat, 15 Sep 2018 15:40:19 +0100 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w8FEeH3h53084258 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Sat, 15 Sep 2018 14:40:17 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BC2475204E; Sat, 15 Sep 2018 17:40:04 +0100 (BST) Received: from vajain21.in.ibm.com.com (unknown [9.199.55.137]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id B3FF252050; Sat, 15 Sep 2018 17:40:01 +0100 (BST) From: Vaibhav Jain To: Oliver , Michael Neuling , Stewart Smith , Frederic Barrat , Andrew Donnellan , Christophe Lombard , Philippe Bergheaud Date: Sat, 15 Sep 2018 20:09:26 +0530 X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180915143926.12870-1-vaibhav@linux.ibm.com> References: <20180915143926.12870-1-vaibhav@linux.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 18091514-0028-0000-0000-000002F9BA25 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18091514-0029-0000-0000-000023B365FC Message-Id: <20180915143926.12870-8-vaibhav@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-09-15_06:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1807170000 definitions=main-1809150161 Subject: [Skiboot] [PATCH 7/7] capp/phb4: Prevent HMI from getting triggered when disabling CAPP X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" While disabling CAPP an HMI gets triggered as soon as ETU is put in reset mode. This is caused as before we can disabled CAPP, it detects PHB link going down and triggers an HMI requesting Opal to perform CAPP recovery. This has an un-intended side effect of spamming the Opal logs with malfunction alert messages and may also confuse the user. To prevent this we mask the CAPP FIR error 'PHB Link Down' Bit(31) when we are disabling CAPP just before we put ETU in reset in phb4_creset(). Also now since bringing down the PHB link now wont trigger an HMI and CAPP recovery, hence we manually set the PHB4_CAPP_RECOVERY flag on the phb to force recovery during creset. Signed-off-by: Vaibhav Jain --- hw/phb4.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/phb4.c b/hw/phb4.c index 2e0ed191..821cf94f 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -3265,6 +3265,15 @@ static int64_t phb4_creset(struct pci_slot *slot) /* Clear error inject register, preventing recursive errors */ xscom_write(p->chip_id, p->pe_xscom + 0x2, 0x0); + /* Prevent HMI when PHB gets fenced as we are disabling CAPP */ + if (p->flags & PHB4_CAPP_DISABLE) { + /* Since no HMI, So set the recovery flag manually. */ + p->flags |= PHB4_CAPP_RECOVERY; + xscom_write_mask(p->chip_id, CAPP_FIR_MASK + + PHB4_CAPP_REG_OFFSET(p), + PPC_BIT(31), PPC_BIT(31)); + } + /* Force fence on the PHB to work around a non-existent PE */ if (!phb4_fenced(p)) xscom_write(p->chip_id, p->pe_stk_xscom + 0x2,