From patchwork Tue Sep 11 07:26:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Yves MORDRET X-Patchwork-Id: 968457 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=st.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 428c286B3Jz9s5c for ; Tue, 11 Sep 2018 17:27:44 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727865AbeIKMZk (ORCPT ); Tue, 11 Sep 2018 08:25:40 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:58860 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727384AbeIKMZj (ORCPT ); Tue, 11 Sep 2018 08:25:39 -0400 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w8B7NucM011467; Tue, 11 Sep 2018 09:27:06 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2me8jb89mg-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 11 Sep 2018 09:27:06 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 324B63D; Tue, 11 Sep 2018 07:27:05 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag5node2.st.com [10.75.127.14]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 054741E3B; Tue, 11 Sep 2018 07:27:05 +0000 (GMT) Received: from localhost (10.75.127.47) by SFHDAG5NODE2.st.com (10.75.127.14) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 11 Sep 2018 09:27:04 +0200 From: Pierre-Yves MORDRET To: Vinod Koul , Rob Herring , Mark Rutland , Alexandre Torgue , Maxime Coquelin , Dan Williams , , , , CC: Pierre-Yves MORDRET Subject: [PATCH v1 1/7] dt-bindings: stm32-dma: Add DMA/MDMA chaining support bindings Date: Tue, 11 Sep 2018 09:26:54 +0200 Message-ID: <1536650820-16076-2-git-send-email-pierre-yves.mordret@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1536650820-16076-1-git-send-email-pierre-yves.mordret@st.com> References: <1536650820-16076-1-git-send-email-pierre-yves.mordret@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.47] X-ClientProxiedBy: SFHDAG6NODE2.st.com (10.75.127.17) To SFHDAG5NODE2.st.com (10.75.127.14) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-09-11_03:, , signatures=0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds dma bindings to support DMA/MDMA chaining transfer. 1 bit is to manage both DMA FIFO Threshold 1 bit is to manage DMA/MDMA Chaining features. 2 bits are used to specify SDRAM size to use for DMA/MDMA chaining. The size in bytes of a certain order is given by the formula: (2 ^ order) * PAGE_SIZE. The order is given by those 2 bits. For cyclic, whether chaining is chosen, any value above 1 can be set : SRAM buffer size will rely on period size and not on this DT value. Signed-off-by: Pierre-Yves MORDRET --- Version history: v1: * Initial --- --- .../devicetree/bindings/dma/stm32-dma.txt | 32 +++++++++++++++++++--- 1 file changed, 28 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/stm32-dma.txt b/Documentation/devicetree/bindings/dma/stm32-dma.txt index c5f5190..163be09 100644 --- a/Documentation/devicetree/bindings/dma/stm32-dma.txt +++ b/Documentation/devicetree/bindings/dma/stm32-dma.txt @@ -17,6 +17,12 @@ Optional properties: - resets: Reference to a reset controller asserting the DMA controller - st,mem2mem: boolean; if defined, it indicates that the controller supports memory-to-memory transfer +- dmas: A list of eight dma specifiers, one for each entry in dma-names. + Refer to stm32-mdma.txt for more details. +- dma-names: should contain "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6" and + "ch7" and represents each STM32 DMA channel connected to a STM32 MDMA one. +- memory-region : phandle to a node describing memory to be used for + M2M intermediate transfer between DMA and MDMA. Example: @@ -36,6 +42,16 @@ Example: st,mem2mem; resets = <&rcc 150>; dma-requests = <8>; + dmas = <&mdma1 8 0x10 0x1200000a 0x40026408 0x00000020 1>, + <&mdma1 9 0x10 0x1200000a 0x40026408 0x00000800 1>, + <&mdma1 10 0x10 0x1200000a 0x40026408 0x00200000 1>, + <&mdma1 11 0x10 0x1200000a 0x40026408 0x08000000 1>, + <&mdma1 12 0x10 0x1200000a 0x4002640C 0x00000020 1>, + <&mdma1 13 0x10 0x1200000a 0x4002640C 0x00000800 1>, + <&mdma1 14 0x10 0x1200000a 0x4002640C 0x00200000 1>, + <&mdma1 15 0x10 0x1200000a 0x4002640C 0x08000000 1>; + dma-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7"; + memory-region = <&sram_dmapool>; }; * DMA client @@ -62,13 +78,21 @@ channel: a phandle to the DMA controller plus the following four integer cells: 0x1: medium 0x2: high 0x3: very high -4. A 32bit bitfield value specifying DMA features which are device dependent: +4. A bitfield value specifying DMA features which are device dependent: -bit 0-1: DMA FIFO threshold selection 0x0: 1/4 full FIFO 0x1: 1/2 full FIFO 0x2: 3/4 full FIFO 0x3: full FIFO - + -bit 2: Intermediate M2M transfer from/to DDR to/from SRAM throughout MDMA + 0: MDMA not used to generate an intermediate M2M transfer + 1: MDMA used to generate an intermediate M2M transfer. + -bit 3-4: indicated SRAM Buffer size in (2^order)*PAGE_SIZE. + Order is given by those 2 bits starting at 0. + Valid only whether Intermediate M2M transfer is set. + For cyclic, whether Intermediate M2M transfer is chosen, any value can + be set: SRAM buffer size will rely on period size and not on this DT + value. Example: @@ -77,7 +101,7 @@ Example: reg = <0x40011000 0x400>; interrupts = <37>; clocks = <&clk_pclk2>; - dmas = <&dma2 2 4 0x10400 0x3>, - <&dma2 7 5 0x10200 0x3>; + dmas = <&dma2 2 4 0x10400 0x1>, + <&dma2 7 5 0x10200 0x1>; dma-names = "rx", "tx"; }; From patchwork Tue Sep 11 07:26:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Yves MORDRET X-Patchwork-Id: 968459 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=st.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 428c2l0hdrz9s55 for ; Tue, 11 Sep 2018 17:28:15 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727833AbeIKMZg (ORCPT ); Tue, 11 Sep 2018 08:25:36 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:10010 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727793AbeIKMZe (ORCPT ); Tue, 11 Sep 2018 08:25:34 -0400 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w8B7OI0m026390; Tue, 11 Sep 2018 09:27:06 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2me62r0yce-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 11 Sep 2018 09:27:06 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 228BF34; Tue, 11 Sep 2018 07:27:06 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag5node2.st.com [10.75.127.14]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id C6AAB1E40; Tue, 11 Sep 2018 07:27:05 +0000 (GMT) Received: from localhost (10.75.127.47) by SFHDAG5NODE2.st.com (10.75.127.14) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 11 Sep 2018 09:27:05 +0200 From: Pierre-Yves MORDRET To: Vinod Koul , Rob Herring , Mark Rutland , Alexandre Torgue , Maxime Coquelin , Dan Williams , , , , CC: Pierre-Yves MORDRET Subject: [PATCH v1 2/7] dt-bindings: stm32-dmamux: Add one cell to support DMA/MDMA chain Date: Tue, 11 Sep 2018 09:26:55 +0200 Message-ID: <1536650820-16076-3-git-send-email-pierre-yves.mordret@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1536650820-16076-1-git-send-email-pierre-yves.mordret@st.com> References: <1536650820-16076-1-git-send-email-pierre-yves.mordret@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.47] X-ClientProxiedBy: SFHDAG3NODE1.st.com (10.75.127.7) To SFHDAG5NODE2.st.com (10.75.127.14) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-09-11_03:, , signatures=0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add one cell to support DMA/MDMA chaining. Signed-off-by: Pierre-Yves MORDRET --- Version history: v1: * Initial --- --- Documentation/devicetree/bindings/dma/stm32-dmamux.txt | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/stm32-dmamux.txt b/Documentation/devicetree/bindings/dma/stm32-dmamux.txt index 1b893b2..8e092d2 100644 --- a/Documentation/devicetree/bindings/dma/stm32-dmamux.txt +++ b/Documentation/devicetree/bindings/dma/stm32-dmamux.txt @@ -4,9 +4,6 @@ Required properties: - compatible: "st,stm32h7-dmamux" - reg: Memory map for accessing module - #dma-cells: Should be set to <3>. - First parameter is request line number. - Second is DMA channel configuration - Third is Fifo threshold For more details about the three cells, please see stm32-dma.txt documentation binding file - dma-masters: Phandle pointing to the DMA controllers. @@ -53,7 +50,7 @@ dma2: dma@40020400 { <68>, <69>, <70>; - clocks = <&timer_clk>; + clocks = <&clk_hclk>; #dma-cells = <4>; st,mem2mem; resets = <&rcc 150>; From patchwork Tue Sep 11 07:26:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Yves MORDRET X-Patchwork-Id: 968460 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=st.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 428c2n6qnwz9s55 for ; Tue, 11 Sep 2018 17:28:17 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727798AbeIKMZd (ORCPT ); Tue, 11 Sep 2018 08:25:33 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:4488 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727384AbeIKMZc (ORCPT ); Tue, 11 Sep 2018 08:25:32 -0400 Received: from pps.filterd (m0046037.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w8B7OVEh032029; Tue, 11 Sep 2018 09:27:07 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2me96f825p-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 11 Sep 2018 09:27:07 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id CE5733F; Tue, 11 Sep 2018 07:27:06 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag5node2.st.com [10.75.127.14]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id A15801E3B; Tue, 11 Sep 2018 07:27:06 +0000 (GMT) Received: from localhost (10.75.127.46) by SFHDAG5NODE2.st.com (10.75.127.14) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 11 Sep 2018 09:27:06 +0200 From: Pierre-Yves MORDRET To: Vinod Koul , Rob Herring , Mark Rutland , Alexandre Torgue , Maxime Coquelin , Dan Williams , , , , CC: Pierre-Yves MORDRET Subject: [PATCH v1 3/7] dt-bindings: stm32-mdma: Add DMA/MDMA chaining support bindings Date: Tue, 11 Sep 2018 09:26:56 +0200 Message-ID: <1536650820-16076-4-git-send-email-pierre-yves.mordret@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1536650820-16076-1-git-send-email-pierre-yves.mordret@st.com> References: <1536650820-16076-1-git-send-email-pierre-yves.mordret@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.46] X-ClientProxiedBy: SFHDAG5NODE1.st.com (10.75.127.13) To SFHDAG5NODE2.st.com (10.75.127.14) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-09-11_03:, , signatures=0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds the description of the 2 properties needed to support M2M transfer triggered by STM32 DMA when his transfer is complete. Signed-off-by: Pierre-Yves MORDRET --- Version history: v1: * Initial --- --- .../devicetree/bindings/dma/stm32-mdma.txt | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/stm32-mdma.txt b/Documentation/devicetree/bindings/dma/stm32-mdma.txt index d18772d..1810f87 100644 --- a/Documentation/devicetree/bindings/dma/stm32-mdma.txt +++ b/Documentation/devicetree/bindings/dma/stm32-mdma.txt @@ -10,7 +10,7 @@ Required properties: - interrupts: Should contain the MDMA interrupt. - clocks: Should contain the input clock of the DMA instance. - resets: Reference to a reset controller asserting the DMA controller. -- #dma-cells : Must be <5>. See DMA client paragraph for more details. +- #dma-cells : Must be <6>. See DMA client paragraph for more details. Optional properties: - dma-channels: Number of DMA channels supported by the controller. @@ -26,7 +26,7 @@ Example: interrupts = <122>; clocks = <&timer_clk>; resets = <&rcc 992>; - #dma-cells = <5>; + #dma-cells = <6>; dma-channels = <16>; dma-requests = <32>; st,ahb-addr-masks = <0x20000000>, <0x00000000>; @@ -35,8 +35,8 @@ Example: * DMA client DMA clients connected to the STM32 MDMA controller must use the format -described in the dma.txt file, using a five-cell specifier for each channel: -a phandle to the MDMA controller plus the following five integer cells: +described in the dma.txt file, using a six-cell specifier for each channel: +a phandle to the MDMA controller plus the following six integer cells: 1. The request line number 2. The priority level @@ -76,19 +76,23 @@ a phandle to the MDMA controller plus the following five integer cells: if no HW ack signal is used by the MDMA client 5. A 32bit mask specifying the value to be written to acknowledge the request if no HW ack signal is used by the MDMA client +6. A bitfield value specifying if the MDMA client wants to generate M2M + transfer with HW trigger (1) or not (0). This bitfield should be only + enabled for M2M transfer triggered by STM32 DMA client. The memory devices + involved in this kind of transfer are SRAM and DDR. Example: i2c4: i2c@5c002000 { compatible = "st,stm32f7-i2c"; reg = <0x5c002000 0x400>; - interrupts = <95>, - <96>; - clocks = <&timer_clk>; + interrupts = , + ; + clocks = <&clk_hsi>; #address-cells = <1>; #size-cells = <0>; - dmas = <&mdma1 36 0x0 0x40008 0x0 0x0>, - <&mdma1 37 0x0 0x40002 0x0 0x0>; + dmas = <&mdma1 36 0x0 0x40008 0x0 0x0 0>, + <&mdma1 37 0x0 0x40002 0x0 0x0 0>; dma-names = "rx", "tx"; status = "disabled"; };