From patchwork Mon Sep 3 12:29:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Hua X-Patchwork-Id: 965402 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-484998-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="qc3urx6l"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="drx2G+86"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 423q6s23RGz9s4Z for ; Mon, 3 Sep 2018 22:30:11 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:cc:content-type; q=dns; s=default; b=MC4kCyh/d5SYSdrPqccAI09gwwCN4/cty9q/utHMBCw IztZsSdJ4/abnAh5sQoOyRYDzMs/+tON3YG6PqUu+AIK7et45ggca10qZjHIYnFt pYliwNaN9XyW0CUhYuotVYleTmudl3bD7pxo33rPD4JcIL1f5oYQCg+lt7WNdxYs = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:cc:content-type; s=default; bh=k7wAbj9Qd3clXspNGwBlrLy83uA=; b=qc3urx6lpvLdvbLXD i4nl01e/JFWHT4+16krf1J4XA21/g5pzTIFHWjOzO3eKV0ivKk2C/I/k+FuG9O+L iz5MK34eqHvlh9CUKpXkdFNQQeLMzGWwPI3mSfhxXzEdFwGNeTQkUo+rsUF3YgZA VWNRRkwNi8VLNQFPoDwLuK9bZs= Received: (qmail 65674 invoked by alias); 3 Sep 2018 12:29:59 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 65658 invoked by uid 89); 3 Sep 2018 12:29:59 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-25.0 required=5.0 tests=FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS, TIME_LIMIT_EXCEEDED autolearn=unavailable version=3.3.2 spammy=respectively, GPL, gpl, twice X-HELO: mail-oi0-f52.google.com Received: from mail-oi0-f52.google.com (HELO mail-oi0-f52.google.com) (209.85.218.52) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 03 Sep 2018 12:29:48 +0000 Received: by mail-oi0-f52.google.com with SMTP id c190-v6so676450oig.6 for ; Mon, 03 Sep 2018 05:29:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to:cc; bh=Tyej0uUjI6O+8WHGkS0ZQPTN+88KU4JlSgFBR6P0R0A=; b=drx2G+86HiJ6/9QJZlTw1ljEUYgRrtAHwlrne9VX78uBPBXyKqe2IV49OmmjFK0G8l 2Ejla46hETqrFFSmA64WeNemE8tNQXQIH8G8GsDygicLQmEOUa9CLr/sIqr0Fsbe23Jg VjZEtudgRpW9p7LM6d2KJJnx/WqQALz9U4tHpPO8eOEMxyB4HZDbrsHdiLMVHDKy8Asn 8IthOGD8qe0FEWQLj2WLZ/lFdL9WPJV7OBnENdHgWkoOqW3at+anyfD1skGxhZps+So9 u3Jrx8WdyIN2kVFmRUbJr6vhw5rW1jMRpvQrMpJ4Rg4tTz5BetGP6bIdT0iqqlLIrVbP Uz5Q== MIME-Version: 1.0 From: Paul Hua Date: Mon, 3 Sep 2018 20:29:35 +0800 Message-ID: Subject: [PATCH 1/6] [MIPS] Split Loongson (MMI) from loongson3a To: gcc-patches Cc: Matthew Fortune X-IsSubscribed: yes From e744693361de2af27ad8bc45aa1d745b0adf5919 Mon Sep 17 00:00:00 2001 From: Chenghua Xu Date: Wed, 25 Jul 2018 16:39:03 +0800 Subject: [PATCH 1/6] [MIPS] Add support for loongson mmi instructions. gcc/ * config.gcc (extra_headers): Add loongson-mmiintrin.h. * config/mips/loongson.md: Move to ... * config/mips/loongson-mmi.md: here; Adjustment. * config/mips/loongsson.h: Move to ... State as deprecated. Include loongson-mmiintrin.h for back compatibility and warning. * config/mips/loongsson-mmiintrin.h: ... here. * config/mips/mips.c (mips_hard_regno_mode_ok_uncached, mips_vector_mode_supported_p, AVAIL_NON_MIPS16): Use TARGET_LOONGSON_MMI instead of TARGET_LOONGSON_VECTORS. (mips_option_override): Make sure MMI use hard float; Default enable MMI on Loongson 2e/2f/3a. (mips_shift_truncation_mask, mips_expand_vpc_loongson_even_odd, mips_expand_vpc_loongson_pshufh, mips_expand_vpc_loongson_bcast, mips_expand_vector_init): Use TARGET_LOONGSON_MMI instead of TARGET_LOONGSON_VECTORS. * gcc/config/mips/mips.h (TARGET_LOONGSON_VECTORS): Delete. (TARGET_CPU_CPP_BUILTINS): Add __mips_loongson_mmi. (SHIFT_COUNT_TRUNCATED): Use TARGET_LOONGSON_MMI instead of TARGET_LOONGSON_VECTORS. * gcc/config/mips/mips.md (MOVE64, MOVE128): Use TARGET_LOONGSON_MMI instead of TARGET_LOONGSON_VECTORS. (Loongson MMI patterns): Include loongson-mmi.md instead of loongson.md. * gcc/config/mips/mips.opt: New option -mloongson-mmi. gcc/testsuite/ * gcc.target/mips/loongson-shift-count-truncated-1.c (dg-options): Run under -mloongson-mmi option. Include loongson-mmiintrin.h instead of loongson.h. * gcc.target/mips/loongson-simd.c: Likewise. * gcc.target/mips/mips.exp (mips_option_groups): Add -mloongson-mmi option. (mips-dg-init): Add -mloongson-mmi option. * gcc.target/mips/umips-store16-1.c (dg-options): Add forbid_cpu=loongson3a. * lib/target-supports.exp: Rename check_mips_loongson_hw_available to check_mips_loongson_mmi_hw_available. Rename check_effective_target_mips_loongson_runtime to check_effective_target_mips_loongson_mmi_runtime. (check_effective_target_vect_int): Use mips_loongson_mmi instead of mips_loongson when check et-is-effective-target. (add_options_for_mips_loongson_mmi): New proc. Rename check_effective_target_mips_loongson to check_effective_target_mips_loongson_mmi. (check_effective_target_vect_shift, check_effective_target_whole_vector_shift, check_effective_target_vect_no_int_min_max, check_effective_target_vect_no_align, check_effective_target_vect_short_mult, check_vect_support_and_set_flags):Use mips_loongson_mmi instead of mips_loongson when check et-is-effective-target. --- gcc/config.gcc | 2 +- gcc/config/mips/loongson-mmi.md | 903 +++++++++++++++++++ gcc/config/mips/loongson-mmiintrin.h | 691 +++++++++++++++ gcc/config/mips/loongson.h | 669 +-------------- gcc/config/mips/loongson.md | 904 -------------------- gcc/config/mips/mips.c | 34 +- gcc/config/mips/mips.h | 21 +- gcc/config/mips/mips.md | 16 +- gcc/config/mips/mips.opt | 4 + .../mips/loongson-shift-count-truncated-1.c | 6 +- gcc/testsuite/gcc.target/mips/loongson-simd.c | 4 +- gcc/testsuite/gcc.target/mips/mips.exp | 7 + gcc/testsuite/gcc.target/mips/umips-store16-1.c | 2 +- gcc/testsuite/lib/target-supports.exp | 47 +- 14 files changed, 1689 insertions(+), 1621 deletions(-) create mode 100644 gcc/config/mips/loongson-mmi.md create mode 100644 gcc/config/mips/loongson-mmiintrin.h delete mode 100644 gcc/config/mips/loongson.md diff --git a/gcc/config.gcc b/gcc/config.gcc index f81cf76..cd931a6 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -441,7 +441,7 @@ microblaze*-*-*) ;; mips*-*-*) cpu_type=mips - extra_headers="loongson.h msa.h" + extra_headers="loongson.h loongson-mmiintrin.h msa.h" extra_objs="frame-header-opt.o" extra_options="${extra_options} g.opt fused-madd.opt mips/mips-tables.opt" ;; diff --git a/gcc/config/mips/loongson-mmi.md b/gcc/config/mips/loongson-mmi.md new file mode 100644 index 0000000..ad23f67 --- /dev/null +++ b/gcc/config/mips/loongson-mmi.md @@ -0,0 +1,903 @@ +;; Machine description for Loongson MultiMedia extensions Instructions (MMI). +;; Copyright (C) 2008-2018 Free Software Foundation, Inc. +;; Contributed by CodeSourcery. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. + +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +(define_c_enum "unspec" [ + UNSPEC_LOONGSON_PAVG + UNSPEC_LOONGSON_PCMPEQ + UNSPEC_LOONGSON_PCMPGT + UNSPEC_LOONGSON_PEXTR + UNSPEC_LOONGSON_PINSRH + UNSPEC_LOONGSON_VINIT + UNSPEC_LOONGSON_PMADD + UNSPEC_LOONGSON_PMOVMSK + UNSPEC_LOONGSON_PMULHU + UNSPEC_LOONGSON_PMULH + UNSPEC_LOONGSON_PMULU + UNSPEC_LOONGSON_PASUBUB + UNSPEC_LOONGSON_BIADD + UNSPEC_LOONGSON_PSADBH + UNSPEC_LOONGSON_PSHUFH + UNSPEC_LOONGSON_PUNPCKH + UNSPEC_LOONGSON_PUNPCKL + UNSPEC_LOONGSON_PADDD + UNSPEC_LOONGSON_PSUBD + UNSPEC_LOONGSON_DSLL + UNSPEC_LOONGSON_DSRL +]) + +;; Mode iterators and attributes. + +;; 64-bit vectors of bytes. +(define_mode_iterator VB [V8QI]) + +;; 64-bit vectors of halfwords. +(define_mode_iterator VH [V4HI]) + +;; 64-bit vectors of words. +(define_mode_iterator VW [V2SI]) + +;; 64-bit vectors of halfwords and bytes. +(define_mode_iterator VHB [V4HI V8QI]) + +;; 64-bit vectors of words and halfwords. +(define_mode_iterator VWH [V2SI V4HI]) + +;; 64-bit vectors of words and bytes +(define_mode_iterator VWB [V2SI V8QI]) + +;; 64-bit vectors of words, halfwords and bytes. +(define_mode_iterator VWHB [V2SI V4HI V8QI]) + +;; 64-bit vectors of words, halfwords and bytes; and DImode. +(define_mode_iterator VWHBDI [V2SI V4HI V8QI DI]) + +;; The Loongson instruction suffixes corresponding to the modes in the +;; VWHBDI iterator. +(define_mode_attr V_suffix [(V2SI "w") (V4HI "h") (V8QI "b") (DI "d")]) + +;; Given a vector type T, the mode of a vector half the size of T +;; and with the same number of elements. +(define_mode_attr V_squash [(V2SI "V2HI") (V4HI "V4QI")]) + +;; Given a vector type T, the mode of a vector the same size as T +;; but with half as many elements. +(define_mode_attr V_stretch_half [(V2SI "DI") (V4HI "V2SI") (V8QI "V4HI")]) + +;; The Loongson instruction suffixes corresponding to the transformation +;; expressed by V_stretch_half. +(define_mode_attr V_stretch_half_suffix [(V2SI "wd") (V4HI "hw") (V8QI "bh")]) + +;; Given a vector type T, the mode of a vector the same size as T +;; but with twice as many elements. +(define_mode_attr V_squash_double [(V2SI "V4HI") (V4HI "V8QI")]) + +;; Given a vector type T, the inner mode. +(define_mode_attr V_inner [(V8QI "QI") (V4HI "HI") (V2SI "SI")]) + +;; The Loongson instruction suffixes corresponding to the conversions +;; specified by V_half_width. +(define_mode_attr V_squash_double_suffix [(V2SI "wh") (V4HI "hb")]) + +;; Move patterns. + +;; Expander to legitimize moves involving values of vector modes. +(define_expand "mov" + [(set (match_operand:VWHB 0) + (match_operand:VWHB 1))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" +{ + if (mips_legitimize_move (mode, operands[0], operands[1])) + DONE; +}) + +;; Handle legitimized moves between values of vector modes. +(define_insn "mov_internal" + [(set (match_operand:VWHB 0 "nonimmediate_operand" "=m,f,d,f, d, m, d") + (match_operand:VWHB 1 "move_operand" "f,m,f,dYG,dYG,dYG,m"))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + { return mips_output_move (operands[0], operands[1]); } + [(set_attr "move_type" "fpstore,fpload,mfc,mtc,move,store,load") + (set_attr "mode" "DI")]) + +;; Initialization of a vector. + +(define_expand "vec_init" + [(set (match_operand:VWHB 0 "register_operand") + (match_operand 1 ""))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" +{ + mips_expand_vector_init (operands[0], operands[1]); + DONE; +}) + +;; Helper for vec_init. Initialize element 0 of the output from the input. +;; All other elements are undefined. +(define_insn "loongson_vec_init1_" + [(set (match_operand:VHB 0 "register_operand" "=f") + (unspec:VHB [(truncate: + (match_operand:DI 1 "reg_or_0_operand" "Jd"))] + UNSPEC_LOONGSON_VINIT))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "dmtc1\t%z1,%0" + [(set_attr "move_type" "mtc") + (set_attr "mode" "DI")]) + +;; Helper for vec_initv2si. +(define_insn "*vec_concatv2si" + [(set (match_operand:V2SI 0 "register_operand" "=f") + (vec_concat:V2SI + (match_operand:SI 1 "register_operand" "f") + (match_operand:SI 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "punpcklwd\t%0,%1,%2" + [(set_attr "type" "fcvt")]) + +;; Instruction patterns for SIMD instructions. + +;; Pack with signed saturation. +(define_insn "vec_pack_ssat_" + [(set (match_operand: 0 "register_operand" "=f") + (vec_concat: + (ss_truncate: + (match_operand:VWH 1 "register_operand" "f")) + (ss_truncate: + (match_operand:VWH 2 "register_operand" "f"))))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "packss\t%0,%1,%2" + [(set_attr "type" "fmul")]) + +;; Pack with unsigned saturation. +(define_insn "vec_pack_usat_" + [(set (match_operand: 0 "register_operand" "=f") + (vec_concat: + (us_truncate: + (match_operand:VH 1 "register_operand" "f")) + (us_truncate: + (match_operand:VH 2 "register_operand" "f"))))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "packus\t%0,%1,%2" + [(set_attr "type" "fmul")]) + +;; Addition, treating overflow by wraparound. +(define_insn "add3" + [(set (match_operand:VWHB 0 "register_operand" "=f") + (plus:VWHB (match_operand:VWHB 1 "register_operand" "f") + (match_operand:VWHB 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "padd\t%0,%1,%2" + [(set_attr "type" "fadd")]) + +;; Addition of doubleword integers stored in FP registers. +;; Overflow is treated by wraparound. +;; We use 'unspec' instead of 'plus' here to avoid clash with +;; mips.md::add3. If 'plus' was used, then such instruction +;; would be recognized as adddi3 and reload would make it use +;; GPRs instead of FPRs. +(define_insn "loongson_paddd" + [(set (match_operand:DI 0 "register_operand" "=f") + (unspec:DI [(match_operand:DI 1 "register_operand" "f") + (match_operand:DI 2 "register_operand" "f")] + UNSPEC_LOONGSON_PADDD))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "paddd\t%0,%1,%2" + [(set_attr "type" "fadd")]) + +;; Addition, treating overflow by signed saturation. +(define_insn "ssadd3" + [(set (match_operand:VHB 0 "register_operand" "=f") + (ss_plus:VHB (match_operand:VHB 1 "register_operand" "f") + (match_operand:VHB 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "padds\t%0,%1,%2" + [(set_attr "type" "fadd")]) + +;; Addition, treating overflow by unsigned saturation. +(define_insn "usadd3" + [(set (match_operand:VHB 0 "register_operand" "=f") + (us_plus:VHB (match_operand:VHB 1 "register_operand" "f") + (match_operand:VHB 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "paddus\t%0,%1,%2" + [(set_attr "type" "fadd")]) + +;; Logical AND NOT. +(define_insn "loongson_pandn_" + [(set (match_operand:VWHBDI 0 "register_operand" "=f") + (and:VWHBDI + (not:VWHBDI (match_operand:VWHBDI 1 "register_operand" "f")) + (match_operand:VWHBDI 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "pandn\t%0,%1,%2" + [(set_attr "type" "fmul")]) + +;; Logical AND. +(define_insn "and3" + [(set (match_operand:VWHB 0 "register_operand" "=f") + (and:VWHB (match_operand:VWHB 1 "register_operand" "f") + (match_operand:VWHB 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "and\t%0,%1,%2" + [(set_attr "type" "fmul")]) + +;; Logical OR. +(define_insn "ior3" + [(set (match_operand:VWHB 0 "register_operand" "=f") + (ior:VWHB (match_operand:VWHB 1 "register_operand" "f") + (match_operand:VWHB 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "or\t%0,%1,%2" + [(set_attr "type" "fcvt")]) + +;; Logical XOR. +(define_insn "xor3" + [(set (match_operand:VWHB 0 "register_operand" "=f") + (xor:VWHB (match_operand:VWHB 1 "register_operand" "f") + (match_operand:VWHB 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "xor\t%0,%1,%2" + [(set_attr "type" "fmul")]) + +;; Logical NOR. +(define_insn "*loongson_nor" + [(set (match_operand:VWHB 0 "register_operand" "=f") + (and:VWHB + (not:VWHB (match_operand:VWHB 1 "register_operand" "f")) + (not:VWHB (match_operand:VWHB 2 "register_operand" "f"))))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "nor\t%0,%1,%2" + [(set_attr "type" "fmul")]) + +;; Logical NOT. +(define_insn "one_cmpl2" + [(set (match_operand:VWHB 0 "register_operand" "=f") + (not:VWHB (match_operand:VWHB 1 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "nor\t%0,%1,%1" + [(set_attr "type" "fmul")]) + +;; Average. +(define_insn "loongson_pavg" + [(set (match_operand:VHB 0 "register_operand" "=f") + (unspec:VHB [(match_operand:VHB 1 "register_operand" "f") + (match_operand:VHB 2 "register_operand" "f")] + UNSPEC_LOONGSON_PAVG))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "pavg\t%0,%1,%2" + [(set_attr "type" "fadd")]) + +;; Equality test. +(define_insn "loongson_pcmpeq" + [(set (match_operand:VWHB 0 "register_operand" "=f") + (unspec:VWHB [(match_operand:VWHB 1 "register_operand" "f") + (match_operand:VWHB 2 "register_operand" "f")] + UNSPEC_LOONGSON_PCMPEQ))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "pcmpeq\t%0,%1,%2" + [(set_attr "type" "fadd")]) + +;; Greater-than test. +(define_insn "loongson_pcmpgt" + [(set (match_operand:VWHB 0 "register_operand" "=f") + (unspec:VWHB [(match_operand:VWHB 1 "register_operand" "f") + (match_operand:VWHB 2 "register_operand" "f")] + UNSPEC_LOONGSON_PCMPGT))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "pcmpgt\t%0,%1,%2" + [(set_attr "type" "fadd")]) + +;; Extract halfword. +(define_insn "loongson_pextrh" + [(set (match_operand:V4HI 0 "register_operand" "=f") + (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "f") + (match_operand:SI 2 "register_operand" "f")] + UNSPEC_LOONGSON_PEXTR))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "pextrh\t%0,%1,%2" + [(set_attr "type" "fcvt")]) + +;; Insert halfword. +(define_insn "loongson_pinsrh_0" + [(set (match_operand:V4HI 0 "register_operand" "=f") + (vec_select:V4HI + (vec_concat:V8HI + (match_operand:V4HI 1 "register_operand" "f") + (match_operand:V4HI 2 "register_operand" "f")) + (parallel [(const_int 4) (const_int 1) + (const_int 2) (const_int 3)])))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "pinsrh_0\t%0,%1,%2" + [(set_attr "type" "fdiv")]) + +(define_insn "loongson_pinsrh_1" + [(set (match_operand:V4HI 0 "register_operand" "=f") + (vec_select:V4HI + (vec_concat:V8HI + (match_operand:V4HI 1 "register_operand" "f") + (match_operand:V4HI 2 "register_operand" "f")) + (parallel [(const_int 0) (const_int 4) + (const_int 2) (const_int 3)])))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "pinsrh_1\t%0,%1,%2" + [(set_attr "type" "fdiv")]) + +(define_insn "loongson_pinsrh_2" + [(set (match_operand:V4HI 0 "register_operand" "=f") + (vec_select:V4HI + (vec_concat:V8HI + (match_operand:V4HI 1 "register_operand" "f") + (match_operand:V4HI 2 "register_operand" "f")) + (parallel [(const_int 0) (const_int 1) + (const_int 4) (const_int 3)])))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "pinsrh_2\t%0,%1,%2" + [(set_attr "type" "fdiv")]) + +(define_insn "loongson_pinsrh_3" + [(set (match_operand:V4HI 0 "register_operand" "=f") + (vec_select:V4HI + (vec_concat:V8HI + (match_operand:V4HI 1 "register_operand" "f") + (match_operand:V4HI 2 "register_operand" "f")) + (parallel [(const_int 0) (const_int 1) + (const_int 2) (const_int 4)])))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "pinsrh_3\t%0,%1,%2" + [(set_attr "type" "fdiv")]) + +(define_insn "*vec_setv4hi" + [(set (match_operand:V4HI 0 "register_operand" "=f") + (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "f") + (match_operand:SI 2 "register_operand" "f") + (match_operand:SI 3 "const_0_to_3_operand" "")] + UNSPEC_LOONGSON_PINSRH))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "pinsrh_%3\t%0,%1,%2" + [(set_attr "type" "fdiv")]) + +(define_expand "vec_setv4hi" + [(set (match_operand:V4HI 0 "register_operand" "=f") + (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "f") + (match_operand:HI 2 "register_operand" "f") + (match_operand:SI 3 "const_0_to_3_operand" "")] + UNSPEC_LOONGSON_PINSRH))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" +{ + rtx ext = gen_reg_rtx (SImode); + emit_move_insn (ext, gen_lowpart (SImode, operands[2])); + operands[2] = ext; +}) + +;; Multiply and add packed integers. +(define_insn "loongson_pmaddhw" + [(set (match_operand:V2SI 0 "register_operand" "=f") + (unspec:V2SI [(match_operand:V4HI 1 "register_operand" "f") + (match_operand:V4HI 2 "register_operand" "f")] + UNSPEC_LOONGSON_PMADD))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "pmaddhw\t%0,%1,%2" + [(set_attr "type" "fmul")]) + +(define_expand "sdot_prodv4hi" + [(match_operand:V2SI 0 "register_operand" "") + (match_operand:V4HI 1 "register_operand" "") + (match_operand:V4HI 2 "register_operand" "") + (match_operand:V2SI 3 "register_operand" "")] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" +{ + rtx t = gen_reg_rtx (V2SImode); + emit_insn (gen_loongson_pmaddhw (t, operands[1], operands[2])); + emit_insn (gen_addv2si3 (operands[0], t, operands[3])); + DONE; +}) + +;; Maximum of signed halfwords. +(define_insn "smaxv4hi3" + [(set (match_operand:V4HI 0 "register_operand" "=f") + (smax:V4HI (match_operand:V4HI 1 "register_operand" "f") + (match_operand:V4HI 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "pmaxsh\t%0,%1,%2" + [(set_attr "type" "fadd")]) + +(define_expand "smax3" + [(match_operand:VWB 0 "register_operand" "") + (match_operand:VWB 1 "register_operand" "") + (match_operand:VWB 2 "register_operand" "")] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" +{ + mips_expand_vec_minmax (operands[0], operands[1], operands[2], + gen_loongson_pcmpgt, false); + DONE; +}) + +;; Maximum of unsigned bytes. +(define_insn "umaxv8qi3" + [(set (match_operand:V8QI 0 "register_operand" "=f") + (umax:V8QI (match_operand:V8QI 1 "register_operand" "f") + (match_operand:V8QI 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "pmaxub\t%0,%1,%2" + [(set_attr "type" "fadd")]) + +;; Minimum of signed halfwords. +(define_insn "sminv4hi3" + [(set (match_operand:V4HI 0 "register_operand" "=f") + (smin:V4HI (match_operand:V4HI 1 "register_operand" "f") + (match_operand:V4HI 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "pminsh\t%0,%1,%2" + [(set_attr "type" "fadd")]) + +(define_expand "smin3" + [(match_operand:VWB 0 "register_operand" "") + (match_operand:VWB 1 "register_operand" "") + (match_operand:VWB 2 "register_operand" "")] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" +{ + mips_expand_vec_minmax (operands[0], operands[1], operands[2], + gen_loongson_pcmpgt, true); + DONE; +}) + +;; Minimum of unsigned bytes. +(define_insn "uminv8qi3" + [(set (match_operand:V8QI 0 "register_operand" "=f") + (umin:V8QI (match_operand:V8QI 1 "register_operand" "f") + (match_operand:V8QI 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "pminub\t%0,%1,%2" + [(set_attr "type" "fadd")]) + +;; Move byte mask. +(define_insn "loongson_pmovmsk" + [(set (match_operand:VB 0 "register_operand" "=f") + (unspec:VB [(match_operand:VB 1 "register_operand" "f")] + UNSPEC_LOONGSON_PMOVMSK))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "pmovmsk\t%0,%1" + [(set_attr "type" "fabs")]) + +;; Multiply unsigned integers and store high result. +(define_insn "umul3_highpart" + [(set (match_operand:VH 0 "register_operand" "=f") + (unspec:VH [(match_operand:VH 1 "register_operand" "f") + (match_operand:VH 2 "register_operand" "f")] + UNSPEC_LOONGSON_PMULHU))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "pmulhu\t%0,%1,%2" + [(set_attr "type" "fmul")]) + +;; Multiply signed integers and store high result. +(define_insn "smul3_highpart" + [(set (match_operand:VH 0 "register_operand" "=f") + (unspec:VH [(match_operand:VH 1 "register_operand" "f") + (match_operand:VH 2 "register_operand" "f")] + UNSPEC_LOONGSON_PMULH))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "pmulh\t%0,%1,%2" + [(set_attr "type" "fmul")]) + +;; Multiply signed integers and store low result. +(define_insn "mul3" + [(set (match_operand:VH 0 "register_operand" "=f") + (mult:VH (match_operand:VH 1 "register_operand" "f") + (match_operand:VH 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "pmull\t%0,%1,%2" + [(set_attr "type" "fmul")]) + +;; Multiply unsigned word integers. +(define_insn "loongson_pmulu" + [(set (match_operand:DI 0 "register_operand" "=f") + (unspec:DI [(match_operand:VW 1 "register_operand" "f") + (match_operand:VW 2 "register_operand" "f")] + UNSPEC_LOONGSON_PMULU))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "pmulu\t%0,%1,%2" + [(set_attr "type" "fmul")]) + +;; Absolute difference. +(define_insn "loongson_pasubub" + [(set (match_operand:VB 0 "register_operand" "=f") + (unspec:VB [(match_operand:VB 1 "register_operand" "f") + (match_operand:VB 2 "register_operand" "f")] + UNSPEC_LOONGSON_PASUBUB))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "pasubub\t%0,%1,%2" + [(set_attr "type" "fadd")]) + +;; Sum of unsigned byte integers. +(define_insn "loongson_biadd" + [(set (match_operand: 0 "register_operand" "=f") + (unspec: [(match_operand:VB 1 "register_operand" "f")] + UNSPEC_LOONGSON_BIADD))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "biadd\t%0,%1" + [(set_attr "type" "fabs")]) + +(define_insn "reduc_uplus_v8qi" + [(set (match_operand:V8QI 0 "register_operand" "=f") + (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "f")] + UNSPEC_LOONGSON_BIADD))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "biadd\t%0,%1" + [(set_attr "type" "fabs")]) + +;; Sum of absolute differences. +(define_insn "loongson_psadbh" + [(set (match_operand: 0 "register_operand" "=f") + (unspec: [(match_operand:VB 1 "register_operand" "f") + (match_operand:VB 2 "register_operand" "f")] + UNSPEC_LOONGSON_PSADBH))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "pasubub\t%0,%1,%2;biadd\t%0,%0" + [(set_attr "type" "fadd")]) + +;; Shuffle halfwords. +(define_insn "loongson_pshufh" + [(set (match_operand:VH 0 "register_operand" "=f") + (unspec:VH [(match_operand:VH 1 "register_operand" "f") + (match_operand:SI 2 "register_operand" "f")] + UNSPEC_LOONGSON_PSHUFH))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "pshufh\t%0,%1,%2" + [(set_attr "type" "fmul")]) + +;; Shift left logical. +(define_insn "ashl3" + [(set (match_operand:VWH 0 "register_operand" "=f") + (ashift:VWH (match_operand:VWH 1 "register_operand" "f") + (match_operand:SI 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "psll\t%0,%1,%2" + [(set_attr "type" "fcvt")]) + +;; Shift right arithmetic. +(define_insn "ashr3" + [(set (match_operand:VWH 0 "register_operand" "=f") + (ashiftrt:VWH (match_operand:VWH 1 "register_operand" "f") + (match_operand:SI 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "psra\t%0,%1,%2" + [(set_attr "type" "fcvt")]) + +;; Shift right logical. +(define_insn "lshr3" + [(set (match_operand:VWH 0 "register_operand" "=f") + (lshiftrt:VWH (match_operand:VWH 1 "register_operand" "f") + (match_operand:SI 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "psrl\t%0,%1,%2" + [(set_attr "type" "fcvt")]) + +;; Subtraction, treating overflow by wraparound. +(define_insn "sub3" + [(set (match_operand:VWHB 0 "register_operand" "=f") + (minus:VWHB (match_operand:VWHB 1 "register_operand" "f") + (match_operand:VWHB 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "psub\t%0,%1,%2" + [(set_attr "type" "fadd")]) + +;; Subtraction of doubleword integers stored in FP registers. +;; Overflow is treated by wraparound. +;; See loongson_paddd for the reason we use 'unspec' rather than +;; 'minus' here. +(define_insn "loongson_psubd" + [(set (match_operand:DI 0 "register_operand" "=f") + (unspec:DI [(match_operand:DI 1 "register_operand" "f") + (match_operand:DI 2 "register_operand" "f")] + UNSPEC_LOONGSON_PSUBD))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "psubd\t%0,%1,%2" + [(set_attr "type" "fadd")]) + +;; Subtraction, treating overflow by signed saturation. +(define_insn "sssub3" + [(set (match_operand:VHB 0 "register_operand" "=f") + (ss_minus:VHB (match_operand:VHB 1 "register_operand" "f") + (match_operand:VHB 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "psubs\t%0,%1,%2" + [(set_attr "type" "fadd")]) + +;; Subtraction, treating overflow by unsigned saturation. +(define_insn "ussub3" + [(set (match_operand:VHB 0 "register_operand" "=f") + (us_minus:VHB (match_operand:VHB 1 "register_operand" "f") + (match_operand:VHB 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "psubus\t%0,%1,%2" + [(set_attr "type" "fadd")]) + +;; Unpack high data. Recall that Loongson only runs in little-endian. +(define_insn "loongson_punpckhbh" + [(set (match_operand:V8QI 0 "register_operand" "=f") + (vec_select:V8QI + (vec_concat:V16QI + (match_operand:V8QI 1 "register_operand" "f") + (match_operand:V8QI 2 "register_operand" "f")) + (parallel [(const_int 4) (const_int 12) + (const_int 5) (const_int 13) + (const_int 6) (const_int 14) + (const_int 7) (const_int 15)])))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "punpckhbh\t%0,%1,%2" + [(set_attr "type" "fdiv")]) + +(define_insn "loongson_punpckhhw" + [(set (match_operand:V4HI 0 "register_operand" "=f") + (vec_select:V4HI + (vec_concat:V8HI + (match_operand:V4HI 1 "register_operand" "f") + (match_operand:V4HI 2 "register_operand" "f")) + (parallel [(const_int 2) (const_int 6) + (const_int 3) (const_int 7)])))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "punpckhhw\t%0,%1,%2" + [(set_attr "type" "fdiv")]) + +(define_insn "loongson_punpckhhw_qi" + [(set (match_operand:V8QI 0 "register_operand" "=f") + (vec_select:V8QI + (vec_concat:V16QI + (match_operand:V8QI 1 "register_operand" "f") + (match_operand:V8QI 2 "register_operand" "f")) + (parallel [(const_int 4) (const_int 5) + (const_int 12) (const_int 13) + (const_int 6) (const_int 7) + (const_int 14) (const_int 15)])))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "punpckhhw\t%0,%1,%2" + [(set_attr "type" "fdiv")]) + +(define_insn "loongson_punpckhwd" + [(set (match_operand:V2SI 0 "register_operand" "=f") + (vec_select:V2SI + (vec_concat:V4SI + (match_operand:V2SI 1 "register_operand" "f") + (match_operand:V2SI 2 "register_operand" "f")) + (parallel [(const_int 1) (const_int 3)])))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "punpckhwd\t%0,%1,%2" + [(set_attr "type" "fcvt")]) + +(define_insn "loongson_punpckhwd_qi" + [(set (match_operand:V8QI 0 "register_operand" "=f") + (vec_select:V8QI + (vec_concat:V16QI + (match_operand:V8QI 1 "register_operand" "f") + (match_operand:V8QI 2 "register_operand" "f")) + (parallel [(const_int 4) (const_int 5) + (const_int 6) (const_int 7) + (const_int 12) (const_int 13) + (const_int 14) (const_int 15)])))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "punpckhwd\t%0,%1,%2" + [(set_attr "type" "fcvt")]) + +(define_insn "loongson_punpckhwd_hi" + [(set (match_operand:V4HI 0 "register_operand" "=f") + (vec_select:V4HI + (vec_concat:V8HI + (match_operand:V4HI 1 "register_operand" "f") + (match_operand:V4HI 2 "register_operand" "f")) + (parallel [(const_int 2) (const_int 3) + (const_int 6) (const_int 7)])))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "punpckhwd\t%0,%1,%2" + [(set_attr "type" "fcvt")]) + +;; Unpack low data. +(define_insn "loongson_punpcklbh" + [(set (match_operand:V8QI 0 "register_operand" "=f") + (vec_select:V8QI + (vec_concat:V16QI + (match_operand:V8QI 1 "register_operand" "f") + (match_operand:V8QI 2 "register_operand" "f")) + (parallel [(const_int 0) (const_int 8) + (const_int 1) (const_int 9) + (const_int 2) (const_int 10) + (const_int 3) (const_int 11)])))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "punpcklbh\t%0,%1,%2" + [(set_attr "type" "fdiv")]) + +(define_insn "loongson_punpcklhw" + [(set (match_operand:V4HI 0 "register_operand" "=f") + (vec_select:V4HI + (vec_concat:V8HI + (match_operand:V4HI 1 "register_operand" "f") + (match_operand:V4HI 2 "register_operand" "f")) + (parallel [(const_int 0) (const_int 4) + (const_int 1) (const_int 5)])))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "punpcklhw\t%0,%1,%2" + [(set_attr "type" "fdiv")]) + +(define_insn "*loongson_punpcklhw_qi" + [(set (match_operand:V8QI 0 "register_operand" "=f") + (vec_select:V8QI + (vec_concat:V16QI + (match_operand:V8QI 1 "register_operand" "f") + (match_operand:V8QI 2 "register_operand" "f")) + (parallel [(const_int 0) (const_int 1) + (const_int 8) (const_int 9) + (const_int 2) (const_int 3) + (const_int 10) (const_int 11)])))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "punpcklhw\t%0,%1,%2" + [(set_attr "type" "fdiv")]) + +(define_insn "loongson_punpcklwd" + [(set (match_operand:V2SI 0 "register_operand" "=f") + (vec_select:V2SI + (vec_concat:V4SI + (match_operand:V2SI 1 "register_operand" "f") + (match_operand:V2SI 2 "register_operand" "f")) + (parallel [(const_int 0) (const_int 2)])))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "punpcklwd\t%0,%1,%2" + [(set_attr "type" "fcvt")]) + +(define_insn "*loongson_punpcklwd_qi" + [(set (match_operand:V8QI 0 "register_operand" "=f") + (vec_select:V8QI + (vec_concat:V16QI + (match_operand:V8QI 1 "register_operand" "f") + (match_operand:V8QI 2 "register_operand" "f")) + (parallel [(const_int 0) (const_int 1) + (const_int 2) (const_int 3) + (const_int 8) (const_int 9) + (const_int 10) (const_int 11)])))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "punpcklwd\t%0,%1,%2" + [(set_attr "type" "fcvt")]) + +(define_insn "*loongson_punpcklwd_hi" + [(set (match_operand:V4HI 0 "register_operand" "=f") + (vec_select:V4HI + (vec_concat:V8HI + (match_operand:V4HI 1 "register_operand" "f") + (match_operand:V4HI 2 "register_operand" "f")) + (parallel [(const_int 0) (const_int 1) + (const_int 4) (const_int 5)])))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "punpcklwd\t%0,%1,%2" + [(set_attr "type" "fcvt")]) + +(define_expand "vec_unpacks_lo_" + [(match_operand: 0 "register_operand" "") + (match_operand:VHB 1 "register_operand" "")] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" +{ + mips_expand_vec_unpack (operands, false, false); + DONE; +}) + +(define_expand "vec_unpacks_hi_" + [(match_operand: 0 "register_operand" "") + (match_operand:VHB 1 "register_operand" "")] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" +{ + mips_expand_vec_unpack (operands, false, true); + DONE; +}) + +(define_expand "vec_unpacku_lo_" + [(match_operand: 0 "register_operand" "") + (match_operand:VHB 1 "register_operand" "")] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" +{ + mips_expand_vec_unpack (operands, true, false); + DONE; +}) + +(define_expand "vec_unpacku_hi_" + [(match_operand: 0 "register_operand" "") + (match_operand:VHB 1 "register_operand" "")] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" +{ + mips_expand_vec_unpack (operands, true, true); + DONE; +}) + +;; Whole vector shifts, used for reduction epilogues. +(define_insn "vec_shl_" + [(set (match_operand:VWHBDI 0 "register_operand" "=f") + (unspec:VWHBDI [(match_operand:VWHBDI 1 "register_operand" "f") + (match_operand:SI 2 "register_operand" "f")] + UNSPEC_LOONGSON_DSLL))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "dsll\t%0,%1,%2" + [(set_attr "type" "fcvt")]) + +(define_insn "vec_shr_" + [(set (match_operand:VWHBDI 0 "register_operand" "=f") + (unspec:VWHBDI [(match_operand:VWHBDI 1 "register_operand" "f") + (match_operand:SI 2 "register_operand" "f")] + UNSPEC_LOONGSON_DSRL))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "dsrl\t%0,%1,%2" + [(set_attr "type" "fcvt")]) + +(define_insn "vec_loongson_extract_lo_" + [(set (match_operand: 0 "register_operand" "=r") + (vec_select: + (match_operand:VWHB 1 "register_operand" "f") + (parallel [(const_int 0)])))] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" + "mfc1\t%0,%1" + [(set_attr "type" "mfc")]) + +(define_expand "reduc_plus_scal_" + [(match_operand: 0 "register_operand" "") + (match_operand:VWHB 1 "register_operand" "")] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" +{ + rtx tmp = gen_reg_rtx (GET_MODE (operands[1])); + mips_expand_vec_reduc (tmp, operands[1], gen_add3); + emit_insn (gen_vec_loongson_extract_lo_ (operands[0], tmp)); + DONE; +}) + +(define_expand "reduc_smax_scal_" + [(match_operand: 0 "register_operand" "") + (match_operand:VWHB 1 "register_operand" "")] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" +{ + rtx tmp = gen_reg_rtx (GET_MODE (operands[1])); + mips_expand_vec_reduc (tmp, operands[1], gen_smax3); + emit_insn (gen_vec_loongson_extract_lo_ (operands[0], tmp)); + DONE; +}) + +(define_expand "reduc_smin_scal_" + [(match_operand: 0 "register_operand" "") + (match_operand:VWHB 1 "register_operand" "")] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" +{ + rtx tmp = gen_reg_rtx (GET_MODE (operands[1])); + mips_expand_vec_reduc (tmp, operands[1], gen_smin3); + emit_insn (gen_vec_loongson_extract_lo_ (operands[0], tmp)); + DONE; +}) + +(define_expand "reduc_umax_scal_" + [(match_operand: 0 "register_operand" "") + (match_operand:VB 1 "register_operand" "")] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" +{ + rtx tmp = gen_reg_rtx (GET_MODE (operands[1])); + mips_expand_vec_reduc (tmp, operands[1], gen_umax3); + emit_insn (gen_vec_loongson_extract_lo_ (operands[0], tmp)); + DONE; +}) + +(define_expand "reduc_umin_scal_" + [(match_operand: 0 "register_operand" "") + (match_operand:VB 1 "register_operand" "")] + "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" +{ + rtx tmp = gen_reg_rtx (GET_MODE (operands[1])); + mips_expand_vec_reduc (tmp, operands[1], gen_umin3); + emit_insn (gen_vec_loongson_extract_lo_ (operands[0], tmp)); + DONE; +}) diff --git a/gcc/config/mips/loongson-mmiintrin.h b/gcc/config/mips/loongson-mmiintrin.h new file mode 100644 index 0000000..6f35fb5 --- /dev/null +++ b/gcc/config/mips/loongson-mmiintrin.h @@ -0,0 +1,691 @@ +/* Intrinsics for Loongson MultiMedia extension Instructions operations. + + Copyright (C) 2008-2018 Free Software Foundation, Inc. + Contributed by CodeSourcery. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + +#ifndef _GCC_LOONGSON_MMIINTRIN_H +#define _GCC_LOONGSON_MMIINTRIN_H + +#if !defined(__mips_loongson_mmi) +# error "You must select -mloongson-mmi or -march=loongson2e/2f/3a to use + loongson-mmiintrin.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* Vectors of unsigned bytes, halfwords and words. */ +typedef uint8_t uint8x8_t __attribute__((vector_size (8))); +typedef uint16_t uint16x4_t __attribute__((vector_size (8))); +typedef uint32_t uint32x2_t __attribute__((vector_size (8))); + +/* Vectors of signed bytes, halfwords and words. */ +typedef int8_t int8x8_t __attribute__((vector_size (8))); +typedef int16_t int16x4_t __attribute__((vector_size (8))); +typedef int32_t int32x2_t __attribute__((vector_size (8))); + +/* SIMD intrinsics. + Unless otherwise noted, calls to the functions below will expand into + precisely one machine instruction, modulo any moves required to + satisfy register allocation constraints. */ + +/* Pack with signed saturation. */ +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +packsswh (int32x2_t s, int32x2_t t) +{ + return __builtin_loongson_packsswh (s, t); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +packsshb (int16x4_t s, int16x4_t t) +{ + return __builtin_loongson_packsshb (s, t); +} + +/* Pack with unsigned saturation. */ +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +packushb (uint16x4_t s, uint16x4_t t) +{ + return __builtin_loongson_packushb (s, t); +} + +/* Vector addition, treating overflow by wraparound. */ +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +paddw_u (uint32x2_t s, uint32x2_t t) +{ + return __builtin_loongson_paddw_u (s, t); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +paddh_u (uint16x4_t s, uint16x4_t t) +{ + return __builtin_loongson_paddh_u (s, t); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +paddb_u (uint8x8_t s, uint8x8_t t) +{ + return __builtin_loongson_paddb_u (s, t); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +paddw_s (int32x2_t s, int32x2_t t) +{ + return __builtin_loongson_paddw_s (s, t); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +paddh_s (int16x4_t s, int16x4_t t) +{ + return __builtin_loongson_paddh_s (s, t); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +paddb_s (int8x8_t s, int8x8_t t) +{ + return __builtin_loongson_paddb_s (s, t); +} + +/* Addition of doubleword integers, treating overflow by wraparound. */ +__extension__ static __inline uint64_t __attribute__ ((__always_inline__)) +paddd_u (uint64_t s, uint64_t t) +{ + return __builtin_loongson_paddd_u (s, t); +} + +__extension__ static __inline int64_t __attribute__ ((__always_inline__)) +paddd_s (int64_t s, int64_t t) +{ + return __builtin_loongson_paddd_s (s, t); +} + +/* Vector addition, treating overflow by signed saturation. */ +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +paddsh (int16x4_t s, int16x4_t t) +{ + return __builtin_loongson_paddsh (s, t); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +paddsb (int8x8_t s, int8x8_t t) +{ + return __builtin_loongson_paddsb (s, t); +} + +/* Vector addition, treating overflow by unsigned saturation. */ +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +paddush (uint16x4_t s, uint16x4_t t) +{ + return __builtin_loongson_paddush (s, t); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +paddusb (uint8x8_t s, uint8x8_t t) +{ + return __builtin_loongson_paddusb (s, t); +} + +/* Logical AND NOT. */ +__extension__ static __inline uint64_t __attribute__ ((__always_inline__)) +pandn_ud (uint64_t s, uint64_t t) +{ + return __builtin_loongson_pandn_ud (s, t); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +pandn_uw (uint32x2_t s, uint32x2_t t) +{ + return __builtin_loongson_pandn_uw (s, t); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +pandn_uh (uint16x4_t s, uint16x4_t t) +{ + return __builtin_loongson_pandn_uh (s, t); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +pandn_ub (uint8x8_t s, uint8x8_t t) +{ + return __builtin_loongson_pandn_ub (s, t); +} + +__extension__ static __inline int64_t __attribute__ ((__always_inline__)) +pandn_sd (int64_t s, int64_t t) +{ + return __builtin_loongson_pandn_sd (s, t); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +pandn_sw (int32x2_t s, int32x2_t t) +{ + return __builtin_loongson_pandn_sw (s, t); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +pandn_sh (int16x4_t s, int16x4_t t) +{ + return __builtin_loongson_pandn_sh (s, t); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +pandn_sb (int8x8_t s, int8x8_t t) +{ + return __builtin_loongson_pandn_sb (s, t); +} + +/* Average. */ +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +pavgh (uint16x4_t s, uint16x4_t t) +{ + return __builtin_loongson_pavgh (s, t); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +pavgb (uint8x8_t s, uint8x8_t t) +{ + return __builtin_loongson_pavgb (s, t); +} + +/* Equality test. */ +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +pcmpeqw_u (uint32x2_t s, uint32x2_t t) +{ + return __builtin_loongson_pcmpeqw_u (s, t); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +pcmpeqh_u (uint16x4_t s, uint16x4_t t) +{ + return __builtin_loongson_pcmpeqh_u (s, t); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +pcmpeqb_u (uint8x8_t s, uint8x8_t t) +{ + return __builtin_loongson_pcmpeqb_u (s, t); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +pcmpeqw_s (int32x2_t s, int32x2_t t) +{ + return __builtin_loongson_pcmpeqw_s (s, t); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +pcmpeqh_s (int16x4_t s, int16x4_t t) +{ + return __builtin_loongson_pcmpeqh_s (s, t); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +pcmpeqb_s (int8x8_t s, int8x8_t t) +{ + return __builtin_loongson_pcmpeqb_s (s, t); +} + +/* Greater-than test. */ +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +pcmpgtw_u (uint32x2_t s, uint32x2_t t) +{ + return __builtin_loongson_pcmpgtw_u (s, t); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +pcmpgth_u (uint16x4_t s, uint16x4_t t) +{ + return __builtin_loongson_pcmpgth_u (s, t); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +pcmpgtb_u (uint8x8_t s, uint8x8_t t) +{ + return __builtin_loongson_pcmpgtb_u (s, t); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +pcmpgtw_s (int32x2_t s, int32x2_t t) +{ + return __builtin_loongson_pcmpgtw_s (s, t); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +pcmpgth_s (int16x4_t s, int16x4_t t) +{ + return __builtin_loongson_pcmpgth_s (s, t); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +pcmpgtb_s (int8x8_t s, int8x8_t t) +{ + return __builtin_loongson_pcmpgtb_s (s, t); +} + +/* Extract halfword. */ +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +pextrh_u (uint16x4_t s, int field /* 0--3. */) +{ + return __builtin_loongson_pextrh_u (s, field); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +pextrh_s (int16x4_t s, int field /* 0--3. */) +{ + return __builtin_loongson_pextrh_s (s, field); +} + +/* Insert halfword. */ +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +pinsrh_0_u (uint16x4_t s, uint16x4_t t) +{ + return __builtin_loongson_pinsrh_0_u (s, t); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +pinsrh_1_u (uint16x4_t s, uint16x4_t t) +{ + return __builtin_loongson_pinsrh_1_u (s, t); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +pinsrh_2_u (uint16x4_t s, uint16x4_t t) +{ + return __builtin_loongson_pinsrh_2_u (s, t); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +pinsrh_3_u (uint16x4_t s, uint16x4_t t) +{ + return __builtin_loongson_pinsrh_3_u (s, t); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +pinsrh_0_s (int16x4_t s, int16x4_t t) +{ + return __builtin_loongson_pinsrh_0_s (s, t); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +pinsrh_1_s (int16x4_t s, int16x4_t t) +{ + return __builtin_loongson_pinsrh_1_s (s, t); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +pinsrh_2_s (int16x4_t s, int16x4_t t) +{ + return __builtin_loongson_pinsrh_2_s (s, t); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +pinsrh_3_s (int16x4_t s, int16x4_t t) +{ + return __builtin_loongson_pinsrh_3_s (s, t); +} + +/* Multiply and add. */ +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +pmaddhw (int16x4_t s, int16x4_t t) +{ + return __builtin_loongson_pmaddhw (s, t); +} + +/* Maximum of signed halfwords. */ +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +pmaxsh (int16x4_t s, int16x4_t t) +{ + return __builtin_loongson_pmaxsh (s, t); +} + +/* Maximum of unsigned bytes. */ +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +pmaxub (uint8x8_t s, uint8x8_t t) +{ + return __builtin_loongson_pmaxub (s, t); +} + +/* Minimum of signed halfwords. */ +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +pminsh (int16x4_t s, int16x4_t t) +{ + return __builtin_loongson_pminsh (s, t); +} + +/* Minimum of unsigned bytes. */ +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +pminub (uint8x8_t s, uint8x8_t t) +{ + return __builtin_loongson_pminub (s, t); +} + +/* Move byte mask. */ +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +pmovmskb_u (uint8x8_t s) +{ + return __builtin_loongson_pmovmskb_u (s); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +pmovmskb_s (int8x8_t s) +{ + return __builtin_loongson_pmovmskb_s (s); +} + +/* Multiply unsigned integers and store high result. */ +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +pmulhuh (uint16x4_t s, uint16x4_t t) +{ + return __builtin_loongson_pmulhuh (s, t); +} + +/* Multiply signed integers and store high result. */ +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +pmulhh (int16x4_t s, int16x4_t t) +{ + return __builtin_loongson_pmulhh (s, t); +} + +/* Multiply signed integers and store low result. */ +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +pmullh (int16x4_t s, int16x4_t t) +{ + return __builtin_loongson_pmullh (s, t); +} + +/* Multiply unsigned word integers. */ +__extension__ static __inline int64_t __attribute__ ((__always_inline__)) +pmuluw (uint32x2_t s, uint32x2_t t) +{ + return __builtin_loongson_pmuluw (s, t); +} + +/* Absolute difference. */ +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +pasubub (uint8x8_t s, uint8x8_t t) +{ + return __builtin_loongson_pasubub (s, t); +} + +/* Sum of unsigned byte integers. */ +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +biadd (uint8x8_t s) +{ + return __builtin_loongson_biadd (s); +} + +/* Sum of absolute differences. + Note that this intrinsic expands into two machine instructions: + PASUBUB followed by BIADD. */ +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +psadbh (uint8x8_t s, uint8x8_t t) +{ + return __builtin_loongson_psadbh (s, t); +} + +/* Shuffle halfwords. */ +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +pshufh_u (uint16x4_t dest, uint16x4_t s, uint8_t order) +{ + return __builtin_loongson_pshufh_u (s, order); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +pshufh_s (int16x4_t dest, int16x4_t s, uint8_t order) +{ + return __builtin_loongson_pshufh_s (s, order); +} + +/* Shift left logical. */ +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +psllh_u (uint16x4_t s, uint8_t amount) +{ + return __builtin_loongson_psllh_u (s, amount); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +psllh_s (int16x4_t s, uint8_t amount) +{ + return __builtin_loongson_psllh_s (s, amount); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +psllw_u (uint32x2_t s, uint8_t amount) +{ + return __builtin_loongson_psllw_u (s, amount); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +psllw_s (int32x2_t s, uint8_t amount) +{ + return __builtin_loongson_psllw_s (s, amount); +} + +/* Shift right logical. */ +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +psrlh_u (uint16x4_t s, uint8_t amount) +{ + return __builtin_loongson_psrlh_u (s, amount); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +psrlh_s (int16x4_t s, uint8_t amount) +{ + return __builtin_loongson_psrlh_s (s, amount); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +psrlw_u (uint32x2_t s, uint8_t amount) +{ + return __builtin_loongson_psrlw_u (s, amount); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +psrlw_s (int32x2_t s, uint8_t amount) +{ + return __builtin_loongson_psrlw_s (s, amount); +} + +/* Shift right arithmetic. */ +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +psrah_u (uint16x4_t s, uint8_t amount) +{ + return __builtin_loongson_psrah_u (s, amount); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +psrah_s (int16x4_t s, uint8_t amount) +{ + return __builtin_loongson_psrah_s (s, amount); +} + +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +psraw_u (uint32x2_t s, uint8_t amount) +{ + return __builtin_loongson_psraw_u (s, amount); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +psraw_s (int32x2_t s, uint8_t amount) +{ + return __builtin_loongson_psraw_s (s, amount); +} + +/* Vector subtraction, treating overflow by wraparound. */ +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +psubw_u (uint32x2_t s, uint32x2_t t) +{ + return __builtin_loongson_psubw_u (s, t); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +psubh_u (uint16x4_t s, uint16x4_t t) +{ + return __builtin_loongson_psubh_u (s, t); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +psubb_u (uint8x8_t s, uint8x8_t t) +{ + return __builtin_loongson_psubb_u (s, t); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +psubw_s (int32x2_t s, int32x2_t t) +{ + return __builtin_loongson_psubw_s (s, t); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +psubh_s (int16x4_t s, int16x4_t t) +{ + return __builtin_loongson_psubh_s (s, t); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +psubb_s (int8x8_t s, int8x8_t t) +{ + return __builtin_loongson_psubb_s (s, t); +} + +/* Subtraction of doubleword integers, treating overflow by wraparound. */ +__extension__ static __inline uint64_t __attribute__ ((__always_inline__)) +psubd_u (uint64_t s, uint64_t t) +{ + return __builtin_loongson_psubd_u (s, t); +} + +__extension__ static __inline int64_t __attribute__ ((__always_inline__)) +psubd_s (int64_t s, int64_t t) +{ + return __builtin_loongson_psubd_s (s, t); +} + +/* Vector subtraction, treating overflow by signed saturation. */ +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +psubsh (int16x4_t s, int16x4_t t) +{ + return __builtin_loongson_psubsh (s, t); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +psubsb (int8x8_t s, int8x8_t t) +{ + return __builtin_loongson_psubsb (s, t); +} + +/* Vector subtraction, treating overflow by unsigned saturation. */ +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +psubush (uint16x4_t s, uint16x4_t t) +{ + return __builtin_loongson_psubush (s, t); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +psubusb (uint8x8_t s, uint8x8_t t) +{ + return __builtin_loongson_psubusb (s, t); +} + +/* Unpack high data. */ +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +punpckhwd_u (uint32x2_t s, uint32x2_t t) +{ + return __builtin_loongson_punpckhwd_u (s, t); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +punpckhhw_u (uint16x4_t s, uint16x4_t t) +{ + return __builtin_loongson_punpckhhw_u (s, t); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +punpckhbh_u (uint8x8_t s, uint8x8_t t) +{ + return __builtin_loongson_punpckhbh_u (s, t); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +punpckhwd_s (int32x2_t s, int32x2_t t) +{ + return __builtin_loongson_punpckhwd_s (s, t); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +punpckhhw_s (int16x4_t s, int16x4_t t) +{ + return __builtin_loongson_punpckhhw_s (s, t); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +punpckhbh_s (int8x8_t s, int8x8_t t) +{ + return __builtin_loongson_punpckhbh_s (s, t); +} + +/* Unpack low data. */ +__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +punpcklwd_u (uint32x2_t s, uint32x2_t t) +{ + return __builtin_loongson_punpcklwd_u (s, t); +} + +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +punpcklhw_u (uint16x4_t s, uint16x4_t t) +{ + return __builtin_loongson_punpcklhw_u (s, t); +} + +__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +punpcklbh_u (uint8x8_t s, uint8x8_t t) +{ + return __builtin_loongson_punpcklbh_u (s, t); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +punpcklwd_s (int32x2_t s, int32x2_t t) +{ + return __builtin_loongson_punpcklwd_s (s, t); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +punpcklhw_s (int16x4_t s, int16x4_t t) +{ + return __builtin_loongson_punpcklhw_s (s, t); +} + +__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +punpcklbh_s (int8x8_t s, int8x8_t t) +{ + return __builtin_loongson_punpcklbh_s (s, t); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/gcc/config/mips/loongson.h b/gcc/config/mips/loongson.h index b4a2602..3880e4c 100644 --- a/gcc/config/mips/loongson.h +++ b/gcc/config/mips/loongson.h @@ -1,4 +1,4 @@ -/* Intrinsics for ST Microelectronics Loongson-2E/2F SIMD operations. +/* Intrinsics for Loongson MultiMedia extension Instructions operations. Copyright (C) 2008-2018 Free Software Foundation, Inc. Contributed by CodeSourcery. @@ -24,667 +24,10 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see . */ -#ifndef _GCC_LOONGSON_H -#define _GCC_LOONGSON_H - -#if !defined(__mips_loongson_vector_rev) -# error "You must select -march=loongson2e or -march=loongson2f to use loongson.h" -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* Vectors of unsigned bytes, halfwords and words. */ -typedef uint8_t uint8x8_t __attribute__((vector_size (8))); -typedef uint16_t uint16x4_t __attribute__((vector_size (8))); -typedef uint32_t uint32x2_t __attribute__((vector_size (8))); - -/* Vectors of signed bytes, halfwords and words. */ -typedef int8_t int8x8_t __attribute__((vector_size (8))); -typedef int16_t int16x4_t __attribute__((vector_size (8))); -typedef int32_t int32x2_t __attribute__((vector_size (8))); - -/* SIMD intrinsics. - Unless otherwise noted, calls to the functions below will expand into - precisely one machine instruction, modulo any moves required to - satisfy register allocation constraints. */ - -/* Pack with signed saturation. */ -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -packsswh (int32x2_t s, int32x2_t t) -{ - return __builtin_loongson_packsswh (s, t); -} - -__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -packsshb (int16x4_t s, int16x4_t t) -{ - return __builtin_loongson_packsshb (s, t); -} - -/* Pack with unsigned saturation. */ -__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -packushb (uint16x4_t s, uint16x4_t t) -{ - return __builtin_loongson_packushb (s, t); -} - -/* Vector addition, treating overflow by wraparound. */ -__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -paddw_u (uint32x2_t s, uint32x2_t t) -{ - return __builtin_loongson_paddw_u (s, t); -} - -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -paddh_u (uint16x4_t s, uint16x4_t t) -{ - return __builtin_loongson_paddh_u (s, t); -} - -__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -paddb_u (uint8x8_t s, uint8x8_t t) -{ - return __builtin_loongson_paddb_u (s, t); -} - -__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -paddw_s (int32x2_t s, int32x2_t t) -{ - return __builtin_loongson_paddw_s (s, t); -} - -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -paddh_s (int16x4_t s, int16x4_t t) -{ - return __builtin_loongson_paddh_s (s, t); -} - -__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -paddb_s (int8x8_t s, int8x8_t t) -{ - return __builtin_loongson_paddb_s (s, t); -} - -/* Addition of doubleword integers, treating overflow by wraparound. */ -__extension__ static __inline uint64_t __attribute__ ((__always_inline__)) -paddd_u (uint64_t s, uint64_t t) -{ - return __builtin_loongson_paddd_u (s, t); -} - -__extension__ static __inline int64_t __attribute__ ((__always_inline__)) -paddd_s (int64_t s, int64_t t) -{ - return __builtin_loongson_paddd_s (s, t); -} - -/* Vector addition, treating overflow by signed saturation. */ -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -paddsh (int16x4_t s, int16x4_t t) -{ - return __builtin_loongson_paddsh (s, t); -} - -__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -paddsb (int8x8_t s, int8x8_t t) -{ - return __builtin_loongson_paddsb (s, t); -} - -/* Vector addition, treating overflow by unsigned saturation. */ -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -paddush (uint16x4_t s, uint16x4_t t) -{ - return __builtin_loongson_paddush (s, t); -} - -__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -paddusb (uint8x8_t s, uint8x8_t t) -{ - return __builtin_loongson_paddusb (s, t); -} - -/* Logical AND NOT. */ -__extension__ static __inline uint64_t __attribute__ ((__always_inline__)) -pandn_ud (uint64_t s, uint64_t t) -{ - return __builtin_loongson_pandn_ud (s, t); -} - -__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -pandn_uw (uint32x2_t s, uint32x2_t t) -{ - return __builtin_loongson_pandn_uw (s, t); -} - -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -pandn_uh (uint16x4_t s, uint16x4_t t) -{ - return __builtin_loongson_pandn_uh (s, t); -} - -__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -pandn_ub (uint8x8_t s, uint8x8_t t) -{ - return __builtin_loongson_pandn_ub (s, t); -} - -__extension__ static __inline int64_t __attribute__ ((__always_inline__)) -pandn_sd (int64_t s, int64_t t) -{ - return __builtin_loongson_pandn_sd (s, t); -} - -__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -pandn_sw (int32x2_t s, int32x2_t t) -{ - return __builtin_loongson_pandn_sw (s, t); -} - -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -pandn_sh (int16x4_t s, int16x4_t t) -{ - return __builtin_loongson_pandn_sh (s, t); -} - -__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -pandn_sb (int8x8_t s, int8x8_t t) -{ - return __builtin_loongson_pandn_sb (s, t); -} - -/* Average. */ -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -pavgh (uint16x4_t s, uint16x4_t t) -{ - return __builtin_loongson_pavgh (s, t); -} - -__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -pavgb (uint8x8_t s, uint8x8_t t) -{ - return __builtin_loongson_pavgb (s, t); -} - -/* Equality test. */ -__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -pcmpeqw_u (uint32x2_t s, uint32x2_t t) -{ - return __builtin_loongson_pcmpeqw_u (s, t); -} - -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -pcmpeqh_u (uint16x4_t s, uint16x4_t t) -{ - return __builtin_loongson_pcmpeqh_u (s, t); -} - -__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -pcmpeqb_u (uint8x8_t s, uint8x8_t t) -{ - return __builtin_loongson_pcmpeqb_u (s, t); -} - -__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -pcmpeqw_s (int32x2_t s, int32x2_t t) -{ - return __builtin_loongson_pcmpeqw_s (s, t); -} - -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -pcmpeqh_s (int16x4_t s, int16x4_t t) -{ - return __builtin_loongson_pcmpeqh_s (s, t); -} - -__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -pcmpeqb_s (int8x8_t s, int8x8_t t) -{ - return __builtin_loongson_pcmpeqb_s (s, t); -} - -/* Greater-than test. */ -__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -pcmpgtw_u (uint32x2_t s, uint32x2_t t) -{ - return __builtin_loongson_pcmpgtw_u (s, t); -} - -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -pcmpgth_u (uint16x4_t s, uint16x4_t t) -{ - return __builtin_loongson_pcmpgth_u (s, t); -} - -__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -pcmpgtb_u (uint8x8_t s, uint8x8_t t) -{ - return __builtin_loongson_pcmpgtb_u (s, t); -} - -__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -pcmpgtw_s (int32x2_t s, int32x2_t t) -{ - return __builtin_loongson_pcmpgtw_s (s, t); -} - -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -pcmpgth_s (int16x4_t s, int16x4_t t) -{ - return __builtin_loongson_pcmpgth_s (s, t); -} - -__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -pcmpgtb_s (int8x8_t s, int8x8_t t) -{ - return __builtin_loongson_pcmpgtb_s (s, t); -} - -/* Extract halfword. */ -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -pextrh_u (uint16x4_t s, int field /* 0--3 */) -{ - return __builtin_loongson_pextrh_u (s, field); -} - -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -pextrh_s (int16x4_t s, int field /* 0--3 */) -{ - return __builtin_loongson_pextrh_s (s, field); -} - -/* Insert halfword. */ -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -pinsrh_0_u (uint16x4_t s, uint16x4_t t) -{ - return __builtin_loongson_pinsrh_0_u (s, t); -} - -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -pinsrh_1_u (uint16x4_t s, uint16x4_t t) -{ - return __builtin_loongson_pinsrh_1_u (s, t); -} - -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -pinsrh_2_u (uint16x4_t s, uint16x4_t t) -{ - return __builtin_loongson_pinsrh_2_u (s, t); -} - -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -pinsrh_3_u (uint16x4_t s, uint16x4_t t) -{ - return __builtin_loongson_pinsrh_3_u (s, t); -} - -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -pinsrh_0_s (int16x4_t s, int16x4_t t) -{ - return __builtin_loongson_pinsrh_0_s (s, t); -} - -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -pinsrh_1_s (int16x4_t s, int16x4_t t) -{ - return __builtin_loongson_pinsrh_1_s (s, t); -} - -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -pinsrh_2_s (int16x4_t s, int16x4_t t) -{ - return __builtin_loongson_pinsrh_2_s (s, t); -} - -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -pinsrh_3_s (int16x4_t s, int16x4_t t) -{ - return __builtin_loongson_pinsrh_3_s (s, t); -} - -/* Multiply and add. */ -__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -pmaddhw (int16x4_t s, int16x4_t t) -{ - return __builtin_loongson_pmaddhw (s, t); -} - -/* Maximum of signed halfwords. */ -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -pmaxsh (int16x4_t s, int16x4_t t) -{ - return __builtin_loongson_pmaxsh (s, t); -} - -/* Maximum of unsigned bytes. */ -__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -pmaxub (uint8x8_t s, uint8x8_t t) -{ - return __builtin_loongson_pmaxub (s, t); -} - -/* Minimum of signed halfwords. */ -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -pminsh (int16x4_t s, int16x4_t t) -{ - return __builtin_loongson_pminsh (s, t); -} - -/* Minimum of unsigned bytes. */ -__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -pminub (uint8x8_t s, uint8x8_t t) -{ - return __builtin_loongson_pminub (s, t); -} - -/* Move byte mask. */ -__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -pmovmskb_u (uint8x8_t s) -{ - return __builtin_loongson_pmovmskb_u (s); -} - -__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -pmovmskb_s (int8x8_t s) -{ - return __builtin_loongson_pmovmskb_s (s); -} - -/* Multiply unsigned integers and store high result. */ -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -pmulhuh (uint16x4_t s, uint16x4_t t) -{ - return __builtin_loongson_pmulhuh (s, t); -} - -/* Multiply signed integers and store high result. */ -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -pmulhh (int16x4_t s, int16x4_t t) -{ - return __builtin_loongson_pmulhh (s, t); -} - -/* Multiply signed integers and store low result. */ -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -pmullh (int16x4_t s, int16x4_t t) -{ - return __builtin_loongson_pmullh (s, t); -} - -/* Multiply unsigned word integers. */ -__extension__ static __inline int64_t __attribute__ ((__always_inline__)) -pmuluw (uint32x2_t s, uint32x2_t t) -{ - return __builtin_loongson_pmuluw (s, t); -} - -/* Absolute difference. */ -__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -pasubub (uint8x8_t s, uint8x8_t t) -{ - return __builtin_loongson_pasubub (s, t); -} - -/* Sum of unsigned byte integers. */ -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -biadd (uint8x8_t s) -{ - return __builtin_loongson_biadd (s); -} - -/* Sum of absolute differences. - Note that this intrinsic expands into two machine instructions: - PASUBUB followed by BIADD. */ -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -psadbh (uint8x8_t s, uint8x8_t t) -{ - return __builtin_loongson_psadbh (s, t); -} - -/* Shuffle halfwords. */ -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -pshufh_u (uint16x4_t dest, uint16x4_t s, uint8_t order) -{ - return __builtin_loongson_pshufh_u (s, order); -} - -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -pshufh_s (int16x4_t dest, int16x4_t s, uint8_t order) -{ - return __builtin_loongson_pshufh_s (s, order); -} - -/* Shift left logical. */ -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -psllh_u (uint16x4_t s, uint8_t amount) -{ - return __builtin_loongson_psllh_u (s, amount); -} - -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -psllh_s (int16x4_t s, uint8_t amount) -{ - return __builtin_loongson_psllh_s (s, amount); -} - -__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -psllw_u (uint32x2_t s, uint8_t amount) -{ - return __builtin_loongson_psllw_u (s, amount); -} - -__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -psllw_s (int32x2_t s, uint8_t amount) -{ - return __builtin_loongson_psllw_s (s, amount); -} - -/* Shift right logical. */ -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -psrlh_u (uint16x4_t s, uint8_t amount) -{ - return __builtin_loongson_psrlh_u (s, amount); -} - -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -psrlh_s (int16x4_t s, uint8_t amount) -{ - return __builtin_loongson_psrlh_s (s, amount); -} - -__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -psrlw_u (uint32x2_t s, uint8_t amount) -{ - return __builtin_loongson_psrlw_u (s, amount); -} - -__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -psrlw_s (int32x2_t s, uint8_t amount) -{ - return __builtin_loongson_psrlw_s (s, amount); -} - -/* Shift right arithmetic. */ -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -psrah_u (uint16x4_t s, uint8_t amount) -{ - return __builtin_loongson_psrah_u (s, amount); -} - -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -psrah_s (int16x4_t s, uint8_t amount) -{ - return __builtin_loongson_psrah_s (s, amount); -} - -__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -psraw_u (uint32x2_t s, uint8_t amount) -{ - return __builtin_loongson_psraw_u (s, amount); -} - -__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -psraw_s (int32x2_t s, uint8_t amount) -{ - return __builtin_loongson_psraw_s (s, amount); -} - -/* Vector subtraction, treating overflow by wraparound. */ -__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -psubw_u (uint32x2_t s, uint32x2_t t) -{ - return __builtin_loongson_psubw_u (s, t); -} - -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -psubh_u (uint16x4_t s, uint16x4_t t) -{ - return __builtin_loongson_psubh_u (s, t); -} - -__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -psubb_u (uint8x8_t s, uint8x8_t t) -{ - return __builtin_loongson_psubb_u (s, t); -} - -__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -psubw_s (int32x2_t s, int32x2_t t) -{ - return __builtin_loongson_psubw_s (s, t); -} - -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -psubh_s (int16x4_t s, int16x4_t t) -{ - return __builtin_loongson_psubh_s (s, t); -} - -__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -psubb_s (int8x8_t s, int8x8_t t) -{ - return __builtin_loongson_psubb_s (s, t); -} - -/* Subtraction of doubleword integers, treating overflow by wraparound. */ -__extension__ static __inline uint64_t __attribute__ ((__always_inline__)) -psubd_u (uint64_t s, uint64_t t) -{ - return __builtin_loongson_psubd_u (s, t); -} - -__extension__ static __inline int64_t __attribute__ ((__always_inline__)) -psubd_s (int64_t s, int64_t t) -{ - return __builtin_loongson_psubd_s (s, t); -} - -/* Vector subtraction, treating overflow by signed saturation. */ -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -psubsh (int16x4_t s, int16x4_t t) -{ - return __builtin_loongson_psubsh (s, t); -} - -__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -psubsb (int8x8_t s, int8x8_t t) -{ - return __builtin_loongson_psubsb (s, t); -} - -/* Vector subtraction, treating overflow by unsigned saturation. */ -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -psubush (uint16x4_t s, uint16x4_t t) -{ - return __builtin_loongson_psubush (s, t); -} - -__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -psubusb (uint8x8_t s, uint8x8_t t) -{ - return __builtin_loongson_psubusb (s, t); -} - -/* Unpack high data. */ -__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -punpckhwd_u (uint32x2_t s, uint32x2_t t) -{ - return __builtin_loongson_punpckhwd_u (s, t); -} - -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -punpckhhw_u (uint16x4_t s, uint16x4_t t) -{ - return __builtin_loongson_punpckhhw_u (s, t); -} - -__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -punpckhbh_u (uint8x8_t s, uint8x8_t t) -{ - return __builtin_loongson_punpckhbh_u (s, t); -} - -__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -punpckhwd_s (int32x2_t s, int32x2_t t) -{ - return __builtin_loongson_punpckhwd_s (s, t); -} - -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -punpckhhw_s (int16x4_t s, int16x4_t t) -{ - return __builtin_loongson_punpckhhw_s (s, t); -} - -__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -punpckhbh_s (int8x8_t s, int8x8_t t) -{ - return __builtin_loongson_punpckhbh_s (s, t); -} - -/* Unpack low data. */ -__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) -punpcklwd_u (uint32x2_t s, uint32x2_t t) -{ - return __builtin_loongson_punpcklwd_u (s, t); -} - -__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) -punpcklhw_u (uint16x4_t s, uint16x4_t t) -{ - return __builtin_loongson_punpcklhw_u (s, t); -} - -__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -punpcklbh_u (uint8x8_t s, uint8x8_t t) -{ - return __builtin_loongson_punpcklbh_u (s, t); -} - -__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) -punpcklwd_s (int32x2_t s, int32x2_t t) -{ - return __builtin_loongson_punpcklwd_s (s, t); -} - -__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) -punpcklhw_s (int16x4_t s, int16x4_t t) -{ - return __builtin_loongson_punpcklhw_s (s, t); -} - -__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -punpcklbh_s (int8x8_t s, int8x8_t t) -{ - return __builtin_loongson_punpcklbh_s (s, t); -} - -#ifdef __cplusplus -} -#endif +#if !defined(_GCC_LOONGSON_MMIINTRIN_H) +#warning \ + loongson.h will be deprecated without further notice at a future date. \ + Please use loongson-mmiintrin.h instead. +#include "loongson-mmiintrin.h" #endif diff --git a/gcc/config/mips/loongson.md b/gcc/config/mips/loongson.md deleted file mode 100644 index 14794d3..0000000 --- a/gcc/config/mips/loongson.md +++ /dev/null @@ -1,904 +0,0 @@ -;; Machine description for Loongson-specific patterns, such as -;; ST Microelectronics Loongson-2E/2F etc. -;; Copyright (C) 2008-2018 Free Software Foundation, Inc. -;; Contributed by CodeSourcery. -;; -;; This file is part of GCC. -;; -;; GCC is free software; you can redistribute it and/or modify -;; it under the terms of the GNU General Public License as published by -;; the Free Software Foundation; either version 3, or (at your option) -;; any later version. - -;; GCC is distributed in the hope that it will be useful, -;; but WITHOUT ANY WARRANTY; without even the implied warranty of -;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -;; GNU General Public License for more details. - -;; You should have received a copy of the GNU General Public License -;; along with GCC; see the file COPYING3. If not see -;; . - -(define_c_enum "unspec" [ - UNSPEC_LOONGSON_PAVG - UNSPEC_LOONGSON_PCMPEQ - UNSPEC_LOONGSON_PCMPGT - UNSPEC_LOONGSON_PEXTR - UNSPEC_LOONGSON_PINSRH - UNSPEC_LOONGSON_VINIT - UNSPEC_LOONGSON_PMADD - UNSPEC_LOONGSON_PMOVMSK - UNSPEC_LOONGSON_PMULHU - UNSPEC_LOONGSON_PMULH - UNSPEC_LOONGSON_PMULU - UNSPEC_LOONGSON_PASUBUB - UNSPEC_LOONGSON_BIADD - UNSPEC_LOONGSON_PSADBH - UNSPEC_LOONGSON_PSHUFH - UNSPEC_LOONGSON_PUNPCKH - UNSPEC_LOONGSON_PUNPCKL - UNSPEC_LOONGSON_PADDD - UNSPEC_LOONGSON_PSUBD - UNSPEC_LOONGSON_DSLL - UNSPEC_LOONGSON_DSRL -]) - -;; Mode iterators and attributes. - -;; 64-bit vectors of bytes. -(define_mode_iterator VB [V8QI]) - -;; 64-bit vectors of halfwords. -(define_mode_iterator VH [V4HI]) - -;; 64-bit vectors of words. -(define_mode_iterator VW [V2SI]) - -;; 64-bit vectors of halfwords and bytes. -(define_mode_iterator VHB [V4HI V8QI]) - -;; 64-bit vectors of words and halfwords. -(define_mode_iterator VWH [V2SI V4HI]) - -;; 64-bit vectors of words and bytes -(define_mode_iterator VWB [V2SI V8QI]) - -;; 64-bit vectors of words, halfwords and bytes. -(define_mode_iterator VWHB [V2SI V4HI V8QI]) - -;; 64-bit vectors of words, halfwords and bytes; and DImode. -(define_mode_iterator VWHBDI [V2SI V4HI V8QI DI]) - -;; The Loongson instruction suffixes corresponding to the modes in the -;; VWHBDI iterator. -(define_mode_attr V_suffix [(V2SI "w") (V4HI "h") (V8QI "b") (DI "d")]) - -;; Given a vector type T, the mode of a vector half the size of T -;; and with the same number of elements. -(define_mode_attr V_squash [(V2SI "V2HI") (V4HI "V4QI")]) - -;; Given a vector type T, the mode of a vector the same size as T -;; but with half as many elements. -(define_mode_attr V_stretch_half [(V2SI "DI") (V4HI "V2SI") (V8QI "V4HI")]) - -;; The Loongson instruction suffixes corresponding to the transformation -;; expressed by V_stretch_half. -(define_mode_attr V_stretch_half_suffix [(V2SI "wd") (V4HI "hw") (V8QI "bh")]) - -;; Given a vector type T, the mode of a vector the same size as T -;; but with twice as many elements. -(define_mode_attr V_squash_double [(V2SI "V4HI") (V4HI "V8QI")]) - -;; Given a vector type T, the inner mode. -(define_mode_attr V_inner [(V8QI "QI") (V4HI "HI") (V2SI "SI")]) - -;; The Loongson instruction suffixes corresponding to the conversions -;; specified by V_half_width. -(define_mode_attr V_squash_double_suffix [(V2SI "wh") (V4HI "hb")]) - -;; Move patterns. - -;; Expander to legitimize moves involving values of vector modes. -(define_expand "mov" - [(set (match_operand:VWHB 0) - (match_operand:VWHB 1))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" -{ - if (mips_legitimize_move (mode, operands[0], operands[1])) - DONE; -}) - -;; Handle legitimized moves between values of vector modes. -(define_insn "mov_internal" - [(set (match_operand:VWHB 0 "nonimmediate_operand" "=m,f,d,f, d, m, d") - (match_operand:VWHB 1 "move_operand" "f,m,f,dYG,dYG,dYG,m"))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - { return mips_output_move (operands[0], operands[1]); } - [(set_attr "move_type" "fpstore,fpload,mfc,mtc,move,store,load") - (set_attr "mode" "DI")]) - -;; Initialization of a vector. - -(define_expand "vec_init" - [(set (match_operand:VWHB 0 "register_operand") - (match_operand 1 ""))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" -{ - mips_expand_vector_init (operands[0], operands[1]); - DONE; -}) - -;; Helper for vec_init. Initialize element 0 of the output from the input. -;; All other elements are undefined. -(define_insn "loongson_vec_init1_" - [(set (match_operand:VHB 0 "register_operand" "=f") - (unspec:VHB [(truncate: - (match_operand:DI 1 "reg_or_0_operand" "Jd"))] - UNSPEC_LOONGSON_VINIT))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "dmtc1\t%z1,%0" - [(set_attr "move_type" "mtc") - (set_attr "mode" "DI")]) - -;; Helper for vec_initv2si. -(define_insn "*vec_concatv2si" - [(set (match_operand:V2SI 0 "register_operand" "=f") - (vec_concat:V2SI - (match_operand:SI 1 "register_operand" "f") - (match_operand:SI 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "punpcklwd\t%0,%1,%2" - [(set_attr "type" "fcvt")]) - -;; Instruction patterns for SIMD instructions. - -;; Pack with signed saturation. -(define_insn "vec_pack_ssat_" - [(set (match_operand: 0 "register_operand" "=f") - (vec_concat: - (ss_truncate: - (match_operand:VWH 1 "register_operand" "f")) - (ss_truncate: - (match_operand:VWH 2 "register_operand" "f"))))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "packss\t%0,%1,%2" - [(set_attr "type" "fmul")]) - -;; Pack with unsigned saturation. -(define_insn "vec_pack_usat_" - [(set (match_operand: 0 "register_operand" "=f") - (vec_concat: - (us_truncate: - (match_operand:VH 1 "register_operand" "f")) - (us_truncate: - (match_operand:VH 2 "register_operand" "f"))))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "packus\t%0,%1,%2" - [(set_attr "type" "fmul")]) - -;; Addition, treating overflow by wraparound. -(define_insn "add3" - [(set (match_operand:VWHB 0 "register_operand" "=f") - (plus:VWHB (match_operand:VWHB 1 "register_operand" "f") - (match_operand:VWHB 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "padd\t%0,%1,%2" - [(set_attr "type" "fadd")]) - -;; Addition of doubleword integers stored in FP registers. -;; Overflow is treated by wraparound. -;; We use 'unspec' instead of 'plus' here to avoid clash with -;; mips.md::add3. If 'plus' was used, then such instruction -;; would be recognized as adddi3 and reload would make it use -;; GPRs instead of FPRs. -(define_insn "loongson_paddd" - [(set (match_operand:DI 0 "register_operand" "=f") - (unspec:DI [(match_operand:DI 1 "register_operand" "f") - (match_operand:DI 2 "register_operand" "f")] - UNSPEC_LOONGSON_PADDD))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "paddd\t%0,%1,%2" - [(set_attr "type" "fadd")]) - -;; Addition, treating overflow by signed saturation. -(define_insn "ssadd3" - [(set (match_operand:VHB 0 "register_operand" "=f") - (ss_plus:VHB (match_operand:VHB 1 "register_operand" "f") - (match_operand:VHB 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "padds\t%0,%1,%2" - [(set_attr "type" "fadd")]) - -;; Addition, treating overflow by unsigned saturation. -(define_insn "usadd3" - [(set (match_operand:VHB 0 "register_operand" "=f") - (us_plus:VHB (match_operand:VHB 1 "register_operand" "f") - (match_operand:VHB 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "paddus\t%0,%1,%2" - [(set_attr "type" "fadd")]) - -;; Logical AND NOT. -(define_insn "loongson_pandn_" - [(set (match_operand:VWHBDI 0 "register_operand" "=f") - (and:VWHBDI - (not:VWHBDI (match_operand:VWHBDI 1 "register_operand" "f")) - (match_operand:VWHBDI 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "pandn\t%0,%1,%2" - [(set_attr "type" "fmul")]) - -;; Logical AND. -(define_insn "and3" - [(set (match_operand:VWHB 0 "register_operand" "=f") - (and:VWHB (match_operand:VWHB 1 "register_operand" "f") - (match_operand:VWHB 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "and\t%0,%1,%2" - [(set_attr "type" "fmul")]) - -;; Logical OR. -(define_insn "ior3" - [(set (match_operand:VWHB 0 "register_operand" "=f") - (ior:VWHB (match_operand:VWHB 1 "register_operand" "f") - (match_operand:VWHB 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "or\t%0,%1,%2" - [(set_attr "type" "fcvt")]) - -;; Logical XOR. -(define_insn "xor3" - [(set (match_operand:VWHB 0 "register_operand" "=f") - (xor:VWHB (match_operand:VWHB 1 "register_operand" "f") - (match_operand:VWHB 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "xor\t%0,%1,%2" - [(set_attr "type" "fmul")]) - -;; Logical NOR. -(define_insn "*loongson_nor" - [(set (match_operand:VWHB 0 "register_operand" "=f") - (and:VWHB - (not:VWHB (match_operand:VWHB 1 "register_operand" "f")) - (not:VWHB (match_operand:VWHB 2 "register_operand" "f"))))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "nor\t%0,%1,%2" - [(set_attr "type" "fmul")]) - -;; Logical NOT. -(define_insn "one_cmpl2" - [(set (match_operand:VWHB 0 "register_operand" "=f") - (not:VWHB (match_operand:VWHB 1 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "nor\t%0,%1,%1" - [(set_attr "type" "fmul")]) - -;; Average. -(define_insn "loongson_pavg" - [(set (match_operand:VHB 0 "register_operand" "=f") - (unspec:VHB [(match_operand:VHB 1 "register_operand" "f") - (match_operand:VHB 2 "register_operand" "f")] - UNSPEC_LOONGSON_PAVG))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "pavg\t%0,%1,%2" - [(set_attr "type" "fadd")]) - -;; Equality test. -(define_insn "loongson_pcmpeq" - [(set (match_operand:VWHB 0 "register_operand" "=f") - (unspec:VWHB [(match_operand:VWHB 1 "register_operand" "f") - (match_operand:VWHB 2 "register_operand" "f")] - UNSPEC_LOONGSON_PCMPEQ))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "pcmpeq\t%0,%1,%2" - [(set_attr "type" "fadd")]) - -;; Greater-than test. -(define_insn "loongson_pcmpgt" - [(set (match_operand:VWHB 0 "register_operand" "=f") - (unspec:VWHB [(match_operand:VWHB 1 "register_operand" "f") - (match_operand:VWHB 2 "register_operand" "f")] - UNSPEC_LOONGSON_PCMPGT))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "pcmpgt\t%0,%1,%2" - [(set_attr "type" "fadd")]) - -;; Extract halfword. -(define_insn "loongson_pextrh" - [(set (match_operand:V4HI 0 "register_operand" "=f") - (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "f") - (match_operand:SI 2 "register_operand" "f")] - UNSPEC_LOONGSON_PEXTR))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "pextrh\t%0,%1,%2" - [(set_attr "type" "fcvt")]) - -;; Insert halfword. -(define_insn "loongson_pinsrh_0" - [(set (match_operand:V4HI 0 "register_operand" "=f") - (vec_select:V4HI - (vec_concat:V8HI - (match_operand:V4HI 1 "register_operand" "f") - (match_operand:V4HI 2 "register_operand" "f")) - (parallel [(const_int 4) (const_int 1) - (const_int 2) (const_int 3)])))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "pinsrh_0\t%0,%1,%2" - [(set_attr "type" "fdiv")]) - -(define_insn "loongson_pinsrh_1" - [(set (match_operand:V4HI 0 "register_operand" "=f") - (vec_select:V4HI - (vec_concat:V8HI - (match_operand:V4HI 1 "register_operand" "f") - (match_operand:V4HI 2 "register_operand" "f")) - (parallel [(const_int 0) (const_int 4) - (const_int 2) (const_int 3)])))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "pinsrh_1\t%0,%1,%2" - [(set_attr "type" "fdiv")]) - -(define_insn "loongson_pinsrh_2" - [(set (match_operand:V4HI 0 "register_operand" "=f") - (vec_select:V4HI - (vec_concat:V8HI - (match_operand:V4HI 1 "register_operand" "f") - (match_operand:V4HI 2 "register_operand" "f")) - (parallel [(const_int 0) (const_int 1) - (const_int 4) (const_int 3)])))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "pinsrh_2\t%0,%1,%2" - [(set_attr "type" "fdiv")]) - -(define_insn "loongson_pinsrh_3" - [(set (match_operand:V4HI 0 "register_operand" "=f") - (vec_select:V4HI - (vec_concat:V8HI - (match_operand:V4HI 1 "register_operand" "f") - (match_operand:V4HI 2 "register_operand" "f")) - (parallel [(const_int 0) (const_int 1) - (const_int 2) (const_int 4)])))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "pinsrh_3\t%0,%1,%2" - [(set_attr "type" "fdiv")]) - -(define_insn "*vec_setv4hi" - [(set (match_operand:V4HI 0 "register_operand" "=f") - (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "f") - (match_operand:SI 2 "register_operand" "f") - (match_operand:SI 3 "const_0_to_3_operand" "")] - UNSPEC_LOONGSON_PINSRH))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "pinsrh_%3\t%0,%1,%2" - [(set_attr "type" "fdiv")]) - -(define_expand "vec_setv4hi" - [(set (match_operand:V4HI 0 "register_operand" "=f") - (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "f") - (match_operand:HI 2 "register_operand" "f") - (match_operand:SI 3 "const_0_to_3_operand" "")] - UNSPEC_LOONGSON_PINSRH))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" -{ - rtx ext = gen_reg_rtx (SImode); - emit_move_insn (ext, gen_lowpart (SImode, operands[2])); - operands[2] = ext; -}) - -;; Multiply and add packed integers. -(define_insn "loongson_pmaddhw" - [(set (match_operand:V2SI 0 "register_operand" "=f") - (unspec:V2SI [(match_operand:V4HI 1 "register_operand" "f") - (match_operand:V4HI 2 "register_operand" "f")] - UNSPEC_LOONGSON_PMADD))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "pmaddhw\t%0,%1,%2" - [(set_attr "type" "fmul")]) - -(define_expand "sdot_prodv4hi" - [(match_operand:V2SI 0 "register_operand" "") - (match_operand:V4HI 1 "register_operand" "") - (match_operand:V4HI 2 "register_operand" "") - (match_operand:V2SI 3 "register_operand" "")] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" -{ - rtx t = gen_reg_rtx (V2SImode); - emit_insn (gen_loongson_pmaddhw (t, operands[1], operands[2])); - emit_insn (gen_addv2si3 (operands[0], t, operands[3])); - DONE; -}) - -;; Maximum of signed halfwords. -(define_insn "smaxv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=f") - (smax:V4HI (match_operand:V4HI 1 "register_operand" "f") - (match_operand:V4HI 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "pmaxsh\t%0,%1,%2" - [(set_attr "type" "fadd")]) - -(define_expand "smax3" - [(match_operand:VWB 0 "register_operand" "") - (match_operand:VWB 1 "register_operand" "") - (match_operand:VWB 2 "register_operand" "")] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" -{ - mips_expand_vec_minmax (operands[0], operands[1], operands[2], - gen_loongson_pcmpgt, false); - DONE; -}) - -;; Maximum of unsigned bytes. -(define_insn "umaxv8qi3" - [(set (match_operand:V8QI 0 "register_operand" "=f") - (umax:V8QI (match_operand:V8QI 1 "register_operand" "f") - (match_operand:V8QI 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "pmaxub\t%0,%1,%2" - [(set_attr "type" "fadd")]) - -;; Minimum of signed halfwords. -(define_insn "sminv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=f") - (smin:V4HI (match_operand:V4HI 1 "register_operand" "f") - (match_operand:V4HI 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "pminsh\t%0,%1,%2" - [(set_attr "type" "fadd")]) - -(define_expand "smin3" - [(match_operand:VWB 0 "register_operand" "") - (match_operand:VWB 1 "register_operand" "") - (match_operand:VWB 2 "register_operand" "")] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" -{ - mips_expand_vec_minmax (operands[0], operands[1], operands[2], - gen_loongson_pcmpgt, true); - DONE; -}) - -;; Minimum of unsigned bytes. -(define_insn "uminv8qi3" - [(set (match_operand:V8QI 0 "register_operand" "=f") - (umin:V8QI (match_operand:V8QI 1 "register_operand" "f") - (match_operand:V8QI 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "pminub\t%0,%1,%2" - [(set_attr "type" "fadd")]) - -;; Move byte mask. -(define_insn "loongson_pmovmsk" - [(set (match_operand:VB 0 "register_operand" "=f") - (unspec:VB [(match_operand:VB 1 "register_operand" "f")] - UNSPEC_LOONGSON_PMOVMSK))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "pmovmsk\t%0,%1" - [(set_attr "type" "fabs")]) - -;; Multiply unsigned integers and store high result. -(define_insn "umul3_highpart" - [(set (match_operand:VH 0 "register_operand" "=f") - (unspec:VH [(match_operand:VH 1 "register_operand" "f") - (match_operand:VH 2 "register_operand" "f")] - UNSPEC_LOONGSON_PMULHU))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "pmulhu\t%0,%1,%2" - [(set_attr "type" "fmul")]) - -;; Multiply signed integers and store high result. -(define_insn "smul3_highpart" - [(set (match_operand:VH 0 "register_operand" "=f") - (unspec:VH [(match_operand:VH 1 "register_operand" "f") - (match_operand:VH 2 "register_operand" "f")] - UNSPEC_LOONGSON_PMULH))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "pmulh\t%0,%1,%2" - [(set_attr "type" "fmul")]) - -;; Multiply signed integers and store low result. -(define_insn "mul3" - [(set (match_operand:VH 0 "register_operand" "=f") - (mult:VH (match_operand:VH 1 "register_operand" "f") - (match_operand:VH 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "pmull\t%0,%1,%2" - [(set_attr "type" "fmul")]) - -;; Multiply unsigned word integers. -(define_insn "loongson_pmulu" - [(set (match_operand:DI 0 "register_operand" "=f") - (unspec:DI [(match_operand:VW 1 "register_operand" "f") - (match_operand:VW 2 "register_operand" "f")] - UNSPEC_LOONGSON_PMULU))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "pmulu\t%0,%1,%2" - [(set_attr "type" "fmul")]) - -;; Absolute difference. -(define_insn "loongson_pasubub" - [(set (match_operand:VB 0 "register_operand" "=f") - (unspec:VB [(match_operand:VB 1 "register_operand" "f") - (match_operand:VB 2 "register_operand" "f")] - UNSPEC_LOONGSON_PASUBUB))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "pasubub\t%0,%1,%2" - [(set_attr "type" "fadd")]) - -;; Sum of unsigned byte integers. -(define_insn "loongson_biadd" - [(set (match_operand: 0 "register_operand" "=f") - (unspec: [(match_operand:VB 1 "register_operand" "f")] - UNSPEC_LOONGSON_BIADD))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "biadd\t%0,%1" - [(set_attr "type" "fabs")]) - -(define_insn "reduc_uplus_v8qi" - [(set (match_operand:V8QI 0 "register_operand" "=f") - (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "f")] - UNSPEC_LOONGSON_BIADD))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "biadd\t%0,%1" - [(set_attr "type" "fabs")]) - -;; Sum of absolute differences. -(define_insn "loongson_psadbh" - [(set (match_operand: 0 "register_operand" "=f") - (unspec: [(match_operand:VB 1 "register_operand" "f") - (match_operand:VB 2 "register_operand" "f")] - UNSPEC_LOONGSON_PSADBH))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "pasubub\t%0,%1,%2;biadd\t%0,%0" - [(set_attr "type" "fadd")]) - -;; Shuffle halfwords. -(define_insn "loongson_pshufh" - [(set (match_operand:VH 0 "register_operand" "=f") - (unspec:VH [(match_operand:VH 1 "register_operand" "f") - (match_operand:SI 2 "register_operand" "f")] - UNSPEC_LOONGSON_PSHUFH))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "pshufh\t%0,%1,%2" - [(set_attr "type" "fmul")]) - -;; Shift left logical. -(define_insn "ashl3" - [(set (match_operand:VWH 0 "register_operand" "=f") - (ashift:VWH (match_operand:VWH 1 "register_operand" "f") - (match_operand:SI 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "psll\t%0,%1,%2" - [(set_attr "type" "fcvt")]) - -;; Shift right arithmetic. -(define_insn "ashr3" - [(set (match_operand:VWH 0 "register_operand" "=f") - (ashiftrt:VWH (match_operand:VWH 1 "register_operand" "f") - (match_operand:SI 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "psra\t%0,%1,%2" - [(set_attr "type" "fcvt")]) - -;; Shift right logical. -(define_insn "lshr3" - [(set (match_operand:VWH 0 "register_operand" "=f") - (lshiftrt:VWH (match_operand:VWH 1 "register_operand" "f") - (match_operand:SI 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "psrl\t%0,%1,%2" - [(set_attr "type" "fcvt")]) - -;; Subtraction, treating overflow by wraparound. -(define_insn "sub3" - [(set (match_operand:VWHB 0 "register_operand" "=f") - (minus:VWHB (match_operand:VWHB 1 "register_operand" "f") - (match_operand:VWHB 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "psub\t%0,%1,%2" - [(set_attr "type" "fadd")]) - -;; Subtraction of doubleword integers stored in FP registers. -;; Overflow is treated by wraparound. -;; See loongson_paddd for the reason we use 'unspec' rather than -;; 'minus' here. -(define_insn "loongson_psubd" - [(set (match_operand:DI 0 "register_operand" "=f") - (unspec:DI [(match_operand:DI 1 "register_operand" "f") - (match_operand:DI 2 "register_operand" "f")] - UNSPEC_LOONGSON_PSUBD))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "psubd\t%0,%1,%2" - [(set_attr "type" "fadd")]) - -;; Subtraction, treating overflow by signed saturation. -(define_insn "sssub3" - [(set (match_operand:VHB 0 "register_operand" "=f") - (ss_minus:VHB (match_operand:VHB 1 "register_operand" "f") - (match_operand:VHB 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "psubs\t%0,%1,%2" - [(set_attr "type" "fadd")]) - -;; Subtraction, treating overflow by unsigned saturation. -(define_insn "ussub3" - [(set (match_operand:VHB 0 "register_operand" "=f") - (us_minus:VHB (match_operand:VHB 1 "register_operand" "f") - (match_operand:VHB 2 "register_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "psubus\t%0,%1,%2" - [(set_attr "type" "fadd")]) - -;; Unpack high data. Recall that Loongson only runs in little-endian. -(define_insn "loongson_punpckhbh" - [(set (match_operand:V8QI 0 "register_operand" "=f") - (vec_select:V8QI - (vec_concat:V16QI - (match_operand:V8QI 1 "register_operand" "f") - (match_operand:V8QI 2 "register_operand" "f")) - (parallel [(const_int 4) (const_int 12) - (const_int 5) (const_int 13) - (const_int 6) (const_int 14) - (const_int 7) (const_int 15)])))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "punpckhbh\t%0,%1,%2" - [(set_attr "type" "fdiv")]) - -(define_insn "loongson_punpckhhw" - [(set (match_operand:V4HI 0 "register_operand" "=f") - (vec_select:V4HI - (vec_concat:V8HI - (match_operand:V4HI 1 "register_operand" "f") - (match_operand:V4HI 2 "register_operand" "f")) - (parallel [(const_int 2) (const_int 6) - (const_int 3) (const_int 7)])))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "punpckhhw\t%0,%1,%2" - [(set_attr "type" "fdiv")]) - -(define_insn "loongson_punpckhhw_qi" - [(set (match_operand:V8QI 0 "register_operand" "=f") - (vec_select:V8QI - (vec_concat:V16QI - (match_operand:V8QI 1 "register_operand" "f") - (match_operand:V8QI 2 "register_operand" "f")) - (parallel [(const_int 4) (const_int 5) - (const_int 12) (const_int 13) - (const_int 6) (const_int 7) - (const_int 14) (const_int 15)])))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "punpckhhw\t%0,%1,%2" - [(set_attr "type" "fdiv")]) - -(define_insn "loongson_punpckhwd" - [(set (match_operand:V2SI 0 "register_operand" "=f") - (vec_select:V2SI - (vec_concat:V4SI - (match_operand:V2SI 1 "register_operand" "f") - (match_operand:V2SI 2 "register_operand" "f")) - (parallel [(const_int 1) (const_int 3)])))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "punpckhwd\t%0,%1,%2" - [(set_attr "type" "fcvt")]) - -(define_insn "loongson_punpckhwd_qi" - [(set (match_operand:V8QI 0 "register_operand" "=f") - (vec_select:V8QI - (vec_concat:V16QI - (match_operand:V8QI 1 "register_operand" "f") - (match_operand:V8QI 2 "register_operand" "f")) - (parallel [(const_int 4) (const_int 5) - (const_int 6) (const_int 7) - (const_int 12) (const_int 13) - (const_int 14) (const_int 15)])))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "punpckhwd\t%0,%1,%2" - [(set_attr "type" "fcvt")]) - -(define_insn "loongson_punpckhwd_hi" - [(set (match_operand:V4HI 0 "register_operand" "=f") - (vec_select:V4HI - (vec_concat:V8HI - (match_operand:V4HI 1 "register_operand" "f") - (match_operand:V4HI 2 "register_operand" "f")) - (parallel [(const_int 2) (const_int 3) - (const_int 6) (const_int 7)])))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "punpckhwd\t%0,%1,%2" - [(set_attr "type" "fcvt")]) - -;; Unpack low data. -(define_insn "loongson_punpcklbh" - [(set (match_operand:V8QI 0 "register_operand" "=f") - (vec_select:V8QI - (vec_concat:V16QI - (match_operand:V8QI 1 "register_operand" "f") - (match_operand:V8QI 2 "register_operand" "f")) - (parallel [(const_int 0) (const_int 8) - (const_int 1) (const_int 9) - (const_int 2) (const_int 10) - (const_int 3) (const_int 11)])))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "punpcklbh\t%0,%1,%2" - [(set_attr "type" "fdiv")]) - -(define_insn "loongson_punpcklhw" - [(set (match_operand:V4HI 0 "register_operand" "=f") - (vec_select:V4HI - (vec_concat:V8HI - (match_operand:V4HI 1 "register_operand" "f") - (match_operand:V4HI 2 "register_operand" "f")) - (parallel [(const_int 0) (const_int 4) - (const_int 1) (const_int 5)])))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "punpcklhw\t%0,%1,%2" - [(set_attr "type" "fdiv")]) - -(define_insn "*loongson_punpcklhw_qi" - [(set (match_operand:V8QI 0 "register_operand" "=f") - (vec_select:V8QI - (vec_concat:V16QI - (match_operand:V8QI 1 "register_operand" "f") - (match_operand:V8QI 2 "register_operand" "f")) - (parallel [(const_int 0) (const_int 1) - (const_int 8) (const_int 9) - (const_int 2) (const_int 3) - (const_int 10) (const_int 11)])))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "punpcklhw\t%0,%1,%2" - [(set_attr "type" "fdiv")]) - -(define_insn "loongson_punpcklwd" - [(set (match_operand:V2SI 0 "register_operand" "=f") - (vec_select:V2SI - (vec_concat:V4SI - (match_operand:V2SI 1 "register_operand" "f") - (match_operand:V2SI 2 "register_operand" "f")) - (parallel [(const_int 0) (const_int 2)])))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "punpcklwd\t%0,%1,%2" - [(set_attr "type" "fcvt")]) - -(define_insn "*loongson_punpcklwd_qi" - [(set (match_operand:V8QI 0 "register_operand" "=f") - (vec_select:V8QI - (vec_concat:V16QI - (match_operand:V8QI 1 "register_operand" "f") - (match_operand:V8QI 2 "register_operand" "f")) - (parallel [(const_int 0) (const_int 1) - (const_int 2) (const_int 3) - (const_int 8) (const_int 9) - (const_int 10) (const_int 11)])))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "punpcklwd\t%0,%1,%2" - [(set_attr "type" "fcvt")]) - -(define_insn "*loongson_punpcklwd_hi" - [(set (match_operand:V4HI 0 "register_operand" "=f") - (vec_select:V4HI - (vec_concat:V8HI - (match_operand:V4HI 1 "register_operand" "f") - (match_operand:V4HI 2 "register_operand" "f")) - (parallel [(const_int 0) (const_int 1) - (const_int 4) (const_int 5)])))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "punpcklwd\t%0,%1,%2" - [(set_attr "type" "fcvt")]) - -(define_expand "vec_unpacks_lo_" - [(match_operand: 0 "register_operand" "") - (match_operand:VHB 1 "register_operand" "")] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" -{ - mips_expand_vec_unpack (operands, false, false); - DONE; -}) - -(define_expand "vec_unpacks_hi_" - [(match_operand: 0 "register_operand" "") - (match_operand:VHB 1 "register_operand" "")] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" -{ - mips_expand_vec_unpack (operands, false, true); - DONE; -}) - -(define_expand "vec_unpacku_lo_" - [(match_operand: 0 "register_operand" "") - (match_operand:VHB 1 "register_operand" "")] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" -{ - mips_expand_vec_unpack (operands, true, false); - DONE; -}) - -(define_expand "vec_unpacku_hi_" - [(match_operand: 0 "register_operand" "") - (match_operand:VHB 1 "register_operand" "")] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" -{ - mips_expand_vec_unpack (operands, true, true); - DONE; -}) - -;; Whole vector shifts, used for reduction epilogues. -(define_insn "vec_shl_" - [(set (match_operand:VWHBDI 0 "register_operand" "=f") - (unspec:VWHBDI [(match_operand:VWHBDI 1 "register_operand" "f") - (match_operand:SI 2 "register_operand" "f")] - UNSPEC_LOONGSON_DSLL))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "dsll\t%0,%1,%2" - [(set_attr "type" "fcvt")]) - -(define_insn "vec_shr_" - [(set (match_operand:VWHBDI 0 "register_operand" "=f") - (unspec:VWHBDI [(match_operand:VWHBDI 1 "register_operand" "f") - (match_operand:SI 2 "register_operand" "f")] - UNSPEC_LOONGSON_DSRL))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "dsrl\t%0,%1,%2" - [(set_attr "type" "fcvt")]) - -(define_insn "vec_loongson_extract_lo_" - [(set (match_operand: 0 "register_operand" "=r") - (vec_select: - (match_operand:VWHB 1 "register_operand" "f") - (parallel [(const_int 0)])))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "mfc1\t%0,%1" - [(set_attr "type" "mfc")]) - -(define_expand "reduc_plus_scal_" - [(match_operand: 0 "register_operand" "") - (match_operand:VWHB 1 "register_operand" "")] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" -{ - rtx tmp = gen_reg_rtx (GET_MODE (operands[1])); - mips_expand_vec_reduc (tmp, operands[1], gen_add3); - emit_insn (gen_vec_loongson_extract_lo_ (operands[0], tmp)); - DONE; -}) - -(define_expand "reduc_smax_scal_" - [(match_operand: 0 "register_operand" "") - (match_operand:VWHB 1 "register_operand" "")] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" -{ - rtx tmp = gen_reg_rtx (GET_MODE (operands[1])); - mips_expand_vec_reduc (tmp, operands[1], gen_smax3); - emit_insn (gen_vec_loongson_extract_lo_ (operands[0], tmp)); - DONE; -}) - -(define_expand "reduc_smin_scal_" - [(match_operand: 0 "register_operand" "") - (match_operand:VWHB 1 "register_operand" "")] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" -{ - rtx tmp = gen_reg_rtx (GET_MODE (operands[1])); - mips_expand_vec_reduc (tmp, operands[1], gen_smin3); - emit_insn (gen_vec_loongson_extract_lo_ (operands[0], tmp)); - DONE; -}) - -(define_expand "reduc_umax_scal_" - [(match_operand: 0 "register_operand" "") - (match_operand:VB 1 "register_operand" "")] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" -{ - rtx tmp = gen_reg_rtx (GET_MODE (operands[1])); - mips_expand_vec_reduc (tmp, operands[1], gen_umax3); - emit_insn (gen_vec_loongson_extract_lo_ (operands[0], tmp)); - DONE; -}) - -(define_expand "reduc_umin_scal_" - [(match_operand: 0 "register_operand" "") - (match_operand:VB 1 "register_operand" "")] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" -{ - rtx tmp = gen_reg_rtx (GET_MODE (operands[1])); - mips_expand_vec_reduc (tmp, operands[1], gen_umin3); - emit_insn (gen_vec_loongson_extract_lo_ (operands[0], tmp)); - DONE; -}) diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index ea2fae1..a804f70 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -12797,8 +12797,9 @@ mips_hard_regno_mode_ok_uncached (unsigned int regno, machine_mode mode) if (mode == CCFmode) return !(TARGET_FLOATXX && (regno & 1) != 0); - /* Allow 64-bit vector modes for Loongson-2E/2F. */ - if (TARGET_LOONGSON_VECTORS + /* Allow 64-bit vector modes for Loongson MultiMedia extensions + Instructions (MMI). */ + if (TARGET_LOONGSON_MMI && (mode == V2SImode || mode == V4HImode || mode == V8QImode @@ -13368,7 +13369,7 @@ mips_vector_mode_supported_p (machine_mode mode) case E_V2SImode: case E_V4HImode: case E_V8QImode: - return TARGET_LOONGSON_VECTORS; + return TARGET_LOONGSON_MMI; default: return MSA_SUPPORTED_MODE_P (mode); @@ -15203,7 +15204,7 @@ AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2) AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP) AVAIL_NON_MIPS16 (dsp_64, TARGET_64BIT && TARGET_DSP) AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2) -AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS) +AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_MMI) AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN) AVAIL_NON_MIPS16 (msa, TARGET_MSA) @@ -20164,6 +20165,19 @@ mips_option_override (void) TARGET_DSPR2 = false; } + /* Make sure that when TARGET_LOONGSON_MMI is true, TARGET_HARD_FLOAT_ABI + is true. In o32 pairs of floating-point registers provide 64-bit + values. */ + if (TARGET_LOONGSON_MMI && !TARGET_HARD_FLOAT_ABI) + error ("%<-mloongson-mmi%> must be used with %<-mhard-float%>"); + + /* Default to enable Loongson MMI on Longson 2e, 2f or 3a target. */ + if ((target_flags_explicit & MASK_LOONGSON_MMI) == 0 + && ((strcmp (mips_arch_info->name, "loongson2e") == 0) + || (strcmp (mips_arch_info->name, "loongson2f") == 0) + || (strcmp (mips_arch_info->name, "loongson3a") == 0))) + target_flags |= MASK_LOONGSON_MMI; + /* .eh_frame addresses should be the same width as a C pointer. Most MIPS ABIs support only one pointer size, so the assembler will usually know exactly how big an .eh_frame address is. @@ -21149,12 +21163,12 @@ void mips_function_profiler (FILE *file) /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default behavior of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even - when TARGET_LOONGSON_VECTORS is true. */ + when TARGET_LOONGSON_MMI is true. */ static unsigned HOST_WIDE_INT mips_shift_truncation_mask (machine_mode mode) { - if (TARGET_LOONGSON_VECTORS && VECTOR_MODE_P (mode)) + if (TARGET_LOONGSON_MMI && VECTOR_MODE_P (mode)) return 0; return GET_MODE_BITSIZE (mode) - 1; @@ -21255,7 +21269,7 @@ mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d *d) unsigned i, odd, nelt = d->nelt; rtx t0, t1, t2, t3; - if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS)) + if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI)) return false; /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */ if (nelt < 4) @@ -21312,7 +21326,7 @@ mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d *d) unsigned i, mask; rtx rmask; - if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS)) + if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI)) return false; if (d->vmode != V4HImode) return false; @@ -21364,7 +21378,7 @@ mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d *d) unsigned i, elt; rtx t0, t1; - if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS)) + if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI)) return false; /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */ if (d->vmode != V8QImode) @@ -21958,7 +21972,7 @@ mips_expand_vector_init (rtx target, rtx vals) } /* Loongson is the only cpu with vectors with more elements. */ - gcc_assert (TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS); + gcc_assert (TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI); /* If all values are identical, broadcast the value. */ if (all_same) diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 6804b79..3563c1d 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -319,13 +319,6 @@ struct mips_cpu_info { #define TUNE_I6400 (mips_tune == PROCESSOR_I6400) #define TUNE_P6600 (mips_tune == PROCESSOR_P6600) -/* Whether vector modes and intrinsics for ST Microelectronics - Loongson-2E/2F processors should be enabled. In o32 pairs of - floating-point registers provide 64-bit values. */ -#define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \ - && (TARGET_LOONGSON_2EF \ - || TARGET_LOONGSON_3A)) - /* True if the pre-reload scheduler should try to create chains of multiply-add or multiply-subtract instructions. For example, suppose we have: @@ -596,9 +589,12 @@ struct mips_cpu_info { if (TARGET_ABICALLS) \ builtin_define ("__mips_abicalls"); \ \ - /* Whether Loongson vector modes are enabled. */ \ - if (TARGET_LOONGSON_VECTORS) \ - builtin_define ("__mips_loongson_vector_rev"); \ + /* Whether Loongson vector modes are enabled. */ \ + if (TARGET_LOONGSON_MMI) \ + { \ + builtin_define ("__mips_loongson_vector_rev"); \ + builtin_define ("__mips_loongson_mmi"); \ + } \ \ /* Historical Octeon macro. */ \ if (TARGET_OCTEON) \ @@ -1358,6 +1354,7 @@ struct mips_cpu_info { %{mcrc} %{mno-crc} \ %{mginv} %{mno-ginv} \ %{mmsa} %{mno-msa} \ +%{mloongson-mmi} %{mno-loongson-mmi} \ %{msmartmips} %{mno-smartmips} \ %{mmt} %{mno-mt} \ %{mfix-rm7000} %{mno-fix-rm7000} \ @@ -2635,9 +2632,9 @@ typedef struct mips_args { #define SLOW_BYTE_ACCESS (!TARGET_MIPS16) /* Standard MIPS integer shifts truncate the shift amount to the - width of the shifted operand. However, Loongson vector shifts + width of the shifted operand. However, Loongson MMI shifts do not truncate the shift amount at all. */ -#define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_VECTORS) +#define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_MMI) /* Specify the machine mode that pointers have. diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index ea5a23b..a88c1c5 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -834,9 +834,9 @@ (define_mode_iterator MOVE64 [DI DF (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT") - (V2SI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS") - (V4HI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS") - (V8QI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")]) + (V2SI "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI") + (V4HI "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI") + (V8QI "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI")]) ;; 128-bit modes for which we provide move patterns on 64-bit targets. (define_mode_iterator MOVE128 [TI TF]) @@ -863,9 +863,9 @@ [(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT") (DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT") (V2SF "!TARGET_64BIT && TARGET_PAIRED_SINGLE_FLOAT") - (V2SI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS") - (V4HI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS") - (V8QI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS") + (V2SI "!TARGET_64BIT && TARGET_LOONGSON_MMI") + (V4HI "!TARGET_64BIT && TARGET_LOONGSON_MMI") + (V8QI "!TARGET_64BIT && TARGET_LOONGSON_MMI") (TF "TARGET_64BIT && TARGET_FLOAT64")]) ;; In GPR templates, a string like "subu" will expand to "subu" in the @@ -7690,8 +7690,8 @@ ; microMIPS patterns. (include "micromips.md") -; ST-Microelectronics Loongson-2E/2F-specific patterns. -(include "loongson.md") +; Loongson MultiMedia extensions Instructions (MMI) patterns. +(include "loongson-mmi.md") ; The MIPS MSA Instructions. (include "mips-msa.md") diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index 5a9f255..6767c47 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -459,3 +459,7 @@ Enum(mips_cb_setting) String(optimal) Value(MIPS_CB_OPTIMAL) EnumValue Enum(mips_cb_setting) String(always) Value(MIPS_CB_ALWAYS) + +mloongson-mmi +Target Report Mask(LOONGSON_MMI) +Use Loongson MultiMedia extensions Instructions (MMI) instructions. diff --git a/gcc/testsuite/gcc.target/mips/loongson-shift-count-truncated-1.c b/gcc/testsuite/gcc.target/mips/loongson-shift-count-truncated-1.c index baed48c..6e22c0e 100644 --- a/gcc/testsuite/gcc.target/mips/loongson-shift-count-truncated-1.c +++ b/gcc/testsuite/gcc.target/mips/loongson-shift-count-truncated-1.c @@ -4,11 +4,11 @@ /* loongson.h does not handle or check for MIPS16ness. There doesn't seem any good reason for it to, given that the Loongson processors do not support MIPS16. */ -/* { dg-options "isa=loongson -mhard-float -mno-mips16 (REQUIRES_STDLIB)" } */ +/* { dg-options "-mloongson-mmi -mhard-float -mno-mips16 (REQUIRES_STDLIB)" } */ /* See PR 52155. */ -/* { dg-options "isa=loongson -mhard-float -mno-mips16 -mlong64" { mips*-*-elf* && ilp32 } } */ +/* { dg-options "-mloongson-mmi -mhard-float -mno-mips16 -mlong64" { mips*-*-elf* && ilp32 } } */ -#include "loongson.h" +#include "loongson-mmiintrin.h" #include typedef union { int32x2_t v; int32_t a[2]; } int32x2_encap_t; diff --git a/gcc/testsuite/gcc.target/mips/loongson-simd.c b/gcc/testsuite/gcc.target/mips/loongson-simd.c index f263b43..34fdcec 100644 --- a/gcc/testsuite/gcc.target/mips/loongson-simd.c +++ b/gcc/testsuite/gcc.target/mips/loongson-simd.c @@ -26,9 +26,9 @@ along with GCC; see the file COPYING3. If not see because inclusion of some system headers e.g. stdint.h will fail due to not finding stubs-o32_hard.h. */ /* { dg-require-effective-target mips_nanlegacy } */ -/* { dg-options "isa=loongson -mhard-float -mno-micromips -mno-mips16 -flax-vector-conversions (REQUIRES_STDLIB)" } */ +/* { dg-options "-mloongson-mmi -mhard-float -mno-micromips -mno-mips16 -flax-vector-conversions (REQUIRES_STDLIB)" } */ -#include "loongson.h" +#include "loongson-mmiintrin.h" #include #include #include diff --git a/gcc/testsuite/gcc.target/mips/mips.exp b/gcc/testsuite/gcc.target/mips/mips.exp index 9db4fbe..4045c59 100644 --- a/gcc/testsuite/gcc.target/mips/mips.exp +++ b/gcc/testsuite/gcc.target/mips/mips.exp @@ -296,6 +296,7 @@ foreach option { mcount-ra-address odd-spreg msa + loongson-mmi } { lappend mips_option_groups $option "-m(no-|)$option" } @@ -883,6 +884,12 @@ proc mips-dg-init {} { "-mno-msa" #endif + #ifdef __mips_loongson_mmi + "-mloongson-mmi" + #else + "-mno-loongson-mmi" + #endif + 0 }; } 0] diff --git a/gcc/testsuite/gcc.target/mips/umips-store16-1.c b/gcc/testsuite/gcc.target/mips/umips-store16-1.c index 6377e85..f82c837 100644 --- a/gcc/testsuite/gcc.target/mips/umips-store16-1.c +++ b/gcc/testsuite/gcc.target/mips/umips-store16-1.c @@ -1,4 +1,4 @@ -/* { dg-options "(-mmicromips)" } */ +/* { dg-options "(-mmicromips) forbid_cpu=loongson3a" } */ /* { dg-do assemble } */ register unsigned int global asm ("$16"); diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index b04ceb6..91e7398 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -1913,20 +1913,20 @@ proc check_mpaired_single_hw_available { } { # Return 1 if the target supports executing Loongson vector instructions, # 0 otherwise. Cache the result. -proc check_mips_loongson_hw_available { } { - return [check_cached_effective_target mips_loongson_hw_available { +proc check_mips_loongson_mmi_hw_available { } { + return [check_cached_effective_target mips_loongson_mmi_hw_available { # If this is not the right target then we can skip the test. if { !([istarget mips*-*-*]) } { expr 0 } else { - check_runtime_nocache mips_loongson_hw_available { - #include + check_runtime_nocache mips_loongson_mmi_hw_available { + #include int main() { asm volatile ("paddw $f2,$f4,$f6"); return 0; } - } "" + } "-mloongson-mmi" } }] } @@ -1980,9 +1980,9 @@ proc check_effective_target_mpaired_single_runtime { } { # Return 1 if the target supports running Loongson executables, 0 otherwise. -proc check_effective_target_mips_loongson_runtime { } { - if { [check_effective_target_mips_loongson] - && [check_mips_loongson_hw_available] } { +proc check_effective_target_mips_loongson_mmi_runtime { } { + if { [check_effective_target_mips_loongson_mmi] + && [check_mips_loongson_mmi_hw_available] } { return 1 } return 0 @@ -3113,7 +3113,7 @@ proc check_effective_target_vect_int { } { || [istarget aarch64*-*-*] || [is-effective-target arm_neon] || ([istarget mips*-*-*] - && ([et-is-effective-target mips_loongson] + && ([et-is-effective-target mips_loongson_mmi] || [et-is-effective-target mips_msa])) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) } { @@ -4850,11 +4850,24 @@ proc add_options_for_mips_msa { flags } { return "$flags -mmsa" } +# Add the options needed for MIPS Loongsn MMI Architecture. + +proc add_options_for_mips_loongson_mmi { flags } { + if { ! [check_effective_target_mips_loongson_mmi] } { + return "$flags" + } + return "$flags -mloongson-mmi" +} + + # Return 1 if this a Loongson-2E or -2F target using an ABI that supports # the Loongson vector modes. -proc check_effective_target_mips_loongson { } { +proc check_effective_target_mips_loongson_mmi { } { return [check_no_compiler_messages loongson assembly { + #if !defined(__mips_loongson_mmi) + #error !__mips_loongson_mmi + #endif #if !defined(__mips_loongson_vector_rev) #error !__mips_loongson_vector_rev #endif @@ -5459,7 +5472,7 @@ proc check_effective_target_vect_shift { } { || [is-effective-target arm_neon] || ([istarget mips*-*-*] && ([et-is-effective-target mips_msa] - || [et-is-effective-target mips_loongson])) + || [et-is-effective-target mips_loongson_mmi])) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) } { set et_vect_shift_saved($et_index) 1 @@ -5479,7 +5492,7 @@ proc check_effective_target_whole_vector_shift { } { || ([is-effective-target arm_neon] && [check_effective_target_arm_little_endian]) || ([istarget mips*-*-*] - && [et-is-effective-target mips_loongson]) + && [et-is-effective-target mips_loongson_mmi]) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) } { set answer 1 @@ -5693,7 +5706,7 @@ proc check_effective_target_vect_no_int_min_max { } { || [istarget spu-*-*] || [istarget alpha*-*-*] || ([istarget mips*-*-*] - && [et-is-effective-target mips_loongson]) } { + && [et-is-effective-target mips_loongson_mmi]) } { set et_vect_no_int_min_max_saved($et_index) 1 } } @@ -6472,7 +6485,7 @@ proc check_effective_target_vect_no_align { } { || [check_effective_target_arm_vect_no_misalign] || ([istarget powerpc*-*-*] && [check_p8vector_hw_available]) || ([istarget mips*-*-*] - && [et-is-effective-target mips_loongson]) } { + && [et-is-effective-target mips_loongson_mmi]) } { set et_vect_no_align_saved($et_index) 1 } } @@ -6802,7 +6815,7 @@ proc check_effective_target_vect_short_mult { } { || [check_effective_target_arm32] || ([istarget mips*-*-*] && ([et-is-effective-target mips_msa] - || [et-is-effective-target mips_loongson])) + || [et-is-effective-target mips_loongson_mmi])) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) } { set et_vect_short_mult_saved($et_index) 1 @@ -8617,8 +8630,8 @@ proc check_vect_support_and_set_flags { } { if { [check_effective_target_mpaired_single] } { lappend EFFECTIVE_TARGETS mpaired_single } - if { [check_effective_target_mips_loongson] } { - lappend EFFECTIVE_TARGETS mips_loongson + if { [check_effective_target_mips_loongson_mmi] } { + lappend EFFECTIVE_TARGETS mips_loongson_mmi } if { [check_effective_target_mips_msa] } { lappend EFFECTIVE_TARGETS mips_msa -- 1.7.1 From patchwork Mon Sep 3 12:32:23 2018 Content-Type: text/plain; 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3 Sep 2018 12:32:39 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.1 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=clz, pop, UD:mips.h, Chenghua X-HELO: mail-oi0-f53.google.com Received: from mail-oi0-f53.google.com (HELO mail-oi0-f53.google.com) (209.85.218.53) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 03 Sep 2018 12:32:36 +0000 Received: by mail-oi0-f53.google.com with SMTP id l82-v6so644321oih.11 for ; Mon, 03 Sep 2018 05:32:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to:cc; bh=kaEOIFSwB32hp+/3OujbxR5LBIbuQs/HkZyXiqaX0L0=; b=m1ZwFeHa95GQoulhOq2n83w4VdG4cx7GDxvpAcGllOc00PCEw5B1V1vAVxOpi7Efib RagGx/H04QJvY3axB/jdo+J8nZ6/7bCMDsw/QLrt98HgJJpZy1bzxIXHhtOnB/Ng8KAB ktahUJsBrs3IKLtl0vGSAY/95wI4kmCLZ7Tp346F/OQmfF4fR47phOiKRJO/i5aIBOwV E5ykIwNLck69TaBnFR2BoTvxnZhCiDU5NSIwfjRJso4SqAn6LNDhRppoMRKql7GISFnH zTaQkicOHWVOU5EYVdKNhWFyuGmTw4K6hGP10aNikYtUv3KxERcHmhclS+n396nkFqY/ KDDg== MIME-Version: 1.0 From: Paul Hua Date: Mon, 3 Sep 2018 20:32:23 +0800 Message-ID: Subject: [PATCH 3/6] [MIPS] Add Loongson EXTensions R2 (EXT2) instructions support To: gcc-patches Cc: Matthew Fortune X-IsSubscribed: yes From 2871889515b9c7cc1af7bc93fe9e645b3adcd623 Mon Sep 17 00:00:00 2001 From: Chenghua Xu Date: Fri, 31 Aug 2018 11:55:48 +0800 Subject: [PATCH 3/6] [MIPS] Add support for Loongson EXT2 istructions. gcc/ * config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Define __mips_loongson_ext2, __mips_loongson_ext_rev=2. (ISA_HAS_CTZ_CTO): New, ture if TARGET_LOONGSON_EXT2. (ASM_SPEC): Add mloongson-ext2 and mno-loongson-ext2. * config/mips/mips.md: Add ctz to "define_attr "type"". (define_insn "ctz2"): New insn pattern. (define_insn "prefetch"): Include TARGET_LOONGSON_EXT2. * config/mips/mips.opt: Add -mloongson-ext2 option. gcc/testsuite/ * gcc.target/mips/loongson-ctz.c: New test. * gcc.target/mips/loongson-dctz.c: Likewise. * gcc.target/mips/mips.exp (mips_option_groups): Add -mloongson-ext2 option. --- gcc/config/mips/mips.h | 12 +++++++++ gcc/config/mips/mips.md | 31 +++++++++++++++++++++---- gcc/config/mips/mips.opt | 4 +++ gcc/testsuite/gcc.target/mips/loongson-ctz.c | 11 +++++++++ gcc/testsuite/gcc.target/mips/loongson-dctz.c | 11 +++++++++ gcc/testsuite/gcc.target/mips/mips.exp | 1 + 6 files changed, 65 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/mips/loongson-ctz.c create mode 100644 gcc/testsuite/gcc.target/mips/loongson-dctz.c diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index e0e78ba..b75646d 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -600,8 +600,16 @@ struct mips_cpu_info { if (TARGET_LOONGSON_EXT) \ { \ builtin_define ("__mips_loongson_ext"); \ + if (TARGET_LOONGSON_EXT2) \ + { \ + builtin_define ("__mips_loongson_ext2"); \ + builtin_define ("__mips_loongson_ext_rev=2"); \ + } \ + else \ + builtin_define ("__mips_loongson_ext_rev=1"); \ } \ \ + \ /* Historical Octeon macro. */ \ if (TARGET_OCTEON) \ builtin_define ("__OCTEON__"); \ @@ -1117,6 +1125,9 @@ struct mips_cpu_info { /* ISA has count leading zeroes/ones instruction (not implemented). */ #define ISA_HAS_CLZ_CLO (mips_isa_rev >= 1 && !TARGET_MIPS16) +/* ISA has count tailing zeroes/ones instruction (not implemented). */ +#define ISA_HAS_CTZ_CTO (TARGET_LOONGSON_EXT2) + /* ISA has three operand multiply instructions that put the high part in an accumulator: mulhi or mulhiu. */ #define ISA_HAS_MULHI ((TARGET_MIPS5400 \ @@ -1362,6 +1373,7 @@ struct mips_cpu_info { %{mmsa} %{mno-msa} \ %{mloongson-mmi} %{mno-loongson-mmi} \ %{mloongson-ext} %{mno-loongson-ext} \ +%{mloongson-ext2} %{mno-loongson-ext2} \ %{msmartmips} %{mno-smartmips} \ %{mmt} %{mno-mt} \ %{mfix-rm7000} %{mno-fix-rm7000} \ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 4b7a627..c8128d4 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -335,6 +335,7 @@ ;; slt set less than instructions ;; signext sign extend instructions ;; clz the clz and clo instructions +;; ctz the ctz and cto instructions ;; pop the pop instruction ;; trap trap if instructions ;; imul integer multiply 2 operands @@ -375,7 +376,7 @@ (define_attr "type" "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore, prefetch,prefetchx,condmove,mtc,mfc,mthi,mtlo,mfhi,mflo,const,arith,logical, - shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move, + shift,slt,signext,clz,ctz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move, fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt, frsqrt,frsqrt1,frsqrt2,dspmac,dspmacsat,accext,accmod,dspalu,dspalusat, multi,atomic,syncloop,nop,ghost,multimem, @@ -3149,6 +3150,23 @@ ;; ;; ................... ;; +;; Count tailing zeroes. +;; +;; ................... +;; + +(define_insn "ctz2" + [(set (match_operand:GPR 0 "register_operand" "=d") + (ctz:GPR (match_operand:GPR 1 "register_operand" "d")))] + "ISA_HAS_CTZ_CTO" + "ctz\t%0,%1" + [(set_attr "type" "ctz") + (set_attr "mode" "")]) + + +;; +;; ................... +;; ;; Count number of set bits. ;; ;; ................... @@ -7136,13 +7154,16 @@ (match_operand 2 "const_int_operand" "n"))] "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS" { - if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT) + if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || TARGET_LOONGSON_EXT2) { - /* Loongson 2[ef] and Loongson 3a use load to $0 for prefetching. */ + /* Loongson ext2 implementation pref insnstructions. */ + if (TARGET_LOONGSON_EXT2) + return "pref\t%1, %a0"; + /* Loongson 2[ef] and Loongson ext use load to $0 for prefetching. */ if (TARGET_64BIT) - return "ld\t$0,%a0"; + return "ld\t$0,%a0"; else - return "lw\t$0,%a0"; + return "lw\t$0,%a0"; } operands[1] = mips_prefetch_cookie (operands[1], operands[2]); return "pref\t%1,%a0"; diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index a8fe8db..c0c8005 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -467,3 +467,7 @@ Use Loongson MultiMedia extensions Instructions (MMI) instructions. mloongson-ext Target Report Mask(LOONGSON_EXT) Use Loongson EXTension (EXT) instructions. + +mloongson-ext2 +Target Report Mask(LOONGSON_EXT2) +Use Loongson EXTension R2 (EXT2) instructions. diff --git a/gcc/testsuite/gcc.target/mips/loongson-ctz.c b/gcc/testsuite/gcc.target/mips/loongson-ctz.c new file mode 100644 index 0000000..8df66a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/loongson-ctz.c @@ -0,0 +1,11 @@ +/* Test cases for Loongson EXT2 instrutions. */ + +/* { dg-do compile } */ +/* { dg-options "-mloongson-ext2" } */ + +unsigned int foo(unsigned int x) +{ + return __builtin_ctz (x); +} + +/* { dg-final { scan-assembler "ctz\t" } } */ diff --git a/gcc/testsuite/gcc.target/mips/loongson-dctz.c b/gcc/testsuite/gcc.target/mips/loongson-dctz.c new file mode 100644 index 0000000..8c47433 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/loongson-dctz.c @@ -0,0 +1,11 @@ +/* Test cases for Loongson EXT2 instrutions. */ + +/* { dg-do compile } */ +/* { dg-options "-mloongson-ext2" } */ + +unsigned long long foo(unsigned long long x) +{ + return __builtin_ctzl (x); +} + +/* { dg-final { scan-assembler "dctz\t" } } */ diff --git a/gcc/testsuite/gcc.target/mips/mips.exp b/gcc/testsuite/gcc.target/mips/mips.exp index 70f7a99..5b2bf8b 100644 --- a/gcc/testsuite/gcc.target/mips/mips.exp +++ b/gcc/testsuite/gcc.target/mips/mips.exp @@ -298,6 +298,7 @@ foreach option { msa loongson-mmi loongson-ext + loongson-ext2 } { lappend mips_option_groups $option "-m(no-|)$option" } -- 1.7.1 From patchwork Mon Sep 3 12:33:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Hua X-Patchwork-Id: 965404 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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auth=none X-Spam-SWARE-Status: No, score=-26.1 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=firstly, pipelined, reservations, xlr X-HELO: mail-oi0-f42.google.com Received: from mail-oi0-f42.google.com (HELO mail-oi0-f42.google.com) (209.85.218.42) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 03 Sep 2018 12:33:53 +0000 Received: by mail-oi0-f42.google.com with SMTP id t68-v6so638275oie.12 for ; Mon, 03 Sep 2018 05:33:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to:cc; bh=Q7r9stsrP0sCkoFdgU2infOfd2ba3ggwS5RRovhC9mE=; b=WerWDUJUoJ36VIX1x5AtLiew27Qylono+/kaTs9FElA5hgluGfDYnjf8bd7w4rQRrP HAJzxxMEJPSkCCL5uN78w5Bi18uAHDFzijhBh670oRC11DwC1Rp4Lk4sRHy+VBbD/Wbz fbrTymgZa4vI9FUrX345YVoTJJ84PwGT+H6Y2etM57aQbo8EPcWBAczg1eHCimFdbJBP FA2frMM6MrWBVsgz+mhCNyWLa/tE1703GDEM3YSd+7OrXe1Dycuzpuybvqfnz16q+d1o qXcUiSOwALhhWW/AjtLIYlfZ6c7+rpxSHCyYYcdFDZOe17WexcJVfZDwU2egjJMwX2vT uJYg== MIME-Version: 1.0 From: Paul Hua Date: Mon, 3 Sep 2018 20:33:40 +0800 Message-ID: Subject: [PATCH 4/6] [MIPS] Add Loongson 3A1000 processor support. To: gcc-patches Cc: Matthew Fortune X-IsSubscribed: yes From 133e21aa8cd7a6f533840bf8255f8edd27543bb3 Mon Sep 17 00:00:00 2001 From: Chenghua Xu Date: Fri, 31 Aug 2018 14:08:01 +0800 Subject: [PATCH 4/6] [MIPS] Add support for Loongson 3A1000 proccessor. gcc/ * config/mips/loongson3a.md: Rename to ... * config/mips/gs464.md: ... here. * config/mips/mips-cpus.def: Define gs464; Add loongson3a as an alias of gs464 processor. * config/mips/mips-tables.opt: Regenerate. * config/mips/mips.c (mips_issue_rate): Use PROCESSOR_GS464 instead of ROCESSOR_LOONGSON_3A. (mips_multipass_dfa_lookahead): Use TUNE_GS464 instread of TUNE_LOONGSON_3A. (mips_option_override): Enable MMI and EXT for gs464. * config/mips/mips.h: Rename TARGET_LOONGSON_3A to TARGET_GS464; Rename TUNE_LOONGSON_3A to TUNE_GS464. (MIPS_ISA_LEVEL_SPEC): Infer mips64r2 from gs464. (ISA_HAS_ODD_SPREG, ISA_AVOID_DIV_HILO, ISA_HAS_FUSED_MADD4, ISA_HAS_UNFUSED_MADD4): Use TARGET_GS464 instead of TARGET_LOONGSON_3A. * config/mips/mips.md: Include gs464.md instead of loongson3a.md. (processor): Add gs464; * doc/invoke.texi: Add gs464 to supported architectures. --- gcc/config/mips/gs464.md | 137 +++++++++++++++++++++++++++++++++++++++ gcc/config/mips/loongson3a.md | 137 --------------------------------------- gcc/config/mips/mips-cpus.def | 3 +- gcc/config/mips/mips-tables.opt | 19 +++-- gcc/config/mips/mips.c | 16 +++-- gcc/config/mips/mips.h | 15 ++-- gcc/config/mips/mips.md | 4 +- gcc/doc/invoke.texi | 2 +- 8 files changed, 170 insertions(+), 163 deletions(-) create mode 100644 gcc/config/mips/gs464.md delete mode 100644 gcc/config/mips/loongson3a.md diff --git a/gcc/config/mips/gs464.md b/gcc/config/mips/gs464.md new file mode 100644 index 0000000..82efb66 --- /dev/null +++ b/gcc/config/mips/gs464.md @@ -0,0 +1,137 @@ +;; Pipeline model for Loongson gs464 cores. + +;; Copyright (C) 2011-2018 Free Software Foundation, Inc. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 3, or (at your +;; option) any later version. +;; +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +;; Uncomment the following line to output automata for debugging. +;; (automata_option "v") + +;; Automaton for integer instructions. +(define_automaton "gs464_a_alu") + +;; Automaton for floating-point instructions. +(define_automaton "gs464_a_falu") + +;; Automaton for memory operations. +(define_automaton "gs464_a_mem") + +;; Describe the resources. + +(define_cpu_unit "gs464_alu1" "gs464_a_alu") +(define_cpu_unit "gs464_alu2" "gs464_a_alu") +(define_cpu_unit "gs464_mem" "gs464_a_mem") +(define_cpu_unit "gs464_falu1" "gs464_a_falu") +(define_cpu_unit "gs464_falu2" "gs464_a_falu") + +;; Describe instruction reservations. + +(define_insn_reservation "gs464_arith" 1 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "arith,clz,const,logical, + move,nop,shift,signext,slt")) + "gs464_alu1 | gs464_alu2") + +(define_insn_reservation "gs464_branch" 1 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "branch,jump,call,condmove,trap")) + "gs464_alu1") + +(define_insn_reservation "gs464_mfhilo" 1 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "mfhi,mflo,mthi,mtlo")) + "gs464_alu2") + +;; Operation imul3nc is fully pipelined. +(define_insn_reservation "gs464_imul3nc" 5 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "imul3nc")) + "gs464_alu2") + +(define_insn_reservation "gs464_imul" 7 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "imul,imadd")) + "gs464_alu2 * 7") + +(define_insn_reservation "gs464_idiv_si" 12 + (and (eq_attr "cpu" "gs464") + (and (eq_attr "type" "idiv") + (eq_attr "mode" "SI"))) + "gs464_alu2 * 12") + +(define_insn_reservation "gs464_idiv_di" 25 + (and (eq_attr "cpu" "gs464") + (and (eq_attr "type" "idiv") + (eq_attr "mode" "DI"))) + "gs464_alu2 * 25") + +(define_insn_reservation "gs464_load" 3 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "load")) + "gs464_mem") + +(define_insn_reservation "gs464_fpload" 4 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "load,mfc,mtc")) + "gs464_mem") + +(define_insn_reservation "gs464_prefetch" 0 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "prefetch,prefetchx")) + "gs464_mem") + +(define_insn_reservation "gs464_store" 0 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "store,fpstore,fpidxstore")) + "gs464_mem") + +;; All the fp operations can be executed in FALU1. Only fp add, +;; sub, mul, madd can be executed in FALU2. Try FALU2 firstly. +(define_insn_reservation "gs464_fadd" 6 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "fadd,fmul,fmadd")) + "gs464_falu2 | gs464_falu1") + +(define_insn_reservation "gs464_fcmp" 2 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "fabs,fcmp,fmove,fneg")) + "gs464_falu1") + +(define_insn_reservation "gs464_fcvt" 4 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "fcvt")) + "gs464_falu1") + +(define_insn_reservation "gs464_fdiv_sf" 12 + (and (eq_attr "cpu" "gs464") + (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt") + (eq_attr "mode" "SF"))) + "gs464_falu1 * 12") + +(define_insn_reservation "gs464_fdiv_df" 19 + (and (eq_attr "cpu" "gs464") + (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt") + (eq_attr "mode" "DF"))) + "gs464_falu1 * 19") + +;; Force single-dispatch for unknown or multi. +(define_insn_reservation "gs464_unknown" 1 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "unknown,multi,atomic,syncloop")) + "gs464_alu1 + gs464_alu2 + gs464_falu1 + gs464_falu2 + gs464_mem") + +;; End of DFA-based pipeline description for gs464 diff --git a/gcc/config/mips/loongson3a.md b/gcc/config/mips/loongson3a.md deleted file mode 100644 index 2ebde68..0000000 --- a/gcc/config/mips/loongson3a.md +++ /dev/null @@ -1,137 +0,0 @@ -;; Pipeline model for Loongson-3A cores. - -;; Copyright (C) 2011-2018 Free Software Foundation, Inc. -;; -;; This file is part of GCC. -;; -;; GCC is free software; you can redistribute it and/or modify it -;; under the terms of the GNU General Public License as published -;; by the Free Software Foundation; either version 3, or (at your -;; option) any later version. -;; -;; GCC is distributed in the hope that it will be useful, but WITHOUT -;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -;; License for more details. -;; -;; You should have received a copy of the GNU General Public License -;; along with GCC; see the file COPYING3. If not see -;; . - -;; Uncomment the following line to output automata for debugging. -;; (automata_option "v") - -;; Automaton for integer instructions. -(define_automaton "ls3a_a_alu") - -;; Automaton for floating-point instructions. -(define_automaton "ls3a_a_falu") - -;; Automaton for memory operations. -(define_automaton "ls3a_a_mem") - -;; Describe the resources. - -(define_cpu_unit "ls3a_alu1" "ls3a_a_alu") -(define_cpu_unit "ls3a_alu2" "ls3a_a_alu") -(define_cpu_unit "ls3a_mem" "ls3a_a_mem") -(define_cpu_unit "ls3a_falu1" "ls3a_a_falu") -(define_cpu_unit "ls3a_falu2" "ls3a_a_falu") - -;; Describe instruction reservations. - -(define_insn_reservation "ls3a_arith" 1 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "arith,clz,const,logical, - move,nop,shift,signext,slt")) - "ls3a_alu1 | ls3a_alu2") - -(define_insn_reservation "ls3a_branch" 1 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "branch,jump,call,condmove,trap")) - "ls3a_alu1") - -(define_insn_reservation "ls3a_mfhilo" 1 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "mfhi,mflo,mthi,mtlo")) - "ls3a_alu2") - -;; Operation imul3nc is fully pipelined. -(define_insn_reservation "ls3a_imul3nc" 5 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "imul3nc")) - "ls3a_alu2") - -(define_insn_reservation "ls3a_imul" 7 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "imul,imadd")) - "ls3a_alu2 * 7") - -(define_insn_reservation "ls3a_idiv_si" 12 - (and (eq_attr "cpu" "loongson_3a") - (and (eq_attr "type" "idiv") - (eq_attr "mode" "SI"))) - "ls3a_alu2 * 12") - -(define_insn_reservation "ls3a_idiv_di" 25 - (and (eq_attr "cpu" "loongson_3a") - (and (eq_attr "type" "idiv") - (eq_attr "mode" "DI"))) - "ls3a_alu2 * 25") - -(define_insn_reservation "ls3a_load" 3 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "load")) - "ls3a_mem") - -(define_insn_reservation "ls3a_fpload" 4 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "load,mfc,mtc")) - "ls3a_mem") - -(define_insn_reservation "ls3a_prefetch" 0 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "prefetch,prefetchx")) - "ls3a_mem") - -(define_insn_reservation "ls3a_store" 0 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "store,fpstore,fpidxstore")) - "ls3a_mem") - -;; All the fp operations can be executed in FALU1. Only fp add, -;; sub, mul, madd can be executed in FALU2. Try FALU2 firstly. -(define_insn_reservation "ls3a_fadd" 6 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "fadd,fmul,fmadd")) - "ls3a_falu2 | ls3a_falu1") - -(define_insn_reservation "ls3a_fcmp" 2 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "fabs,fcmp,fmove,fneg")) - "ls3a_falu1") - -(define_insn_reservation "ls3a_fcvt" 4 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "fcvt")) - "ls3a_falu1") - -(define_insn_reservation "ls3a_fdiv_sf" 12 - (and (eq_attr "cpu" "loongson_3a") - (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt") - (eq_attr "mode" "SF"))) - "ls3a_falu1 * 12") - -(define_insn_reservation "ls3a_fdiv_df" 19 - (and (eq_attr "cpu" "loongson_3a") - (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt") - (eq_attr "mode" "DF"))) - "ls3a_falu1 * 19") - -;; Force single-dispatch for unknown or multi. -(define_insn_reservation "ls3a_unknown" 1 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "unknown,multi,atomic,syncloop")) - "ls3a_alu1 + ls3a_alu2 + ls3a_falu1 + ls3a_falu2 + ls3a_mem") - -;; End of DFA-based pipeline description for loongson_3a diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def index 6a54563..eabe045 100644 --- a/gcc/config/mips/mips-cpus.def +++ b/gcc/config/mips/mips-cpus.def @@ -162,7 +162,8 @@ MIPS_CPU ("sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("xlr", PROCESSOR_XLR, 64, PTF_AVOID_BRANCHLIKELY_SPEED) /* MIPS64 Release 2 processors. */ -MIPS_CPU ("loongson3a", PROCESSOR_LOONGSON_3A, 65, PTF_AVOID_BRANCHLIKELY_SPEED) +MIPS_CPU ("loongson3a", PROCESSOR_GS464, 65, PTF_AVOID_BRANCHLIKELY_SPEED) +MIPS_CPU ("gs464", PROCESSOR_GS464, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("octeon+", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("octeon2", PROCESSOR_OCTEON2, 65, PTF_AVOID_BRANCHLIKELY_SPEED) diff --git a/gcc/config/mips/mips-tables.opt b/gcc/config/mips/mips-tables.opt index 11be463..3114fce 100644 --- a/gcc/config/mips/mips-tables.opt +++ b/gcc/config/mips/mips-tables.opt @@ -679,26 +679,29 @@ EnumValue Enum(mips_arch_opt_value) String(loongson3a) Value(96) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon) Value(97) Canonical +Enum(mips_arch_opt_value) String(gs464) Value(97) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon+) Value(98) Canonical +Enum(mips_arch_opt_value) String(octeon) Value(98) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon2) Value(99) Canonical +Enum(mips_arch_opt_value) String(octeon+) Value(99) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon3) Value(100) Canonical +Enum(mips_arch_opt_value) String(octeon2) Value(100) Canonical EnumValue -Enum(mips_arch_opt_value) String(xlp) Value(101) Canonical +Enum(mips_arch_opt_value) String(octeon3) Value(101) Canonical EnumValue -Enum(mips_arch_opt_value) String(i6400) Value(102) Canonical +Enum(mips_arch_opt_value) String(xlp) Value(102) Canonical EnumValue -Enum(mips_arch_opt_value) String(i6500) Value(103) Canonical +Enum(mips_arch_opt_value) String(i6400) Value(103) Canonical EnumValue -Enum(mips_arch_opt_value) String(p6600) Value(104) Canonical +Enum(mips_arch_opt_value) String(i6500) Value(104) Canonical + +EnumValue +Enum(mips_arch_opt_value) String(p6600) Value(105) Canonical diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 019a6dc..51ae7f8 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -836,7 +836,7 @@ static const struct mips_rtx_cost_data { /* Loongson-2F */ DEFAULT_COSTS }, - { /* Loongson-3A */ + { /* Loongson gs464. */ DEFAULT_COSTS }, { /* M4k */ @@ -14614,7 +14614,7 @@ mips_issue_rate (void) case PROCESSOR_LOONGSON_2E: case PROCESSOR_LOONGSON_2F: - case PROCESSOR_LOONGSON_3A: + case PROCESSOR_GS464: case PROCESSOR_P5600: case PROCESSOR_P6600: return 4; @@ -14746,7 +14746,7 @@ mips_multipass_dfa_lookahead (void) if (TUNE_SB1) return 4; - if (TUNE_LOONGSON_2EF || TUNE_LOONGSON_3A) + if (TUNE_LOONGSON_2EF || TUNE_GS464) return 4; if (TUNE_OCTEON) @@ -20171,16 +20171,18 @@ mips_option_override (void) if (TARGET_LOONGSON_MMI && !TARGET_HARD_FLOAT_ABI) error ("%<-mloongson-mmi%> must be used with %<-mhard-float%>"); - /* Default to enable Loongson MMI on Longson 2e, 2f or 3a target. */ + /* Default to enable Loongson MMI on Longson 2e, 2f or gs464 target. */ if ((target_flags_explicit & MASK_LOONGSON_MMI) == 0 && ((strcmp (mips_arch_info->name, "loongson2e") == 0) || (strcmp (mips_arch_info->name, "loongson2f") == 0) - || (strcmp (mips_arch_info->name, "loongson3a") == 0))) + || (strcmp (mips_arch_info->name, "loongson3a") == 0) + || (strcmp (mips_arch_info->name, "gs464") == 0))) target_flags |= MASK_LOONGSON_MMI; - /* Default to enable Loongson EXT on Longson 3a target. */ + /* Default to enable Loongson EXT on Longson gs464 target. */ if ((target_flags_explicit & MASK_LOONGSON_EXT) == 0 - && (strcmp (mips_arch_info->name, "loongson3a") == 0)) + && ((strcmp (mips_arch_info->name, "loongson3a") == 0) + || (strcmp (mips_arch_info->name, "gs464") == 0))) target_flags |= MASK_LOONGSON_EXT; /* .eh_frame addresses should be the same width as a C pointer. diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index b75646d..6d27c3d 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -266,7 +266,7 @@ struct mips_cpu_info { #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E) #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F) #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F) -#define TARGET_LOONGSON_3A (mips_arch == PROCESSOR_LOONGSON_3A) +#define TARGET_GS464 (mips_arch == PROCESSOR_GS464) #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900) #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000) #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120) @@ -298,7 +298,7 @@ struct mips_cpu_info { || mips_tune == PROCESSOR_74KF3_2) #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \ || mips_tune == PROCESSOR_LOONGSON_2F) -#define TUNE_LOONGSON_3A (mips_tune == PROCESSOR_LOONGSON_3A) +#define TUNE_GS464 (mips_tune == PROCESSOR_GS464) #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000) #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900) #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000) @@ -790,7 +790,8 @@ struct mips_cpu_info { %{march=mips32r6: -mips32r6} \ %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \ |march=xlr: -mips64} \ - %{march=mips64r2|march=loongson3a|march=octeon|march=xlp: -mips64r2} \ + %{march=mips64r2|march=loongson3a|march=gs464|march=octeon \ + |march=xlp: -mips64r2} \ %{march=mips64r3: -mips64r3} \ %{march=mips64r5: -mips64r5} \ %{march=mips64r6|march=i6400|march=i6500|march=p6600: -mips64r6}}" @@ -946,7 +947,7 @@ struct mips_cpu_info { /* ISA has 32 single-precision registers. */ #define ISA_HAS_ODD_SPREG ((mips_isa_rev >= 1 \ - && !TARGET_LOONGSON_3A) \ + && !TARGET_GS464) \ || TARGET_FLOAT64 \ || TARGET_MIPS5900) @@ -989,7 +990,7 @@ struct mips_cpu_info { because the former are faster and can also have the effect of reducing code size. */ #define ISA_AVOID_DIV_HILO ((TARGET_LOONGSON_2EF \ - || TARGET_LOONGSON_3A) \ + || TARGET_GS464) \ && !TARGET_MIPS16) /* ISA supports instructions DDIV and DDIVU. */ @@ -1082,14 +1083,14 @@ struct mips_cpu_info { 'd = [+-] (a * b [+-] c)'. */ #define ISA_HAS_FUSED_MADD4 (mips_madd4 \ && (TARGET_MIPS8000 \ - || TARGET_LOONGSON_3A)) + || TARGET_GS464)) /* ISA has 4 operand unfused madd instructions of the form 'd = [+-] (a * b [+-] c)'. */ #define ISA_HAS_UNFUSED_MADD4 (mips_madd4 \ && ISA_HAS_FP4 \ && !TARGET_MIPS8000 \ - && !TARGET_LOONGSON_3A) + && !TARGET_GS464) /* ISA has 3 operand r6 fused madd instructions of the form 'c = c [+-] (a * b)'. */ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index c8128d4..1ae8f73 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -37,7 +37,7 @@ 74kf3_2 loongson_2e loongson_2f - loongson_3a + gs464 m4k octeon octeon2 @@ -1174,7 +1174,7 @@ (include "9000.md") (include "10000.md") (include "loongson2ef.md") -(include "loongson3a.md") +(include "gs464.md") (include "octeon.md") (include "sb1.md") (include "sr71k.md") diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index e414829..91fe388 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -20552,7 +20552,7 @@ The processor names are: @samp{1004kc}, @samp{1004kf2_1}, @samp{1004kf1_1}, @samp{i6400}, @samp{i6500}, @samp{interaptiv}, -@samp{loongson2e}, @samp{loongson2f}, @samp{loongson3a}, +@samp{loongson2e}, @samp{loongson2f}, @samp{gs464}, @samp{m4k}, @samp{m14k}, @samp{m14kc}, @samp{m14ke}, @samp{m14kec}, @samp{m5100}, @samp{m5101}, -- 1.7.1 From patchwork Mon Sep 3 12:34:33 2018 Content-Type: text/plain; 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3 Sep 2018 12:34:49 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.1 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-oi0-f53.google.com Received: from mail-oi0-f53.google.com (HELO mail-oi0-f53.google.com) (209.85.218.53) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 03 Sep 2018 12:34:46 +0000 Received: by mail-oi0-f53.google.com with SMTP id k81-v6so671160oib.9 for ; Mon, 03 Sep 2018 05:34:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to:cc; bh=ulzVaOqTFQzmm9izlmSqnYKKsRJB3RasDxTMH1hnt48=; b=F8eYiyYv88gGVH91imkHL/fWb8mUQzF0ZLDbgiPQyBhSAZnho88mlP8Y/N+wsPVV13 OpxlttVUeThZ1Uzk37Ru05hC/6g8mrLrjK2NCVDlzJET2y+WgyLfGO7o9xyt1B7Ua1zF kcNdqvYKPiKh1Zq4VxtYvQjzY7DgIzDbR845Xjm2qDAQMJfuRhg3toFrF/5126Zsk0Ga QwM1Q0aSoJxPbjKX+HkxD1U1+2HH3JjLKnDYjcvy/SG85vNL/WjerjZ9jTLNdkqwp6IM PSFaKq+Ee4HUd2A5lPgTYMtLhNllvb4/slFrsczQ6hACky7eMU+MFCcGX4SWrHNX36pE W7HA== MIME-Version: 1.0 From: Paul Hua Date: Mon, 3 Sep 2018 20:34:33 +0800 Message-ID: Subject: [PATCH 5/6] [MIPS] Add Loongson 3A2000/3A3000 processor support To: gcc-patches Cc: Matthew Fortune X-IsSubscribed: yes From 7c7599e473ef5a0e34c7ce192770eaaab7aa2efe Mon Sep 17 00:00:00 2001 From: Chenghua Xu Date: Mon, 3 Sep 2018 19:45:15 +0800 Subject: [PATCH 5/6] [MIPS] Add support for Loongson 3A2000/3A3000 proccessor. gcc/ * config/mips/gs464e.md: New. * config/mips/mips-cpus.def: Define gs464e. * config/mips/mips-tables.opt: Regenerate. * config/mips/mips.c (mips_rtx_cost_data): Add DEFAULT_COSTS for gs464e. (mips_issue_rate): Add support for gs464e. (mips_multipass_dfa_lookahead): Likewise. (mips_option_override): Enable MMI, EXT and EXT2 for gs464e. * config/mips/mips.h: Define TARGET_GS464E and TUNE_GS464E. (MIPS_ISA_LEVEL_SPEC): Infer mips64r2 from gs464e. * config/mips/mips.md: Include gs464e.md. (processor): Add gs464e. * doc/invoke.texi: Add gs464e to supported architectures. --- gcc/config/mips/gs464e.md | 137 +++++++++++++++++++++++++++++++++++++++ gcc/config/mips/mips-cpus.def | 1 + gcc/config/mips/mips-tables.opt | 19 +++-- gcc/config/mips/mips.c | 22 +++++-- gcc/config/mips/mips.h | 4 +- gcc/config/mips/mips.md | 2 + gcc/doc/invoke.texi | 2 +- 7 files changed, 172 insertions(+), 15 deletions(-) create mode 100644 gcc/config/mips/gs464e.md diff --git a/gcc/config/mips/gs464e.md b/gcc/config/mips/gs464e.md new file mode 100644 index 0000000..e2ef37d --- /dev/null +++ b/gcc/config/mips/gs464e.md @@ -0,0 +1,137 @@ +;; Pipeline model for Loongson gs464e cores. + +;; Copyright (C) 2011-2018 Free Software Foundation, Inc. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 3, or (at your +;; option) any later version. +;; +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +;; Uncomment the following line to output automata for debugging. +;; (automata_option "v") + +;; Automaton for integer instructions. +(define_automaton "gs464e_a_alu") + +;; Automaton for floating-point instructions. +(define_automaton "gs464e_a_falu") + +;; Automaton for memory operations. +(define_automaton "gs464e_a_mem") + +;; Describe the resources. + +(define_cpu_unit "gs464e_alu1" "gs464e_a_alu") +(define_cpu_unit "gs464e_alu2" "gs464e_a_alu") +(define_cpu_unit "gs464e_mem1" "gs464e_a_mem") +(define_cpu_unit "gs464e_mem2" "gs464e_a_mem") +(define_cpu_unit "gs464e_falu1" "gs464e_a_falu") +(define_cpu_unit "gs464e_falu2" "gs464e_a_falu") + +;; Describe instruction reservations. + +(define_insn_reservation "gs464e_arith" 1 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "arith,clz,const,logical, + move,nop,shift,signext,slt")) + "gs464e_alu1 | gs464e_alu2") + +(define_insn_reservation "gs464e_branch" 1 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "branch,jump,call,condmove,trap")) + "gs464e_alu1 | gs464e_alu2") + +(define_insn_reservation "gs464e_mfhilo" 1 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "mfhi,mflo,mthi,mtlo")) + "gs464e_alu1 | gs464e_alu2") + +;; Operation imul3nc is fully pipelined. +(define_insn_reservation "gs464e_imul3nc" 5 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "imul3nc")) + "gs464e_alu1 | gs464e_alu2") + +(define_insn_reservation "gs464e_imul" 7 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "imul,imadd")) + "gs464e_alu1 | gs464e_alu2") + +(define_insn_reservation "gs464e_idiv_si" 12 + (and (eq_attr "cpu" "gs464e") + (and (eq_attr "type" "idiv") + (eq_attr "mode" "SI"))) + "gs464e_alu1 | gs464e_alu2") + +(define_insn_reservation "gs464e_idiv_di" 25 + (and (eq_attr "cpu" "gs464e") + (and (eq_attr "type" "idiv") + (eq_attr "mode" "DI"))) + "gs464e_alu1 | gs464e_alu2") + +(define_insn_reservation "gs464e_load" 4 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "load")) + "gs464e_mem1 | gs464e_mem2") + +(define_insn_reservation "gs464e_fpload" 5 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "load,mfc,mtc")) + "gs464e_mem1 | gs464e_mem2") + +(define_insn_reservation "gs464e_prefetch" 0 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "prefetch,prefetchx")) + "gs464e_mem1 | gs464e_mem2") + +(define_insn_reservation "gs464e_store" 0 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "store,fpstore,fpidxstore")) + "gs464e_mem1 | gs464e_mem2") + +(define_insn_reservation "gs464e_fadd" 4 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "fadd,fmul,fmadd")) + "gs464e_falu1 | gs464e_falu2") + +(define_insn_reservation "gs464e_fcmp" 2 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "fabs,fcmp,fmove,fneg")) + "gs464e_falu1 | gs464e_falu2") + +(define_insn_reservation "gs464e_fcvt" 4 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "fcvt")) + "gs464e_falu1 | gs464e_falu2") + +(define_insn_reservation "gs464e_fdiv_sf" 12 + (and (eq_attr "cpu" "gs464e") + (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt") + (eq_attr "mode" "SF"))) + "gs464e_falu1 | gs464e_falu2") + +(define_insn_reservation "gs464e_fdiv_df" 19 + (and (eq_attr "cpu" "gs464e") + (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt") + (eq_attr "mode" "DF"))) + "gs464e_falu1 | gs464e_falu2") + +;; Force single-dispatch for unknown or multi. +(define_insn_reservation "gs464e_unknown" 1 + (and (eq_attr "cpu" "gs464e") + (eq_attr "type" "unknown,multi,atomic,syncloop")) + "gs464e_alu1 + gs464e_alu2 + gs464e_falu1 + + gs464e_falu2 + gs464e_mem1 + gs464e_mem2") + +;; End of DFA-based pipeline description for gs464e diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def index eabe045..b05b455 100644 --- a/gcc/config/mips/mips-cpus.def +++ b/gcc/config/mips/mips-cpus.def @@ -164,6 +164,7 @@ MIPS_CPU ("xlr", PROCESSOR_XLR, 64, PTF_AVOID_BRANCHLIKELY_SPEED) /* MIPS64 Release 2 processors. */ MIPS_CPU ("loongson3a", PROCESSOR_GS464, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("gs464", PROCESSOR_GS464, 65, PTF_AVOID_BRANCHLIKELY_SPEED) +MIPS_CPU ("gs464e", PROCESSOR_GS464E, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("octeon+", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("octeon2", PROCESSOR_OCTEON2, 65, PTF_AVOID_BRANCHLIKELY_SPEED) diff --git a/gcc/config/mips/mips-tables.opt b/gcc/config/mips/mips-tables.opt index 3114fce..539266a 100644 --- a/gcc/config/mips/mips-tables.opt +++ b/gcc/config/mips/mips-tables.opt @@ -682,26 +682,29 @@ EnumValue Enum(mips_arch_opt_value) String(gs464) Value(97) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon) Value(98) Canonical +Enum(mips_arch_opt_value) String(gs464e) Value(98) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon+) Value(99) Canonical +Enum(mips_arch_opt_value) String(octeon) Value(99) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon2) Value(100) Canonical +Enum(mips_arch_opt_value) String(octeon+) Value(100) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon3) Value(101) Canonical +Enum(mips_arch_opt_value) String(octeon2) Value(101) Canonical EnumValue -Enum(mips_arch_opt_value) String(xlp) Value(102) Canonical +Enum(mips_arch_opt_value) String(octeon3) Value(102) Canonical EnumValue -Enum(mips_arch_opt_value) String(i6400) Value(103) Canonical +Enum(mips_arch_opt_value) String(xlp) Value(103) Canonical EnumValue -Enum(mips_arch_opt_value) String(i6500) Value(104) Canonical +Enum(mips_arch_opt_value) String(i6400) Value(104) Canonical EnumValue -Enum(mips_arch_opt_value) String(p6600) Value(105) Canonical +Enum(mips_arch_opt_value) String(i6500) Value(105) Canonical + +EnumValue +Enum(mips_arch_opt_value) String(p6600) Value(106) Canonical diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 51ae7f8..e6fd0ca 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -839,6 +839,9 @@ static const struct mips_rtx_cost_data { /* Loongson gs464. */ DEFAULT_COSTS }, + { /* Loongson gs464e. */ + DEFAULT_COSTS + }, { /* M4k */ DEFAULT_COSTS }, @@ -14615,6 +14618,7 @@ mips_issue_rate (void) case PROCESSOR_LOONGSON_2E: case PROCESSOR_LOONGSON_2F: case PROCESSOR_GS464: + case PROCESSOR_GS464E: case PROCESSOR_P5600: case PROCESSOR_P6600: return 4; @@ -14746,7 +14750,7 @@ mips_multipass_dfa_lookahead (void) if (TUNE_SB1) return 4; - if (TUNE_LOONGSON_2EF || TUNE_GS464) + if (TUNE_LOONGSON_2EF || TUNE_GS464 || TUNE_GS464E) return 4; if (TUNE_OCTEON) @@ -20171,20 +20175,28 @@ mips_option_override (void) if (TARGET_LOONGSON_MMI && !TARGET_HARD_FLOAT_ABI) error ("%<-mloongson-mmi%> must be used with %<-mhard-float%>"); - /* Default to enable Loongson MMI on Longson 2e, 2f or gs464 target. */ + /* Default to enable Loongson MMI on Longson 2e, 2f, gs464 + * or gs464e target. */ if ((target_flags_explicit & MASK_LOONGSON_MMI) == 0 && ((strcmp (mips_arch_info->name, "loongson2e") == 0) || (strcmp (mips_arch_info->name, "loongson2f") == 0) || (strcmp (mips_arch_info->name, "loongson3a") == 0) - || (strcmp (mips_arch_info->name, "gs464") == 0))) + || (strcmp (mips_arch_info->name, "gs464") == 0) + || (strcmp (mips_arch_info->name, "gs464e") == 0))) target_flags |= MASK_LOONGSON_MMI; - /* Default to enable Loongson EXT on Longson gs464 target. */ + /* Default to enable Loongson EXT on Longson gs464 or gs464e target. */ if ((target_flags_explicit & MASK_LOONGSON_EXT) == 0 && ((strcmp (mips_arch_info->name, "loongson3a") == 0) - || (strcmp (mips_arch_info->name, "gs464") == 0))) + || (strcmp (mips_arch_info->name, "gs464") == 0) + || (strcmp (mips_arch_info->name, "gs464e") == 0))) target_flags |= MASK_LOONGSON_EXT; + /* Default to enable Loongson EXT2 on gs464e target. */ + if ((target_flags_explicit & MASK_LOONGSON_EXT2) == 0 + && (strcmp (mips_arch_info->name, "gs464e") == 0)) + target_flags |= MASK_LOONGSON_EXT2; + /* .eh_frame addresses should be the same width as a C pointer. Most MIPS ABIs support only one pointer size, so the assembler will usually know exactly how big an .eh_frame address is. diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 6d27c3d..42023e5 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -267,6 +267,7 @@ struct mips_cpu_info { #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F) #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F) #define TARGET_GS464 (mips_arch == PROCESSOR_GS464) +#define TARGET_GS464E (mips_arch == PROCESSOR_GS464E) #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900) #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000) #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120) @@ -299,6 +300,7 @@ struct mips_cpu_info { #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \ || mips_tune == PROCESSOR_LOONGSON_2F) #define TUNE_GS464 (mips_tune == PROCESSOR_GS464) +#define TUNE_GS464E (mips_tune == PROCESSOR_GS464E) #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000) #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900) #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000) @@ -790,7 +792,7 @@ struct mips_cpu_info { %{march=mips32r6: -mips32r6} \ %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \ |march=xlr: -mips64} \ - %{march=mips64r2|march=loongson3a|march=gs464|march=octeon \ + %{march=mips64r2|march=loongson3a|march=gs464|march=gs464e|march=octeon \ |march=xlp: -mips64r2} \ %{march=mips64r3: -mips64r3} \ %{march=mips64r5: -mips64r5} \ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 1ae8f73..15f0e47 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -38,6 +38,7 @@ loongson_2e loongson_2f gs464 + gs464e m4k octeon octeon2 @@ -1175,6 +1176,7 @@ (include "10000.md") (include "loongson2ef.md") (include "gs464.md") +(include "gs464e.md") (include "octeon.md") (include "sb1.md") (include "sr71k.md") diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 91fe388..fd0ba4c 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -20552,7 +20552,7 @@ The processor names are: @samp{1004kc}, @samp{1004kf2_1}, @samp{1004kf1_1}, @samp{i6400}, @samp{i6500}, @samp{interaptiv}, -@samp{loongson2e}, @samp{loongson2f}, @samp{gs464}, +@samp{loongson2e}, @samp{loongson2f}, @samp{gs464}, @samp{gs464e}, @samp{m4k}, @samp{m14k}, @samp{m14kc}, @samp{m14ke}, @samp{m14kec}, @samp{m5100}, @samp{m5101}, -- 1.7.1 From patchwork Mon Sep 3 12:36:33 2018 Content-Type: text/plain; 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3 Sep 2018 12:36:49 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.1 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-oi0-f42.google.com Received: from mail-oi0-f42.google.com (HELO mail-oi0-f42.google.com) (209.85.218.42) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 03 Sep 2018 12:36:46 +0000 Received: by mail-oi0-f42.google.com with SMTP id c190-v6so710398oig.6 for ; Mon, 03 Sep 2018 05:36:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to:cc; bh=3zee87wEtHgG8/BLkoUmMG95xdXihGZUXMpuYJDeKdU=; b=qmLTa3/0TwpSCZ+JCp28koV4sT0tsiRSVqGH0I3BhS1wbDTNe0pe5vz7uDHjRja/fc Q+XohTxqEzvyMoCPv5KIn7Q819Dcg6Mp6hI91sOM14dD482Lz8hCs5RAublbqZIktiCT a+MkBm0zCDXhQyJponMHVT4Cy0Cq2gI07zYdD+eQKM5maQnXSr/Xv7+aPrvRdKzT0wS0 ezg8/NoKNnllMKk2YpAl6lc585YtgvK4YVPczI9PoseQbmxe/CaePD/lW4a21P/6Ckmr mXN2uF03hzH6NLJ2FDhZUaYutF7nNNJ4MnWGt7DdCp/4wLKOu/ix+iMkUxsr5iDkYxSA oWqw== MIME-Version: 1.0 From: Paul Hua Date: Mon, 3 Sep 2018 20:36:33 +0800 Message-ID: Subject: [PATCH 6/6] [MIPS] Add Loongson 2K1000 processor support To: gcc-patches Cc: Matthew Fortune X-IsSubscribed: yes From a33230a02948e614e9c5c3a310cf9bdd0968aefc Mon Sep 17 00:00:00 2001 From: Chenghua Xu Date: Mon, 3 Sep 2018 20:01:54 +0800 Subject: [PATCH 6/6] [MIPS] Add support for Loongson 2K1000 proccessor. gcc/ * config/mips/gs264e.md: New. * config/mips/mips-cpus.def: Define gs264e. * config/mips/mips-tables.opt: Regenerate. * config/mips/mips.c (mips_rtx_cost_data): Add DEFAULT_COSTS for gs264e. (mips_issue_rate): Add support for gs264e. (mips_multipass_dfa_lookahead): Likewise. (mips_option_override): Enable MMI, EXT, EXT2 and MSA for gs264e. * config/mips/mips.h: Define TARGET_GS264E and TUNE_GS264E. (MIPS_ISA_LEVEL_SPEC): Infer mips64r2 from gs464e. * config/mips/mips.md: Include gs264e.md. (processor): Add gs264e. * config/mips/mips.opt (MSA): Use Mask instead of Var. * doc/invoke.texi: Add gs264e to supported architectures. --- gcc/config/mips/gs264e.md | 133 +++++++++++++++++++++++++++++++++++++++ gcc/config/mips/mips-cpus.def | 1 + gcc/config/mips/mips-tables.opt | 19 +++--- gcc/config/mips/mips.c | 29 ++++++--- gcc/config/mips/mips.h | 6 +- gcc/config/mips/mips.md | 2 + gcc/config/mips/mips.opt | 2 +- gcc/doc/invoke.texi | 1 + 8 files changed, 174 insertions(+), 19 deletions(-) create mode 100644 gcc/config/mips/gs264e.md diff --git a/gcc/config/mips/gs264e.md b/gcc/config/mips/gs264e.md new file mode 100644 index 0000000..9b30bb5 --- /dev/null +++ b/gcc/config/mips/gs264e.md @@ -0,0 +1,133 @@ +;; Pipeline model for Loongson gs264e cores. + +;; Copyright (C) 2011-2018 Free Software Foundation, Inc. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 3, or (at your +;; option) any later version. +;; +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +;; Uncomment the following line to output automata for debugging. +;; (automata_option "v") + +;; Automaton for integer instructions. +(define_automaton "gs264e_a_alu") + +;; Automaton for floating-point instructions. +(define_automaton "gs264e_a_falu") + +;; Automaton for memory operations. +(define_automaton "gs264e_a_mem") + +;; Describe the resources. + +(define_cpu_unit "gs264e_alu1" "gs264e_a_alu") +(define_cpu_unit "gs264e_mem1" "gs264e_a_mem") +(define_cpu_unit "gs264e_falu1" "gs264e_a_falu") + +;; Describe instruction reservations. + +(define_insn_reservation "gs264e_arith" 1 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "arith,clz,const,logical, + move,nop,shift,signext,slt")) + "gs264e_alu1") + +(define_insn_reservation "gs264e_branch" 1 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "branch,jump,call,condmove,trap")) + "gs264e_alu1") + +(define_insn_reservation "gs264e_mfhilo" 1 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "mfhi,mflo,mthi,mtlo")) + "gs264e_alu1") + +;; Operation imul3nc is fully pipelined. +(define_insn_reservation "gs264e_imul3nc" 7 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "imul3nc")) + "gs264e_alu1") + +(define_insn_reservation "gs264e_imul" 7 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "imul,imadd")) + "gs264e_alu1") + +(define_insn_reservation "gs264e_idiv_si" 12 + (and (eq_attr "cpu" "gs264e") + (and (eq_attr "type" "idiv") + (eq_attr "mode" "SI"))) + "gs264e_alu1") + +(define_insn_reservation "gs264e_idiv_di" 25 + (and (eq_attr "cpu" "gs264e") + (and (eq_attr "type" "idiv") + (eq_attr "mode" "DI"))) + "gs264e_alu1") + +(define_insn_reservation "gs264e_load" 4 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "load")) + "gs264e_mem1") + +(define_insn_reservation "gs264e_fpload" 4 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "load,mfc,mtc")) + "gs264e_mem1") + +(define_insn_reservation "gs264e_prefetch" 0 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "prefetch,prefetchx")) + "gs264e_mem1") + +(define_insn_reservation "gs264e_store" 0 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "store,fpstore,fpidxstore")) + "gs264e_mem1") + +(define_insn_reservation "gs264e_fadd" 4 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "fadd,fmul,fmadd")) + "gs264e_falu1") + +(define_insn_reservation "gs264e_fcmp" 2 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "fabs,fcmp,fmove,fneg")) + "gs264e_falu1") + +(define_insn_reservation "gs264e_fcvt" 4 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "fcvt")) + "gs264e_falu1") + +(define_insn_reservation "gs264e_fdiv_sf" 12 + (and (eq_attr "cpu" "gs264e") + (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt") + (eq_attr "mode" "SF"))) + "gs264e_falu1") + +(define_insn_reservation "gs264e_fdiv_df" 19 + (and (eq_attr "cpu" "gs264e") + (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt") + (eq_attr "mode" "DF"))) + "gs264e_falu1") + +;; Force single-dispatch for unknown or multi. +(define_insn_reservation "gs264e_unknown" 1 + (and (eq_attr "cpu" "gs264e") + (eq_attr "type" "unknown,multi,atomic,syncloop")) + "gs264e_alu1 + gs264e_falu1 + gs264e_mem1") + +;; End of DFA-based pipeline description for gs264e diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def index b05b455..747739f 100644 --- a/gcc/config/mips/mips-cpus.def +++ b/gcc/config/mips/mips-cpus.def @@ -165,6 +165,7 @@ MIPS_CPU ("xlr", PROCESSOR_XLR, 64, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("loongson3a", PROCESSOR_GS464, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("gs464", PROCESSOR_GS464, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("gs464e", PROCESSOR_GS464E, 65, PTF_AVOID_BRANCHLIKELY_SPEED) +MIPS_CPU ("gs264e", PROCESSOR_GS264E, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("octeon+", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("octeon2", PROCESSOR_OCTEON2, 65, PTF_AVOID_BRANCHLIKELY_SPEED) diff --git a/gcc/config/mips/mips-tables.opt b/gcc/config/mips/mips-tables.opt index 539266a..7ab2cf5 100644 --- a/gcc/config/mips/mips-tables.opt +++ b/gcc/config/mips/mips-tables.opt @@ -685,26 +685,29 @@ EnumValue Enum(mips_arch_opt_value) String(gs464e) Value(98) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon) Value(99) Canonical +Enum(mips_arch_opt_value) String(gs264e) Value(99) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon+) Value(100) Canonical +Enum(mips_arch_opt_value) String(octeon) Value(100) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon2) Value(101) Canonical +Enum(mips_arch_opt_value) String(octeon+) Value(101) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon3) Value(102) Canonical +Enum(mips_arch_opt_value) String(octeon2) Value(102) Canonical EnumValue -Enum(mips_arch_opt_value) String(xlp) Value(103) Canonical +Enum(mips_arch_opt_value) String(octeon3) Value(103) Canonical EnumValue -Enum(mips_arch_opt_value) String(i6400) Value(104) Canonical +Enum(mips_arch_opt_value) String(xlp) Value(104) Canonical EnumValue -Enum(mips_arch_opt_value) String(i6500) Value(105) Canonical +Enum(mips_arch_opt_value) String(i6400) Value(105) Canonical EnumValue -Enum(mips_arch_opt_value) String(p6600) Value(106) Canonical +Enum(mips_arch_opt_value) String(i6500) Value(106) Canonical + +EnumValue +Enum(mips_arch_opt_value) String(p6600) Value(107) Canonical diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index e6fd0ca..cf15777 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -842,6 +842,9 @@ static const struct mips_rtx_cost_data { /* Loongson gs464e. */ DEFAULT_COSTS }, + { /* Loongson gs264e. */ + DEFAULT_COSTS + }, { /* M4k */ DEFAULT_COSTS }, @@ -14605,6 +14608,7 @@ mips_issue_rate (void) case PROCESSOR_OCTEON2: case PROCESSOR_OCTEON3: case PROCESSOR_I6400: + case PROCESSOR_GS264E: return 2; case PROCESSOR_SB1: @@ -14753,7 +14757,7 @@ mips_multipass_dfa_lookahead (void) if (TUNE_LOONGSON_2EF || TUNE_GS464 || TUNE_GS464E) return 4; - if (TUNE_OCTEON) + if (TUNE_OCTEON || TUNE_GS264E) return 2; if (TUNE_P5600 || TUNE_P6600 || TUNE_I6400) @@ -20175,28 +20179,37 @@ mips_option_override (void) if (TARGET_LOONGSON_MMI && !TARGET_HARD_FLOAT_ABI) error ("%<-mloongson-mmi%> must be used with %<-mhard-float%>"); - /* Default to enable Loongson MMI on Longson 2e, 2f, gs464 - * or gs464e target. */ + /* Default to enable Loongson MMI on Longson 2e, 2f, gs464, gs464e + * or gs264e target. */ if ((target_flags_explicit & MASK_LOONGSON_MMI) == 0 && ((strcmp (mips_arch_info->name, "loongson2e") == 0) || (strcmp (mips_arch_info->name, "loongson2f") == 0) || (strcmp (mips_arch_info->name, "loongson3a") == 0) || (strcmp (mips_arch_info->name, "gs464") == 0) - || (strcmp (mips_arch_info->name, "gs464e") == 0))) + || (strcmp (mips_arch_info->name, "gs464e") == 0) + || (strcmp (mips_arch_info->name, "gs264e") == 0))) target_flags |= MASK_LOONGSON_MMI; - /* Default to enable Loongson EXT on Longson gs464 or gs464e target. */ + /* Default to enable Loongson EXT on Longson gs464, gs464e + * or gs264e target. */ if ((target_flags_explicit & MASK_LOONGSON_EXT) == 0 && ((strcmp (mips_arch_info->name, "loongson3a") == 0) || (strcmp (mips_arch_info->name, "gs464") == 0) - || (strcmp (mips_arch_info->name, "gs464e") == 0))) + || (strcmp (mips_arch_info->name, "gs464e") == 0) + || (strcmp (mips_arch_info->name, "gs264e") == 0))) target_flags |= MASK_LOONGSON_EXT; - /* Default to enable Loongson EXT2 on gs464e target. */ + /* Default to enable Loongson EXT2 on gs464e or gs264e target. */ if ((target_flags_explicit & MASK_LOONGSON_EXT2) == 0 - && (strcmp (mips_arch_info->name, "gs464e") == 0)) + && ((strcmp (mips_arch_info->name, "gs464e") == 0) + || (strcmp (mips_arch_info->name, "gs264e") == 0))) target_flags |= MASK_LOONGSON_EXT2; + /* Default to enable MSA on gs264e target. */ + if ((target_flags_explicit & MASK_MSA) == 0 + && (strcmp (mips_arch_info->name, "gs264e") == 0)) + target_flags |= MASK_MSA; + /* .eh_frame addresses should be the same width as a C pointer. Most MIPS ABIs support only one pointer size, so the assembler will usually know exactly how big an .eh_frame address is. diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 42023e5..12c8156 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -268,6 +268,7 @@ struct mips_cpu_info { #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F) #define TARGET_GS464 (mips_arch == PROCESSOR_GS464) #define TARGET_GS464E (mips_arch == PROCESSOR_GS464E) +#define TARGET_GS264E (mips_arch == PROCESSOR_GS264E) #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900) #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000) #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120) @@ -301,6 +302,7 @@ struct mips_cpu_info { || mips_tune == PROCESSOR_LOONGSON_2F) #define TUNE_GS464 (mips_tune == PROCESSOR_GS464) #define TUNE_GS464E (mips_tune == PROCESSOR_GS464E) +#define TUNE_GS264E (mips_tune == PROCESSOR_GS264E) #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000) #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900) #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000) @@ -792,8 +794,8 @@ struct mips_cpu_info { %{march=mips32r6: -mips32r6} \ %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \ |march=xlr: -mips64} \ - %{march=mips64r2|march=loongson3a|march=gs464|march=gs464e|march=octeon \ - |march=xlp: -mips64r2} \ + %{march=mips64r2|march=loongson3a|march=gs464|march=gs464e|march=gs264e \ + |march=octeon|march=xlp: -mips64r2} \ %{march=mips64r3: -mips64r3} \ %{march=mips64r5: -mips64r5} \ %{march=mips64r6|march=i6400|march=i6500|march=p6600: -mips64r6}}" diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 15f0e47..6ff75ea 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -39,6 +39,7 @@ loongson_2f gs464 gs464e + gs264e m4k octeon octeon2 @@ -1177,6 +1178,7 @@ (include "loongson2ef.md") (include "gs464.md") (include "gs464e.md") +(include "gs264e.md") (include "octeon.md") (include "sb1.md") (include "sr71k.md") diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index c0c8005..16c33d1 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -300,7 +300,7 @@ Target Report Mask(MICROMIPS) Use microMIPS instructions. mmsa -Target Report Var(TARGET_MSA) +Target Report Mask(MSA) Use MIPS MSA Extension instructions. mmt diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index fd0ba4c..3a31079 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -20553,6 +20553,7 @@ The processor names are: @samp{i6400}, @samp{i6500}, @samp{interaptiv}, @samp{loongson2e}, @samp{loongson2f}, @samp{gs464}, @samp{gs464e}, +@samp{gs264e}, @samp{m4k}, @samp{m14k}, @samp{m14kc}, @samp{m14ke}, @samp{m14kec}, @samp{m5100}, @samp{m5101}, -- 1.7.1