From patchwork Fri Aug 31 14:01:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 964463 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="Dt9Brbi5"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 4221K20WJyz9rvt for ; Sat, 1 Sep 2018 00:02:45 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728713AbeHaSKV (ORCPT ); Fri, 31 Aug 2018 14:10:21 -0400 Received: from mail-wr1-f67.google.com ([209.85.221.67]:40966 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728735AbeHaSJn (ORCPT ); Fri, 31 Aug 2018 14:09:43 -0400 Received: by mail-wr1-f67.google.com with SMTP id z96-v6so11330784wrb.8 for ; Fri, 31 Aug 2018 07:02:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=j1YcuxG9rYHAsbs3iLSfV/3gBH5qWeeY6yGsufYQHUY=; b=Dt9Brbi5I5sdMsfu8+0SKCz2VnhOlZFHylNdZCS4BNpdZ00ttGxIKxHL+vdIN5Q7HU brAvQlQKoBUxjJPKXhyztt922ZlgD2X0Jj//CHpiumV6yiwwe8vwG/akynmtEi99YBhz qKh9JZhi+Bjy5HShCgI5y+V6gfYBm0DuwmMtc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=j1YcuxG9rYHAsbs3iLSfV/3gBH5qWeeY6yGsufYQHUY=; b=pI8RpjsYbIdV8/jiKQUvgchqElvutGb1e0UoO1Y36Td2GmCkIkv5vtVfYgaGL/V+Z5 HF7/Sd7Xjt7Xs5EcODEEozMBImTmkpMlVaVa5roxIxaBjI4xeT4TGh+qn+gXkg/z0Ohc vwpNogsnKHaILKnY548kvfcEWzt3BwD0KRWcv/Bt12Voc7mC/NP6BecdXDl2LPM/ZM0j 4ptG82+/0XynQWFO2oU6krwQbMrWfyGgr4RhjrsUdTi/MQ8LU29ug/fCmghJBTi78F95 ZSpGnBekRxOtX/xOA7IEqQqTTs4SmebDFANfTcDLDPjkxDqVTQQEtNUiPZQBUeIGjZhL 3ruA== X-Gm-Message-State: APzg51DbKh1nzqDzEVsu/NwqgcpPs065uTzE2pbJc658iJGpjnVmSeCm mYuYP8j20cdXfptbJQedgBjxrA== X-Google-Smtp-Source: ANB0VdZg987v8lageIp6CW8zebXDC+lcpIhLtnl9JlZ0u9B8wDsSgvK6HTLVoa9MZZX6acgukuQfYA== X-Received: by 2002:adf:f648:: with SMTP id x8-v6mr11283757wrp.144.1535724124066; Fri, 31 Aug 2018 07:02:04 -0700 (PDT) Received: from localhost.localdomain ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id m68-v6sm8624513wmb.10.2018.08.31.07.02.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 31 Aug 2018 07:02:02 -0700 (PDT) From: Georgi Djakov To: linux-pm@vger.kernel.org, gregkh@linuxfoundation.org Cc: rjw@rjwysocki.net, robh+dt@kernel.org, mturquette@baylibre.com, khilman@baylibre.com, vincent.guittot@linaro.org, skannan@codeaurora.org, bjorn.andersson@linaro.org, amit.kucheria@linaro.org, seansw@qti.qualcomm.com, daidavid1@codeaurora.org, evgreen@chromium.org, mark.rutland@arm.com, lorenzo.pieralisi@arm.com, abailon@baylibre.com, maxime.ripard@bootlin.com, arnd@arndb.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH v9 5/8] interconnect: qcom: Add RPM communication Date: Fri, 31 Aug 2018 17:01:48 +0300 Message-Id: <20180831140151.13972-6-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180831140151.13972-1-georgi.djakov@linaro.org> References: <20180831140151.13972-1-georgi.djakov@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On some Qualcomm SoCs, there is a remote processor, which controls some of the Network-On-Chip interconnect resources. Other CPUs express their needs by communicating with this processor. Add a driver to handle communication with this remote processor. Signed-off-by: Georgi Djakov Reviewed-by: Evan Green --- .../bindings/interconnect/qcom-smd.txt | 32 +++++++ drivers/interconnect/qcom/Kconfig | 13 +++ drivers/interconnect/qcom/Makefile | 5 + drivers/interconnect/qcom/smd-rpm.c | 91 +++++++++++++++++++ drivers/interconnect/qcom/smd-rpm.h | 15 +++ 5 files changed, 156 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom-smd.txt create mode 100644 drivers/interconnect/qcom/Kconfig create mode 100644 drivers/interconnect/qcom/Makefile create mode 100644 drivers/interconnect/qcom/smd-rpm.c create mode 100644 drivers/interconnect/qcom/smd-rpm.h diff --git a/Documentation/devicetree/bindings/interconnect/qcom-smd.txt b/Documentation/devicetree/bindings/interconnect/qcom-smd.txt new file mode 100644 index 000000000000..2325167f6eaf --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom-smd.txt @@ -0,0 +1,32 @@ +Qualcomm SMD-RPM interconnect driver binding +------------------------------------------------ +The RPM (Resource Power Manager) is a dedicated hardware engine +for managing the shared SoC resources in order to keep the lowest +power profile. It communicates with other hardware subsystems via +the shared memory driver (SMD) back-end and accepts requests for +various resources. + +Required properties : +- compatible : shall contain only one of the following: + "qcom,interconnect-smd-rpm" + +Example: + smd { + compatible = "qcom,smd"; + + rpm { + interrupts = ; + qcom,ipc = <&apcs 8 0>; + qcom,smd-edge = <15>; + + rpm_requests { + compatible = "qcom,rpm-msm8916"; + qcom,smd-channels = "rpm_requests"; + + interconnect-smd-rpm { + compatible = "qcom,interconnect-smd-rpm"; + }; + + }; + }; + }; diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig new file mode 100644 index 000000000000..6146552fac86 --- /dev/null +++ b/drivers/interconnect/qcom/Kconfig @@ -0,0 +1,13 @@ +config INTERCONNECT_QCOM + bool "Qualcomm Network-on-Chip interconnect drivers" + depends on ARCH_QCOM + help + Support for Qualcomm's Network-on-Chip interconnect hardware. + +config INTERCONNECT_QCOM_SMD_RPM + tristate "Qualcomm SMD RPM interconnect driver" + depends on INTERCONNECT_QCOM + depends on QCOM_SMD_RPM + help + This is a driver for communicating interconnect related configuration + details with a remote processor (RPM) on Qualcomm platforms. diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile new file mode 100644 index 000000000000..f4477ad22ba2 --- /dev/null +++ b/drivers/interconnect/qcom/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 + +qnoc-smd-rpm-objs := smd-rpm.o + +obj-$(CONFIG_INTERCONNECT_QCOM_SMD_RPM) += qnoc-smd-rpm.o diff --git a/drivers/interconnect/qcom/smd-rpm.c b/drivers/interconnect/qcom/smd-rpm.c new file mode 100644 index 000000000000..48b7a2a6eb84 --- /dev/null +++ b/drivers/interconnect/qcom/smd-rpm.c @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RPM over SMD communication wrapper for interconnects + * + * Copyright (C) 2018 Linaro Ltd + * Author: Georgi Djakov + */ + +#include +#include +#include +#include +#include +#include +#include "smd-rpm.h" + +#define RPM_KEY_BW 0x00007762 + +static struct qcom_icc_rpm { + struct qcom_smd_rpm *rpm; +} icc_rpm_smd; + +struct icc_rpm_smd_req { + __le32 key; + __le32 nbytes; + __le32 value; +}; + +bool qcom_icc_rpm_smd_available(void) +{ + if (!icc_rpm_smd.rpm) + return false; + + return true; +} +EXPORT_SYMBOL_GPL(qcom_icc_rpm_smd_available); + +int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u32 val) +{ + struct icc_rpm_smd_req req = { + .key = cpu_to_le32(RPM_KEY_BW), + .nbytes = cpu_to_le32(sizeof(u32)), + .value = cpu_to_le32(val), + }; + + return qcom_rpm_smd_write(icc_rpm_smd.rpm, ctx, rsc_type, id, &req, + sizeof(req)); +} +EXPORT_SYMBOL_GPL(qcom_icc_rpm_smd_send); + +static int qcom_icc_rpm_smd_probe(struct platform_device *pdev) +{ + icc_rpm_smd.rpm = dev_get_drvdata(pdev->dev.parent); + if (!icc_rpm_smd.rpm) { + dev_err(&pdev->dev, "unable to retrieve handle to RPM\n"); + return -ENODEV; + } + + return 0; +} + +static const struct of_device_id qcom_icc_rpm_smd_dt_match[] = { + { .compatible = "qcom,interconnect-smd-rpm", }, + { }, +}; + +MODULE_DEVICE_TABLE(of, qcom_icc_rpm_smd_dt_match); + +static struct platform_driver qcom_interconnect_rpm_smd_driver = { + .driver = { + .name = "qcom-interconnect-smd-rpm", + .of_match_table = qcom_icc_rpm_smd_dt_match, + }, + .probe = qcom_icc_rpm_smd_probe, +}; + +static int __init rpm_smd_interconnect_init(void) +{ + return platform_driver_register(&qcom_interconnect_rpm_smd_driver); +} +subsys_initcall(rpm_smd_interconnect_init); + +static void __exit rpm_smd_interconnect_exit(void) +{ + platform_driver_unregister(&qcom_interconnect_rpm_smd_driver); +} +module_exit(rpm_smd_interconnect_exit) + +MODULE_AUTHOR("Georgi Djakov "); +MODULE_DESCRIPTION("Qualcomm SMD RPM interconnect driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/interconnect/qcom/smd-rpm.h b/drivers/interconnect/qcom/smd-rpm.h new file mode 100644 index 000000000000..11c280eb86dc --- /dev/null +++ b/drivers/interconnect/qcom/smd-rpm.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, Linaro Ltd. + * Author: Georgi Djakov + */ + +#ifndef __DRIVERS_INTERCONNECT_QCOM_SMD_RPM_H +#define __DRIVERS_INTERCONNECT_QCOM_SMD_RPM_H + +#include + +bool qcom_icc_rpm_smd_available(void); +int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u32 val); + +#endif From patchwork Fri Aug 31 14:01:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 964461 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="Rp2Uxdf7"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 4221JM2R4xz9s4Z for ; Sat, 1 Sep 2018 00:02:11 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728774AbeHaSJq (ORCPT ); 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Fri, 31 Aug 2018 07:02:05 -0700 (PDT) Received: from localhost.localdomain ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id m68-v6sm8624513wmb.10.2018.08.31.07.02.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 31 Aug 2018 07:02:05 -0700 (PDT) From: Georgi Djakov To: linux-pm@vger.kernel.org, gregkh@linuxfoundation.org Cc: rjw@rjwysocki.net, robh+dt@kernel.org, mturquette@baylibre.com, khilman@baylibre.com, vincent.guittot@linaro.org, skannan@codeaurora.org, bjorn.andersson@linaro.org, amit.kucheria@linaro.org, seansw@qti.qualcomm.com, daidavid1@codeaurora.org, evgreen@chromium.org, mark.rutland@arm.com, lorenzo.pieralisi@arm.com, abailon@baylibre.com, maxime.ripard@bootlin.com, arnd@arndb.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH v9 6/8] dt-bindings: interconnect: Document qcom, msm8916 NoC bindings Date: Fri, 31 Aug 2018 17:01:49 +0300 Message-Id: <20180831140151.13972-7-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180831140151.13972-1-georgi.djakov@linaro.org> References: <20180831140151.13972-1-georgi.djakov@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document the device-tree bindings of the Network-On-Chip interconnect hardware found on Qualcomm msm8916 platforms. Signed-off-by: Georgi Djakov --- .../bindings/interconnect/qcom-msm8916.txt | 41 ++++++++ include/dt-bindings/interconnect/qcom.h | 98 +++++++++++++++++++ 2 files changed, 139 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom-msm8916.txt create mode 100644 include/dt-bindings/interconnect/qcom.h diff --git a/Documentation/devicetree/bindings/interconnect/qcom-msm8916.txt b/Documentation/devicetree/bindings/interconnect/qcom-msm8916.txt new file mode 100644 index 000000000000..744df51df4ed --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom-msm8916.txt @@ -0,0 +1,41 @@ +Qualcomm MSM8916 Network-On-Chip interconnect driver binding +---------------------------------------------------- + +Required properties : +- compatible : shall contain only one of the following: + "qcom,msm8916-bimc" + "qcom,msm8916-pnoc" + "qcom,msm8916-snoc" +- #interconnect-cells : should contain 1 +- reg : shall contain base register location and length + +Optional properties : +clocks : list of phandles and specifiers to all interconnect bus clocks +clock-names : clock names should include both "bus_clk" and "bus_a_clk" + +Examples: + + snoc: snoc@580000 { + compatible = "qcom,msm8916-snoc"; + #interconnect-cells = <1>; + reg = <0x580000 0x14000>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, + <&rpmcc RPM_SMD_SNOC_A_CLK>; + }; + bimc: bimc@400000 { + compatible = "qcom,msm8916-bimc"; + #interconnect-cells = <1>; + reg = <0x400000 0x62000>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc RPM_SMD_BIMC_CLK>, + <&rpmcc RPM_SMD_BIMC_A_CLK>; + }; + pnoc: pnoc@500000 { + compatible = "qcom,msm8916-pnoc"; + #interconnect-cells = <1>; + reg = <0x500000 0x11000>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, + <&rpmcc RPM_SMD_PCNOC_A_CLK>; + }; diff --git a/include/dt-bindings/interconnect/qcom.h b/include/dt-bindings/interconnect/qcom.h new file mode 100644 index 000000000000..48f944b30e5d --- /dev/null +++ b/include/dt-bindings/interconnect/qcom.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Qualcomm interconnect IDs + * + * Copyright (c) 2018, Linaro Ltd. + * Author: Georgi Djakov + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_H + +#define BIMC_SNOC_MAS 1 +#define BIMC_SNOC_SLV 2 +#define MASTER_AMPSS_M0 3 +#define MASTER_BLSP_1 4 +#define MASTER_CRYPTO_CORE0 5 +#define MASTER_DEHR 6 +#define MASTER_GRAPHICS_3D 7 +#define MASTER_JPEG 8 +#define MASTER_LPASS 9 +#define MASTER_MDP_PORT0 10 +#define MASTER_QDSS_BAM 11 +#define MASTER_QDSS_ETR 12 +#define MASTER_SDCC_1 13 +#define MASTER_SDCC_2 14 +#define MASTER_SNOC_CFG 15 +#define MASTER_SPDM 16 +#define MASTER_TCU_0 17 +#define MASTER_TCU_1 18 +#define MASTER_USB_HS 19 +#define MASTER_VFE 20 +#define MASTER_VIDEO_P0 21 +#define PNOC_INT_0 22 +#define PNOC_INT_1 23 +#define PNOC_M_0 24 +#define PNOC_M_1 25 +#define PNOC_SLV_0 26 +#define PNOC_SLV_1 27 +#define PNOC_SLV_2 28 +#define PNOC_SLV_3 29 +#define PNOC_SLV_4 30 +#define PNOC_SLV_8 31 +#define PNOC_SLV_9 32 +#define PNOC_SNOC_MAS 33 +#define PNOC_SNOC_SLV 34 +#define SLAVE_AMPSS_L2 35 +#define SLAVE_BIMC_CFG 36 +#define SLAVE_BLSP_1 37 +#define SLAVE_BOOT_ROM 38 +#define SLAVE_CAMERA_CFG 39 +#define SLAVE_CATS_128 40 +#define SLAVE_CLK_CTL 41 +#define SLAVE_CRYPTO_0_CFG 42 +#define SLAVE_DEHR_CFG 43 +#define SLAVE_DISPLAY_CFG 44 +#define SLAVE_EBI_CH0 45 +#define SLAVE_GRAPHICS_3D_CFG 46 +#define SLAVE_IMEM_CFG 47 +#define SLAVE_LPASS 48 +#define SLAVE_MPM 49 +#define SLAVE_MSM_PDM 50 +#define SLAVE_MSM_TCSR 51 +#define SLAVE_MSS 52 +#define SLAVE_OCMEM_64 53 +#define SLAVE_PMIC_ARB 54 +#define SLAVE_PNOC_CFG 55 +#define SLAVE_PRNG 56 +#define SLAVE_QDSS_CFG 57 +#define SLAVE_QDSS_STM 58 +#define SLAVE_RBCPR_CFG 59 +#define SLAVE_RPM_MSG_RAM 60 +#define SLAVE_SDCC_1 61 +#define SLAVE_SDCC_4 62 +#define SLAVE_SECURITY 63 +#define SLAVE_SERVICE_SNOC 64 +#define SLAVE_SNOC_CFG 65 +#define SLAVE_SPDM 66 +#define SLAVE_SYSTEM_IMEM 67 +#define SLAVE_TLMM 68 +#define SLAVE_USB_HS 69 +#define SLAVE_VENUS_CFG 70 +#define SNOC_BIMC_0_MAS 71 +#define SNOC_BIMC_0_SLV 72 +#define SNOC_BIMC_1_MAS 73 +#define SNOC_BIMC_1_SLV 74 +#define SNOC_INT_0 75 +#define SNOC_INT_1 76 +#define SNOC_INT_BIMC 77 +#define SNOC_MM_INT_0 78 +#define SNOC_MM_INT_1 79 +#define SNOC_MM_INT_2 80 +#define SNOC_MM_INT_BIMC 81 +#define SNOC_PNOC_MAS 82 +#define SNOC_PNOC_SLV 83 +#define SNOC_QDSS_INT 84 +#define SYSTEM_SLAVE_FAB_APPS 85 + +#endif