From patchwork Thu Aug 30 05:14:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Thiago Macieira X-Patchwork-Id: 963755 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-484767-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="VAahZibm"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4219dn5XM5z9s2P for ; Thu, 30 Aug 2018 15:14:19 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type :content-transfer-encoding; q=dns; s=default; b=qWO2qHguRP/gxhSd zM13FGC+rWdh4ubNVafEyzbcLw2geDcuwZFYJ5I6Vggem9K9sIoSyV1gHAY2VLkn jVIS7qukN46//I8j7wyn3MtDvpESJvgd/aFSYxx4L7iAYur58DJWxsyFGXPubqPS JpFh5QXhrVyn3wvbJeRhAkF/9ek= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type :content-transfer-encoding; s=default; bh=ojaMAM/XwYbFUda0YHJ713 o5tbE=; b=VAahZibmySyKvbHPqlgVQz0xJLtgeiLJWsQ/c7/XcyRV89c/AZKRvh xfXkAMUvQEC3JqpJphWzxcEpNqGOFjeDrq31lJEjksbeu6ry+C7ijvx5Gj+PqXTx 6lljQC/cNsLMj1niUTXjSBWGJmjVSoxpH/lts5JC4DIbO8eeBFuR0= Received: (qmail 33109 invoked by alias); 30 Aug 2018 05:14:10 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 33092 invoked by uid 89); 30 Aug 2018 05:14:10 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_PASS autolearn=ham version=3.3.2 spammy=Lake, lake, UD:intel.com, UD:en.wikipedia.org X-HELO: mga14.intel.com Received: from mga14.intel.com (HELO mga14.intel.com) (192.55.52.115) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 30 Aug 2018 05:14:08 +0000 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Aug 2018 22:14:07 -0700 Received: from psander1-mobl.amr.corp.intel.com (HELO tjmaciei-mobl1-clear.ger.corp.intel.com) ([10.254.75.85]) by fmsmga005.fm.intel.com with ESMTP; 29 Aug 2018 22:14:06 -0700 From: Thiago Macieira To: gcc-patches@gcc.gnu.org, Uros Bizjak Cc: "H . J . Lu" Subject: [PATCH 1/1] Move AESNI generation to Skylake and Goldmont Date: Wed, 29 Aug 2018 22:14:06 -0700 Message-Id: <20180830051406.118182-1-thiago.macieira@intel.com> MIME-Version: 1.0 The instruction set first appeared with Westmere, but not all processors in that and the next few generations have the instructions. According to Wikipedia[1], the first generation in which all SKUs have AES instructions are Skylake and Goldmont. I can't find any Skylake, Kabylake, Kabylake-R or Cannon Lake currently listed at https://ark.intel.com that says "Intel® AES New Instructions" "No". [1] https://en.wikipedia.org/wiki/AES_instruction_set --- gcc/ 2018-08-27 Thiago Macieira config/i386/i386.c: Update PTA_WESTMERE, PTA_SKYLAKE and PTA_GOLDMONT --- gcc/config/i386/i386.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index c437c18a29c..8672a666024 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -3479,7 +3479,7 @@ ix86_option_override_internal (bool main_args_p, | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR; const wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_POPCNT; - const wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_AES | PTA_PCLMUL; + const wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_PCLMUL; const wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT; const wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE @@ -3488,7 +3488,7 @@ ix86_option_override_internal (bool main_args_p, | PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE; const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED; - const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_CLFLUSHOPT + const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_AES | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES | PTA_SGX; const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU @@ -3505,7 +3505,7 @@ ix86_option_override_internal (bool main_args_p, | PTA_AVX512F | PTA_AVX512CD; const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE; const wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | PTA_RDRND; - const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_SHA | PTA_XSAVE + const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_AES | PTA_SHA | PTA_XSAVE | PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT | PTA_XSAVEOPT | PTA_FSGSBASE; const wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID