From patchwork Thu Aug 2 11:49:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoph Hellwig X-Patchwork-Id: 952699 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=lst.de Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=infradead.org header.i=@infradead.org header.b="sSAX9YR/"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41h7mr2YwRz9s2g for ; Thu, 2 Aug 2018 21:51:24 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732273AbeHBNlJ (ORCPT ); Thu, 2 Aug 2018 09:41:09 -0400 Received: from bombadil.infradead.org ([198.137.202.133]:38838 "EHLO bombadil.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732269AbeHBNlJ (ORCPT ); Thu, 2 Aug 2018 09:41:09 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20170209; h=References:In-Reply-To:Message-Id: Date:Subject:Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=KmtehZBvQ8FHrHdjfV2nyNHi6QaRR6lTpkmbGqVhkOw=; b=sSAX9YR/EaTonCaRf7vNEgwmw KP69vG4OfEv0NRDcdkTfwzgPcEB0NQwSJxnTvMJE/KtPNYg1nqYGjAeOwi6lO7mPKxkgaZn+aeqqo ThHzOSSk0aYb0eR/1i1QcW+Gp4ZXefa+6Ojwy0uGokpuZ//14EJH10848bx221n0ueKhHHou2WX3A YsV6hOQqAl8YvRFMRwlDia+yvNFKXGFId0tU/wnGUDk3WT7jmhRA2zGGqJS1ecGkQLRmdkLZflf5g 499lkTI0JyHCYRMgi9hiHm6Vw4/qnO/tERq/FxMjBtJSFoIDYFMq8RRJh/1exfwo4w//apFJ+4eRW HHxAnsqdA==; Received: from clnet-p19-102.ikbnet.co.at ([83.175.77.102] helo=localhost) by bombadil.infradead.org with esmtpsa (Exim 4.90_1 #2 (Red Hat Linux)) id 1flC7U-00058m-BW; Thu, 02 Aug 2018 11:50:17 +0000 From: Christoph Hellwig To: tglx@linutronix.de, palmer@sifive.com, jason@lakedaemon.net, marc.zyngier@arm.com, robh+dt@kernel.org, mark.rutland@arm.com Cc: anup@brainfault.org, atish.patra@wdc.com, devicetree@vger.kernel.org, aou@eecs.berkeley.edu, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, shorne@gmail.com Subject: [PATCH 01/11] dt-bindings: Correct RISC-V's timebase-frequency Date: Thu, 2 Aug 2018 13:49:58 +0200 Message-Id: <20180802115008.4031-2-hch@lst.de> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180802115008.4031-1-hch@lst.de> References: <20180802115008.4031-1-hch@lst.de> X-SRS-Rewrite: SMTP reverse-path rewritten from by bombadil.infradead.org. See http://www.infradead.org/rpr.html Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Palmer Dabbelt Someone must have read the device tree specification incorrectly, because we were putting timebase-frequency in the wrong place. This corrects the issue, moving it from / { cpus { timebase-frequency = X; } } to / { cpus { cpu@0 { timebase-frequency = X; } } } This is great, because the timer's frequency should really be a per-cpu quantity on RISC-V systems since there's a timer per CPU. This should lead to some cleanups in our timer driver. Signed-off-by: Palmer Dabbelt Signed-off-by: Christoph Hellwig Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/riscv/cpus.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.txt b/Documentation/devicetree/bindings/riscv/cpus.txt index adf7b7af5dc3..b0b038d6c406 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.txt +++ b/Documentation/devicetree/bindings/riscv/cpus.txt @@ -93,9 +93,9 @@ Linux is allowed to run on. cpus { #address-cells = <1>; #size-cells = <0>; - timebase-frequency = <1000000>; cpu@0 { clock-frequency = <1600000000>; + timebase-frequency = <1000000>; compatible = "sifive,rocket0", "riscv"; device_type = "cpu"; i-cache-block-size = <64>; @@ -113,6 +113,7 @@ Linux is allowed to run on. }; cpu@1 { clock-frequency = <1600000000>; + timebase-frequency = <1000000>; compatible = "sifive,rocket0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; @@ -145,6 +146,7 @@ Example: Spike ISA Simulator with 1 Hart This device tree matches the Spike ISA golden model as run with `spike -p1`. cpus { + timebase-frequency = <1000000>; cpu@0 { device_type = "cpu"; reg = <0x00000000>; From patchwork Thu Aug 2 11:49:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoph Hellwig X-Patchwork-Id: 952697 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=lst.de Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=infradead.org header.i=@infradead.org header.b="MNYZW5Ri"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41h7ln3qZ5z9s5K for ; Thu, 2 Aug 2018 21:50:29 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732334AbeHBNlN (ORCPT ); Thu, 2 Aug 2018 09:41:13 -0400 Received: from bombadil.infradead.org ([198.137.202.133]:38956 "EHLO bombadil.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732266AbeHBNlM (ORCPT ); Thu, 2 Aug 2018 09:41:12 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20170209; h=References:In-Reply-To:Message-Id: Date:Subject:Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=/lbxZxozS8tvIqsOyT7OgjcPkjwajRLKeNgqmPo8/tE=; b=MNYZW5RiAhd2VCQiPBd+IsJwu 3IBVbXbDzrygmT6v7NAfGm3q4B/cpca+nee3ywRVqyhb7FhYbqys+xVDalJlNo+z7ot7OmMH94r87 y2R0mRxFKnIgHA1kR6RirMT+yMpinYWjioMhwkDMbsf76m/0RC/kSPaobHr+P9OGfW4NQztJo3GAs 5ArbxQAS5wSTB6QN+89RnkXUgfpEgY6x2nYhywWxMPyJmxmj319drnEovNFH5Q0qsw3m99MRCuMtp Ikk/WhfBk4S0FKFstA2Dl9aeeddh/soTaq0ZfyncPvMIKoFOMmrdUEPuAEUOS15mgVV/zSU2YsYOb 16FwiVJ1w==; Received: from clnet-p19-102.ikbnet.co.at ([83.175.77.102] helo=localhost) by bombadil.infradead.org with esmtpsa (Exim 4.90_1 #2 (Red Hat Linux)) id 1flC7Y-0005AI-5C; Thu, 02 Aug 2018 11:50:20 +0000 From: Christoph Hellwig To: tglx@linutronix.de, palmer@sifive.com, jason@lakedaemon.net, marc.zyngier@arm.com, robh+dt@kernel.org, mark.rutland@arm.com Cc: anup@brainfault.org, atish.patra@wdc.com, devicetree@vger.kernel.org, aou@eecs.berkeley.edu, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, shorne@gmail.com Subject: [PATCH 02/11] dt-bindings: Add an enable method to RISC-V Date: Thu, 2 Aug 2018 13:49:59 +0200 Message-Id: <20180802115008.4031-3-hch@lst.de> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180802115008.4031-1-hch@lst.de> References: <20180802115008.4031-1-hch@lst.de> X-SRS-Rewrite: SMTP reverse-path rewritten from by bombadil.infradead.org. See http://www.infradead.org/rpr.html Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Palmer Dabbelt RISC-V doesn't currently specify a mechanism for enabling or disabling CPUs. Instead, we assume that all CPUs are enabled on boot, and if someone wants to save power we instead put a CPU to sleep via a WFI loop. Future systems may have an explicit mechanism for putting a CPU to sleep, so we're standardizing the device tree entry for when that happens. We're not defining a spin-table based interface to the firmware, as the plan is to handle this entirely within the kernel instead. Signed-off-by: Palmer Dabbelt Signed-off-by: Christoph Hellwig --- Documentation/devicetree/bindings/riscv/cpus.txt | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.txt b/Documentation/devicetree/bindings/riscv/cpus.txt index b0b038d6c406..6aa9cd075a5b 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.txt +++ b/Documentation/devicetree/bindings/riscv/cpus.txt @@ -82,6 +82,15 @@ described below. Value type: Definition: Contains the RISC-V ISA string of this hart. These ISA strings are defined by the RISC-V ISA manual. + - cpu-enable-method: + Usage: optional + Value type: + Definition: When absent, default is either "always-disabled" + "always-enabled", depending on the current state + of the CPU. + Must be one of: + * "always-disabled": This CPU cannot be enabled. + * "always-enabled": This CPU cannot be disabled. Example: SiFive Freedom U540G Development Kit --------------------------------------------- From patchwork Thu Aug 2 11:50:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoph Hellwig X-Patchwork-Id: 952698 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=lst.de Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=infradead.org header.i=@infradead.org header.b="MS5XlIQ9"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41h7mn20Mtz9s2g for ; Thu, 2 Aug 2018 21:51:21 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732350AbeHBNlR (ORCPT ); Thu, 2 Aug 2018 09:41:17 -0400 Received: from bombadil.infradead.org ([198.137.202.133]:39104 "EHLO bombadil.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732266AbeHBNlR (ORCPT ); Thu, 2 Aug 2018 09:41:17 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20170209; h=References:In-Reply-To:Message-Id: Date:Subject:Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=3mCWctoBLSjxLeHfKuERcNVPj4TN94MtvY6Rz81P+J4=; b=MS5XlIQ9GS42IAfJdFNWTqAyT U6QKQIvQFNLg9zj05ZMj4aJz2JBiaIjgRCuYfPWDdESMT1NR4cTLrwy/TslSCYUYD4NAhAHi0NJZ+ t6MFBbEXd9UYkOhXCnJQT2xYB4S2qzTTs4WStvv30qJyLuG5OQltHFwCiiJ19cmThkJ7dLEsnHUqG FbnEb0kmKbSXQcsUNiuSBeNENv8Kqqw+Vj32u/HAdGskTvWDaH2YB/j/elF29Xy3RTpMPMk+QA3qG 0sJPPhlOxkRQ4/T3qKTsrHDOmOGHNk+sU5HvVrpr1/WQ+xvuAXMHlo9jgIkaclEkj0/X9dj0CMHyn XxhsM3cng==; Received: from clnet-p19-102.ikbnet.co.at ([83.175.77.102] helo=localhost) by bombadil.infradead.org with esmtpsa (Exim 4.90_1 #2 (Red Hat Linux)) id 1flC7b-0005Bs-DE; Thu, 02 Aug 2018 11:50:24 +0000 From: Christoph Hellwig To: tglx@linutronix.de, palmer@sifive.com, jason@lakedaemon.net, marc.zyngier@arm.com, robh+dt@kernel.org, mark.rutland@arm.com Cc: anup@brainfault.org, atish.patra@wdc.com, devicetree@vger.kernel.org, aou@eecs.berkeley.edu, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, shorne@gmail.com, Palmer Dabbelt Subject: [PATCH 03/11] dt-bindings: interrupt-controller: RISC-V PLIC documentation Date: Thu, 2 Aug 2018 13:50:00 +0200 Message-Id: <20180802115008.4031-4-hch@lst.de> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180802115008.4031-1-hch@lst.de> References: <20180802115008.4031-1-hch@lst.de> X-SRS-Rewrite: SMTP reverse-path rewritten from by bombadil.infradead.org. See http://www.infradead.org/rpr.html Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Palmer Dabbelt This patch adds documentation for the platform-level interrupt controller (PLIC) found in all RISC-V systems. This interrupt controller routes interrupts from all the devices in the system to each hart-local interrupt controller. Note: the DTS bindings for the PLIC aren't set in stone yet, as we might want to change how we're specifying holes in the hart list. Signed-off-by: Palmer Dabbelt [hch: various fixes and updates] Signed-off-by: Christoph Hellwig --- .../interrupt-controller/sifive,plic0.txt | 57 +++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sifive,plic0.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic0.txt b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic0.txt new file mode 100644 index 000000000000..c756cd208a93 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic0.txt @@ -0,0 +1,57 @@ +SiFive Platform-Level Interrupt Controller (PLIC) +------------------------------------------------- + +SiFive SOCs include an implementation of the Platform-Level Interrupt Controller +(PLIC) high-level specification in the RISC-V Privileged Architecture +specification. The PLIC connects all external interrupts in the system to all +hart contexts in the system, via the external interrupt source in each hart. + +A hart context is a privilege mode in a hardware execution thread. For example, +in an 4 core system with 2-way SMT, you have 8 harts and probably at least two +privilege modes per hart; machine mode and supervisor mode. + +Each interrupt can be enabled on per-context basis. Any context can claim +a pending enabled interrupt and then release it once it has been handled. + +Each interrupt has a configurable priority. Higher priority interrupts are +serviced first. Each context can specify a priority threshold. Interrupts +with priority below this threshold will not cause the PLIC to raise its +interrupt line leading to the context. + +While the PLIC supports both edge-triggered and level-triggered interrupts, +interrupt handlers are oblivious to this distinction and therefore it is not +specified in the PLIC device-tree binding. + +While the RISC-V ISA doesn't specify a memory layout for the PLIC, the +"sifive,plic0" device is a concrete implementation of the PLIC that contains a +specific memory layout, which is documented in chapter 8 of the SiFive U5 +Coreplex Series Manual . + +Required properties: +- compatible : "sifive,plic0" +- #address-cells : should be <0> +- #interrupt-cells : should be <1> +- interrupt-controller : Identifies the node as an interrupt controller +- reg : Should contain 1 register range (address and length) +- interrupts-extended : Specifies which contexts are connected to the PLIC, + with "-1" specifying that a context is not present. The nodes pointed + to should be "riscv" HART nodes, or eventually be parented by such nodes. +- riscv,ndev: Specifies how many external interrupts are supported by + this controller. + +Example: + + plic: interrupt-controller@c000000 { + #address-cells = <0>; + #interrupt-cells = <1>; + compatible = "riscv,plic0"; + interrupt-controller; + interrupts-extended = < + &cpu0-intc 11 + &cpu1-intc 11 &cpu1-intc 9 + &cpu2-intc 11 &cpu2-intc 9 + &cpu3-intc 11 &cpu3-intc 9 + &cpu4-intc 11 &cpu4-intc 9>; + reg = <0xc000000 0x4000000>; + riscv,ndev = <10>; + };