From patchwork Wed Aug 1 08:19:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Boris Brezillon X-Patchwork-Id: 951984 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bootlin.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41gR7K4xB6z9s0R for ; Wed, 1 Aug 2018 18:19:57 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388320AbeHAKE1 (ORCPT ); Wed, 1 Aug 2018 06:04:27 -0400 Received: from mail.bootlin.com ([62.4.15.54]:33878 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388304AbeHAKE1 (ORCPT ); Wed, 1 Aug 2018 06:04:27 -0400 Received: by mail.bootlin.com (Postfix, from userid 110) id AF02F20799; Wed, 1 Aug 2018 10:19:53 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.bootlin.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost.localdomain (AAubervilliers-681-1-89-120.w90-88.abo.wanadoo.fr [90.88.30.120]) by mail.bootlin.com (Postfix) with ESMTPSA id 57BA62074F; Wed, 1 Aug 2018 10:19:53 +0200 (CEST) From: Boris Brezillon To: Mike Turquette , Stephen Boyd , linux-clk@vger.kernel.org Cc: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , devicetree@vger.kernel.org, Julien Su , Mason Yang , , linux-arm-kernel@lists.infradead.org, Michal Simek , Boris Brezillon Subject: [PATCH 2/2] dt-bindings: clock: Add bindings for the Clocking Wizard IP Date: Wed, 1 Aug 2018 10:19:50 +0200 Message-Id: <20180801081950.10497-2-boris.brezillon@bootlin.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180801081950.10497-1-boris.brezillon@bootlin.com> References: <20180801081950.10497-1-boris.brezillon@bootlin.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document Xilinx Clocking Wizard bindings. Signed-off-by: Boris Brezillon Reviewed-by: Rob Herring --- .../devicetree/bindings/clock/xlnx,clk-wizard.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/xlnx,clk-wizard.txt diff --git a/Documentation/devicetree/bindings/clock/xlnx,clk-wizard.txt b/Documentation/devicetree/bindings/clock/xlnx,clk-wizard.txt new file mode 100644 index 000000000000..1bf7a764f4a9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/xlnx,clk-wizard.txt @@ -0,0 +1,28 @@ +Device Tree Clock bindings for the "Clocking Wizard" IP provided by Xilinx + +This block can be used to generate up to 4 clock signals out of a single input +clock. It embeds a PLL to generate an intermediate clock which then feeds 4 +clock dividers whose divider value can be adjusted based on the user needs. + +Required properties: + - #clock-cells: must be 1. The cell is encoding the id of the output clk + (from 0 to xlnx,clk-wizard-num-outputs - 1) + - compatible: must be "xlnx,clk-wizard-5.1" + - clocks: 2 clocks are required + - clock-names: should contain 2 clock names: "aclk" and "clkin". + "aclk" is driving the register interface and "clk_in" is the + input clock signal that is used by the PLL block + - xlnx,clk-wizard-num-outputs: this describe the number of output clocks + (chosen at synthesization time) + - reg: registers used to configure the Clocking wizard block + +Example: + + clkwizard: clkwizard@43c20000 { + compatible = "xlnx,clk-wizard-5.1"; + reg = <0x43c20000 0x10000>; + clocks = <&clkc 18>, <&clkc 18>; + clock-names = "aclk", "clk_in1"; + #clock-cells = <1>; + xlnx,clk-wizard-num-outputs = <2>; + };