From patchwork Thu Jul 19 01:13:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 946004 X-Patchwork-Delegate: yamada.m@jp.panasonic.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=socionext.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=nifty.com header.i=@nifty.com header.b="WWMACT9L"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41WGJH10ZFz9s3x for ; Thu, 19 Jul 2018 11:14:21 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id DB367C21E45; Thu, 19 Jul 2018 01:14:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 7AF12C21C27; Thu, 19 Jul 2018 01:14:12 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 4B43BC21C27; Thu, 19 Jul 2018 01:14:11 +0000 (UTC) Received: from conuserg-09.nifty.com (conuserg-09.nifty.com [210.131.2.76]) by lists.denx.de (Postfix) with ESMTPS id 3A45CC21BE5 for ; Thu, 19 Jul 2018 01:14:09 +0000 (UTC) Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-09.nifty.com with ESMTP id w6J1Dbvx001386; Thu, 19 Jul 2018 10:13:37 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com w6J1Dbvx001386 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1531962818; bh=6YrWf+FHL1K7vvIkmKZfkw79okwzIJg65DFyYdKtxsI=; h=From:To:Cc:Subject:Date:From; b=WWMACT9Lh7CSV9g9iRBk4eGgoLjIGpTrs9SlqC1Qglz+eGE1dS2w7B5yU89MeFWGb /ifEiYcOqbuX/nfpqwPJ2Xi/H6iEeMetSXEpG8ATqk46ktyeusONyHiCZwrZfZlZlz KTm9e18F44oDyIaQjVQzuf8XBC4vaXKaka27mYGziyGUrzPYhPTO0sJBJNhKdQJJ9W YVPA0h7aJX9RcQpCbwcEt34V9vG/tXepV32UZb4yq/RMMyRv7GDDfJjGDQfFgWs4Aw /Na4IQcF+2hTdOD7EUE5Z4uQDgrfN5bd39u3ooDMgCyLUbk6b41yG2DA7Ox05NYujs SULWGV2/lFu2g== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Thu, 19 Jul 2018 10:13:23 +0900 Message-Id: <1531962803-25477-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 Cc: Marek Vasut , Scott Wood Subject: [U-Boot] [PATCH] mtd: nand: denali: correct buffer alignment for DMA transfer X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The NAND framework makes sure to pass in the buffer with at least chip->buf_align alignment. Currently, the Denali NAND driver only requests 16 byte alignment. This causes unaligned cache operations for the DMA transfer. [Error Example] => nand read 81000010 0 1000 NAND read: device 0 offset 0x0, size 0x1000 CACHE: Misaligned operation at range [81000010, 81001010] CACHE: Misaligned operation at range [81000010, 81001010] CACHE: Misaligned operation at range [81000010, 81001010] CACHE: Misaligned operation at range [81000010, 81001010] 4096 bytes read: OK Reported-by: Marek Vasut Signed-off-by: Masahiro Yamada --- drivers/mtd/nand/denali.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 6266c8a..7302c37 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -1270,7 +1270,7 @@ int denali_init(struct denali_nand_info *denali) denali->dma_avail = 1; if (denali->dma_avail) { - chip->buf_align = 16; + chip->buf_align = ARCH_DMA_MINALIGN; if (denali->caps & DENALI_CAP_DMA_64BIT) denali->setup_dma = denali_setup_dma64; else