From patchwork Tue Jul 17 07:02:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felix Brack X-Patchwork-Id: 944756 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=ltec.ch Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41VB7n6Kphz9rxs for ; Tue, 17 Jul 2018 17:03:16 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 1DF40C21E1A; Tue, 17 Jul 2018 07:03:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 0A9A3C21C4A; Tue, 17 Jul 2018 07:03:07 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B9D78C21C4A; Tue, 17 Jul 2018 07:03:05 +0000 (UTC) Received: from mail.ltec.ch (mail.ltec.ch [95.143.48.181]) by lists.denx.de (Postfix) with ESMTPS id 747B2C21C3F for ; Tue, 17 Jul 2018 07:03:05 +0000 (UTC) Received: from nebula.ltec ([172.27.11.2] helo=vm64.ltec) by mail.ltec.ch with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_CBC_SHA256:128) (Exim 4.89) (envelope-from ) id 1ffK0V-0007vI-Gc; Tue, 17 Jul 2018 09:02:47 +0200 From: Felix Brack To: u-boot@lists.denx.de Date: Tue, 17 Jul 2018 09:02:23 +0200 Message-Id: <1531810943-3417-1-git-send-email-fb@ltec.ch> X-Mailer: git-send-email 2.7.4 Cc: Tom Rini , Stefan Roese , Alexey Brodkin , Michal Simek , Alexander Graf Subject: [U-Boot] [PATCH v2] serial: ns16550: Add register shift variable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch adds a new Kconfig variable that allows setting the register offset shift value for the ns16550 driver to some other value then 0 if not defined by the DT. All credit for this patch goes to Lokesh Vutla as it was his idea. The motivation for writing this patch originates in the effort of synchronizing U-Boot DT to Linux DT for am33xx SOCs. The current am33xx.dtsi file from U-Boot defines the property for all UART nodes. The actual (4.18+) am33xx.dtsi file from Linux does not define anymore. To prevent (probably difficult) changes in many .dts and .dtsi files once the synchronization is done, one can use this new variable. For the pdu001 board, for example, SYS_NS16550_REG_SHIFT is set to 2; no need to clutter U-Boot and board specific dts files with properties. Signed-off-by: Felix Brack --- Changes in v2: - clarify variable usage - set default value to 2 for AM33XX SoC drivers/serial/Kconfig | 15 +++++++++++++++ drivers/serial/ns16550.c | 3 ++- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 766e5ce..7eb3c6f 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -530,6 +530,21 @@ config SYS_NS16550 be used. It can be a constant or a function to get clock, eg, get_serial_clock(). +config SYS_NS16550_REG_SHIFT + int "Amount of bits to shift register offsets left" + default 2 if AM33XX + default 0 + depends on SYS_NS16550 + help + Use this to specify the amount of bits to shift device register + offsets to the left. The resulting register offset is calculate as + follows: "reg offset" << SYS_NS16550_REG_SHIFT. If, for example, + the device register offsets are 0x00, 0x04, 0x08, 0x0C and so forth + than set this to 2. + In case of AM33XX SoC the default value is 2, 0 otherwise. Note + that a property defined in a UART node of the device + tree will always take precedence. + config INTEL_MID_SERIAL bool "Intel MID platform UART support" depends on DM_SERIAL && OF_CONTROL diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 9c80090..9ff6dbe 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -442,7 +442,8 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev) #endif plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0); - plat->reg_shift = dev_read_u32_default(dev, "reg-shift", 0); + plat->reg_shift = dev_read_u32_default(dev, "reg-shift", + CONFIG_SYS_NS16550_REG_SHIFT); err = clk_get_by_index(dev, 0, &clk); if (!err) {