From patchwork Thu Jul 5 15:13:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Programmingkid X-Patchwork-Id: 939983 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="kYGABctp"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41M1bv29KGz9s2g for ; Fri, 6 Jul 2018 01:14:17 +1000 (AEST) Received: from localhost ([::1]:53246 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fb5xW-0005pO-Gq for incoming@patchwork.ozlabs.org; Thu, 05 Jul 2018 11:14:14 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42542) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fb5xC-0005pF-6U for qemu-devel@nongnu.org; Thu, 05 Jul 2018 11:13:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fb5x7-0003oC-UN for qemu-devel@nongnu.org; Thu, 05 Jul 2018 11:13:54 -0400 Received: from mail-io0-x241.google.com ([2607:f8b0:4001:c06::241]:41754) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fb5x7-0003nv-Jz; Thu, 05 Jul 2018 11:13:49 -0400 Received: by mail-io0-x241.google.com with SMTP id q9-v6so8058337ioj.8; Thu, 05 Jul 2018 08:13:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=VHmbKIVOq3ijp89qeb40lo9B/xDWnNzkPLpLrfpr37I=; b=kYGABctpdbNRnh2uTO+S2xRA/QuGg1caWB8FA1UY96cFlRs2PuqHgB9n0v6Y0zIuxr I5emBlRrFePP3iS+E1fYHEnWWBzGWkDcpr3o3OTdS/D8uOHh3MMHR0wsx6cZLACPvkxa bhtr85YN5qlOeCqrs+ANtW5eE6oXZ4ISIUEGXiZQSDZylcOioJNuv48LJFIZSOXB293X p9lNKUUTatmLoVZBzf47gZ71NfGFmyyxs86ddnX5KDJcyTovjt0vD2GXs7izsT3ZpIlI hRCpRL2RlHpqqeHKzJPFRdHNckamgT2rcCXqbFWWmcggobZlKLEG3Jg4adNGSRqzlRB/ X5cA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=VHmbKIVOq3ijp89qeb40lo9B/xDWnNzkPLpLrfpr37I=; b=rzbMOSVu38gbI6EYaukqcBCFfOH4sbPALmdeOGPbKAjaet44pFuizVYb58iZFKv/bY 4XiLlqgT7/1OewO9qX62saWYPVI9K17irO3igOcfbH1lUGoeqPwf6HIdy/8J3gOmnoO/ wrKh7cE/uEOYHUr0gwjM3MdzVJ67anM/W35JUM84r3k9beF5hxrXXiJaCKJe5C4b8QIr us1AOw8K8+rnSwxtYUQ2tzFiWsUU3SohPafe4qcGvdgHe3GGFQTxWvKO0uS/jNfc8I+L zamlBrhlIgj1qZG+ISE3kCBqcqP2Nqk3eGRkjTd8IhfJObmvr/RVn0YjoKJVuE4obIYn r4Dw== X-Gm-Message-State: AOUpUlHskBt5j5u2UFkSWhBcqpdCQrUSfBrA+4qPLKR0nX+ejC+q1cZh v0+7Ne3cc8PPFuMj+PL5AJc= X-Google-Smtp-Source: AAOMgpfHPtEa8EkUAyR93aDOk3QuXC6z5den8emFchRHTCFOUjDow3nLjSygwzQJXqJLJ35k7HyQ2Q== X-Received: by 2002:a6b:8dc7:: with SMTP id p190-v6mr5496563iod.303.1530803629053; Thu, 05 Jul 2018 08:13:49 -0700 (PDT) Received: from localhost.localdomain ([69.14.184.20]) by smtp.gmail.com with ESMTPSA id 77-v6sm2832555iof.60.2018.07.05.08.13.47 (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 05 Jul 2018 08:13:48 -0700 (PDT) From: John Arbuckle To: david@gibson.dropbear.id.au, richard.henderson@linaro.org, qemu-devel@nongnu.org, qemu-ppc@nongnu.org Date: Thu, 5 Jul 2018 11:13:34 -0400 Message-Id: <20180705151334.12271-1-programmingkidx@gmail.com> X-Mailer: git-send-email 2.14.3 (Apple Git-98) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c06::241 Subject: [Qemu-devel] [RFC] fix setting FPSCR[FR] bit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: John Arbuckle Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" https://www.pdfdrive.net/powerpc-microprocessor-family-the-programming-environments-for-32-e3087633.html Page 63 in table 2-4 is where the description of this bit can be found. It is described as: Floating-point fraction rounded. The last arithmetic or rounding and conversion instruction that rounded the intermediate result incremented the fraction. This bit is NOT sticky. What I think this means is when the softfloat.c:round_canonical() function adds the inc variable to the frac variable, the floating point fraction rounded bit should be set. It also means that every time a floating point operation takes place, this bit needs to be updated since it isn't a sticky bit. My testing has produced mixed results with this patch. Some of my floating point tests are fixed by this patch, and others are broken by this patch. I'm not clear if this is the right way to implement setting the FPSCR[FR] bit. Feedback would be great. Signed-off-by: John Arbuckle --- fpu/softfloat.c | 6 +++++- include/fpu/softfloat-types.h | 1 + target/ppc/fpu_helper.c | 8 ++++++++ 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 8cd2400081..b2b2c61cff 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -382,11 +382,12 @@ static FloatParts round_canonical(FloatParts p, float_status *s, const uint64_t roundeven_mask = parm->roundeven_mask; const int exp_max = parm->exp_max; const int frac_shift = parm->frac_shift; - uint64_t frac, inc; + uint64_t frac, inc, old_frac; int exp, flags = 0; bool overflow_norm; frac = p.frac; + old_frac = frac; /* Used to determine if the fraction was rounded */ exp = p.exp; switch (p.cls) { @@ -503,6 +504,9 @@ static FloatParts round_canonical(FloatParts p, float_status *s, g_assert_not_reached(); } + if (frac != old_frac) { + flags |= float_flag_round; + } float_raise(flags, s); p.exp = exp; p.frac = frac; diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 2aae6a89b1..1d124e659c 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -147,6 +147,7 @@ enum { enum { float_flag_invalid = 1, + float_flag_round = 2, float_flag_divbyzero = 4, float_flag_overflow = 8, float_flag_underflow = 16, diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index cb82e6e842..ba57ea7cfe 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -581,6 +581,7 @@ static void do_float_check_status(CPUPPCState *env, uintptr_t raddr) CPUState *cs = CPU(ppc_env_get_cpu(env)); int status = get_float_exception_flags(&env->fp_status); bool inexact_happened = false; + bool round_happened = false; if (status & float_flag_overflow) { float_overflow_excp(env); @@ -589,6 +590,8 @@ static void do_float_check_status(CPUPPCState *env, uintptr_t raddr) } else if (status & float_flag_inexact) { float_inexact_excp(env); inexact_happened = true; + } else if (status & float_flag_round) { + round_happened = true; } /* if the inexact flag was not set */ @@ -596,6 +599,11 @@ static void do_float_check_status(CPUPPCState *env, uintptr_t raddr) env->fpscr &= ~(1 << FPSCR_FI); /* clear the FPSCR[FI] bit */ } + /* if the floating-point fraction rounded bit was not set */ + if (round_happened == false) { + env->fpscr &= ~(1 << FPSCR_FR); /* clear the FPSCR[FR] bit */ + } + if (cs->exception_index == POWERPC_EXCP_PROGRAM && (env->error_code & POWERPC_EXCP_FP)) { /* Differred floating-point exception after target FPR update */