From patchwork Thu Jul 5 11:15:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 939863 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=exceet.de Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=as-electronics.de header.i=@as-electronics.de header.b="k6A4r0Ui"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41LwMd5xryz9s3C for ; Thu, 5 Jul 2018 21:18:21 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754038AbeGELST (ORCPT ); Thu, 5 Jul 2018 07:18:19 -0400 Received: from mo4-p05-ob.smtp.rzone.de ([85.215.255.130]:18257 "EHLO mo4-p05-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753590AbeGELSP (ORCPT ); Thu, 5 Jul 2018 07:18:15 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1530789493; s=strato-dkim-0002; d=as-electronics.de; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=7pJAO9PacsLp4V4hPtw3+mrQGHAsNY4yZd9dI/Rya2g=; b=k6A4r0UiIzBmw9EqJDxcde/vrfUxf/F8D/as3ANhkBZznkc1pRd3KXIpg398VVTQE+ bQ2wmSiMTbRz69h01VupUPYZd2XQ35XvudtBFDLMGdqwIa1sGYRYy2UzqT9u+qQrXOnG x83QPG4HzWP8z1npvaDKbS6LZwczjHQIezkRqBcYsAfqOUdWOAz+22MaxItuX4vvVClP 8ZTIDdoEjD+jmRN3imKAbGLhYd2XCw7Yay6jzD9XPyblfRmNGYKoKv2xFbAUGXNF/lXE CsQcmegwJwoJhQDDrzgEEOGCANQ0DE1XkI0exXrSAfAOW6UH2rKfaYd833SsxcI7atwY fuVw== X-RZG-AUTH: ":LX8JdEmkW/4tAFwMkcNJIloh1hrA5u3owhPk7bdT5Fx22AatU+eLaHfutoZdl+X9BETxn4/4+IVqx+daE87UU5bgm7XHzClQnm8VxHglxo5wj3H1fls=" X-RZG-CLASS-ID: mo05 Received: from fs-work.fritz.box by smtp.strato.de (RZmta 43.12 AUTH) with ESMTPSA id a0925bu65BHf4iB (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA (curve secp521r1 with 521 ECDH bits, eq. 15360 bits RSA)) (Client did not present a certificate); Thu, 5 Jul 2018 13:17:41 +0200 (CEST) From: Frieder Schrempf To: linux-mtd@lists.infradead.org, boris.brezillon@bootlin.com, linux-spi@vger.kernel.org Cc: dwmw2@infradead.org, computersforpeace@gmail.com, marek.vasut@gmail.com, richard@nod.at, miquel.raynal@bootlin.com, broonie@kernel.org, david.wolfe@nxp.com, fabio.estevam@nxp.com, prabhakar.kushwaha@nxp.com, yogeshnarayan.gaur@nxp.com, han.xu@nxp.com, shawnguo@kernel.org, Frieder Schrempf , Rob Herring , Mark Rutland , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 04/12] dt-bindings: spi: Move the bindings for the FSL QSPI driver Date: Thu, 5 Jul 2018 13:15:00 +0200 Message-Id: <1530789310-16254-5-git-send-email-frieder.schrempf@exceet.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1530789310-16254-1-git-send-email-frieder.schrempf@exceet.de> References: <1530789310-16254-1-git-send-email-frieder.schrempf@exceet.de> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Move the documentation of the old SPI NOR driver to the place of the new SPI memory interface based driver. Signed-off-by: Frieder Schrempf Acked-by: Rob Herring --- Changes in v2: ============== * Split the moving and editing of the dt-bindings in two patches .../devicetree/bindings/mtd/fsl-quadspi.txt | 65 -------------------- .../devicetree/bindings/spi/spi-fsl-qspi.txt | 65 ++++++++++++++++++++ 2 files changed, 65 insertions(+), 65 deletions(-) diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt deleted file mode 100644 index 483e9cf..0000000 --- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt +++ /dev/null @@ -1,65 +0,0 @@ -* Freescale Quad Serial Peripheral Interface(QuadSPI) - -Required properties: - - compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi", - "fsl,imx7d-qspi", "fsl,imx6ul-qspi", - "fsl,ls1021a-qspi" - or - "fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi", - "fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi" - - reg : the first contains the register location and length, - the second contains the memory mapping address and length - - reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory" - - interrupts : Should contain the interrupt for the device - - clocks : The clocks needed by the QuadSPI controller - - clock-names : Should contain the name of the clocks: "qspi_en" and "qspi". - -Optional properties: - - fsl,qspi-has-second-chip: The controller has two buses, bus A and bus B. - Each bus can be connected with two NOR flashes. - Most of the time, each bus only has one NOR flash - connected, this is the default case. - But if there are two NOR flashes connected to the - bus, you should enable this property. - (Please check the board's schematic.) - - big-endian : That means the IP register is big endian - -Example: - -qspi0: quadspi@40044000 { - compatible = "fsl,vf610-qspi"; - reg = <0x40044000 0x1000>, <0x20000000 0x10000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_QSPI0_EN>, - <&clks VF610_CLK_QSPI0>; - clock-names = "qspi_en", "qspi"; - - flash0: s25fl128s@0 { - .... - }; -}; - -Example showing the usage of two SPI NOR devices: - -&qspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi2>; - status = "okay"; - - flash0: n25q256a@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q256a", "jedec,spi-nor"; - spi-max-frequency = <29000000>; - reg = <0>; - }; - - flash1: n25q256a@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q256a", "jedec,spi-nor"; - spi-max-frequency = <29000000>; - reg = <1>; - }; -}; diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt new file mode 100644 index 0000000..483e9cf --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt @@ -0,0 +1,65 @@ +* Freescale Quad Serial Peripheral Interface(QuadSPI) + +Required properties: + - compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi", + "fsl,imx7d-qspi", "fsl,imx6ul-qspi", + "fsl,ls1021a-qspi" + or + "fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi", + "fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi" + - reg : the first contains the register location and length, + the second contains the memory mapping address and length + - reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory" + - interrupts : Should contain the interrupt for the device + - clocks : The clocks needed by the QuadSPI controller + - clock-names : Should contain the name of the clocks: "qspi_en" and "qspi". + +Optional properties: + - fsl,qspi-has-second-chip: The controller has two buses, bus A and bus B. + Each bus can be connected with two NOR flashes. + Most of the time, each bus only has one NOR flash + connected, this is the default case. + But if there are two NOR flashes connected to the + bus, you should enable this property. + (Please check the board's schematic.) + - big-endian : That means the IP register is big endian + +Example: + +qspi0: quadspi@40044000 { + compatible = "fsl,vf610-qspi"; + reg = <0x40044000 0x1000>, <0x20000000 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_QSPI0_EN>, + <&clks VF610_CLK_QSPI0>; + clock-names = "qspi_en", "qspi"; + + flash0: s25fl128s@0 { + .... + }; +}; + +Example showing the usage of two SPI NOR devices: + +&qspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi2>; + status = "okay"; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + reg = <0>; + }; + + flash1: n25q256a@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + reg = <1>; + }; +}; From patchwork Thu Jul 5 11:15:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 939872 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=exceet.de Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=as-electronics.de header.i=@as-electronics.de header.b="oGNHfdtk"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41LwRV66k2z9s2R for ; Thu, 5 Jul 2018 21:21:42 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753941AbeGELSP (ORCPT ); Thu, 5 Jul 2018 07:18:15 -0400 Received: from mo4-p05-ob.smtp.rzone.de ([85.215.255.132]:27271 "EHLO mo4-p05-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753987AbeGELSN (ORCPT ); Thu, 5 Jul 2018 07:18:13 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1530789491; s=strato-dkim-0002; d=as-electronics.de; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=YDBrDiW6WYXA00RkQwERGynv8FJXXTpWWf9YV05GYmg=; b=oGNHfdtkYI2/BRmG2yNfaWdtOu9tAvMPs4LJh5Spd9Ww6VCtuI4wlYRz6TqJ59Dt5S 5XywY/fojKyEMt3MTxSpStIS1NmkLb/WLt14/oTZqu7pE1+MY7B07ygEYE2PcQBoraAJ hNdn12IQSvx32Ld9eVc9QABjFqL2ovyBxKJoVxQ91ZEK5c8K+fexyzqWGGrH2sTL0lME UfijUoESa4ylqWq1pD31l4j4/U9rODthGiFxyqsBxbm12ppacXfysPhGnHX+oG8spzbn Dub4s/LPp3tfE0D1BgEgdqzMnyeIzXhwGte/fIkHPz/CfNF/+rTXFWTMu/nHqijmVbtJ CSWw== X-RZG-AUTH: ":LX8JdEmkW/4tAFwMkcNJIloh1hrA5u3owhPk7bdT5Fx22AatU+eLaHfutoZdl+X9BETxn4/4+IVqx+daE87UU5bgm7XHzClQnm8VxHglxo5wj3H1fls=" X-RZG-CLASS-ID: mo05 Received: from fs-work.fritz.box by smtp.strato.de (RZmta 43.12 AUTH) with ESMTPSA id a0925bu65BHk4iC (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA (curve secp521r1 with 521 ECDH bits, eq. 15360 bits RSA)) (Client did not present a certificate); Thu, 5 Jul 2018 13:17:46 +0200 (CEST) From: Frieder Schrempf To: linux-mtd@lists.infradead.org, boris.brezillon@bootlin.com, linux-spi@vger.kernel.org Cc: dwmw2@infradead.org, computersforpeace@gmail.com, marek.vasut@gmail.com, richard@nod.at, miquel.raynal@bootlin.com, broonie@kernel.org, david.wolfe@nxp.com, fabio.estevam@nxp.com, prabhakar.kushwaha@nxp.com, yogeshnarayan.gaur@nxp.com, han.xu@nxp.com, shawnguo@kernel.org, Frieder Schrempf , Rob Herring , Mark Rutland , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 05/12] dt-bindings: spi: Adjust the bindings for the FSL QSPI driver Date: Thu, 5 Jul 2018 13:15:01 +0200 Message-Id: <1530789310-16254-6-git-send-email-frieder.schrempf@exceet.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1530789310-16254-1-git-send-email-frieder.schrempf@exceet.de> References: <1530789310-16254-1-git-send-email-frieder.schrempf@exceet.de> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Adjust the documentation of the new SPI memory interface based driver to reflect the new drivers settings. Signed-off-by: Frieder Schrempf --- Changes in v2: ============== * Split the moving and editing of the dt-bindings in two patches .../devicetree/bindings/spi/spi-fsl-qspi.txt | 22 ++++++++++---------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt index 483e9cf..8b4eed7 100644 --- a/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt +++ b/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt @@ -3,9 +3,8 @@ Required properties: - compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi", "fsl,imx7d-qspi", "fsl,imx6ul-qspi", - "fsl,ls1021a-qspi" + "fsl,ls1021a-qspi", "fsl,ls2080a-qspi" or - "fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi", "fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi" - reg : the first contains the register location and length, the second contains the memory mapping address and length @@ -15,14 +14,15 @@ Required properties: - clock-names : Should contain the name of the clocks: "qspi_en" and "qspi". Optional properties: - - fsl,qspi-has-second-chip: The controller has two buses, bus A and bus B. - Each bus can be connected with two NOR flashes. - Most of the time, each bus only has one NOR flash - connected, this is the default case. - But if there are two NOR flashes connected to the - bus, you should enable this property. - (Please check the board's schematic.) - - big-endian : That means the IP register is big endian + - big-endian : That means the IP registers format is big endian + +Required SPI slave node properties: + - reg: There are two buses (A and B) with two chip selects each. + This encodes to which bus and CS the flash is connected: + <0>: Bus A, CS 0 + <1>: Bus A, CS 1 + <2>: Bus B, CS 0 + <3>: Bus B, CS 1 Example: @@ -40,7 +40,7 @@ qspi0: quadspi@40044000 { }; }; -Example showing the usage of two SPI NOR devices: +Example showing the usage of two SPI NOR devices on bus A: &qspi2 { pinctrl-names = "default";