From patchwork Wed Jul 4 12:01:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siva Durga Prasad Paladugu X-Patchwork-Id: 939276 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=xilinx.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=xilinx.onmicrosoft.com header.i=@xilinx.onmicrosoft.com header.b="l+pw+rAZ"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41LKPN3yV2z9s29 for ; Wed, 4 Jul 2018 22:02:48 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id EEBD3C21F84; Wed, 4 Jul 2018 12:02:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=BAD_ENC_HEADER, SPF_HELO_PASS, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D475CC21F7F; Wed, 4 Jul 2018 12:02:25 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C62FDC21F8A; Wed, 4 Jul 2018 12:02:16 +0000 (UTC) Received: from NAM01-SN1-obe.outbound.protection.outlook.com (mail-sn1nam01on0061.outbound.protection.outlook.com [104.47.32.61]) by lists.denx.de (Postfix) with ESMTPS id 665D6C21F7A for ; Wed, 4 Jul 2018 12:02:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector1-xilinx-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=NJvmbwjrUVd5TeQ5KJ552Pn+/C7B7gH4xxpQYavpZ+c=; b=l+pw+rAZcLdkJgEqX9LYQgEM2LFRFoo+egYTFNOBixwxQhXjlF+lN4TrohCLG6z8DWO2E0He6FjhP0OfCwV1dWEukCOJ/RiYRLMhO/f7EuQfD2Vc8A6s4+9wd9CHc9c2WhNaz6miWXMKVNYaFGo5nFX+X9a35B5mpZLroY905No= Received: from SN6PR02CA0005.namprd02.prod.outlook.com (2603:10b6:805:a2::18) by DM5PR0201MB3511.namprd02.prod.outlook.com (2603:10b6:4:77::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.906.25; Wed, 4 Jul 2018 12:02:03 +0000 Received: from BL2NAM02FT045.eop-nam02.prod.protection.outlook.com (2a01:111:f400:7e46::208) by SN6PR02CA0005.outlook.office365.com (2603:10b6:805:a2::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.884.23 via Frontend Transport; Wed, 4 Jul 2018 12:02:03 +0000 Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; openedev.com; dkim=none (message not signed) header.d=none;openedev.com; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.83 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.83; helo=xsj-pvapsmtpgw01; Received: from xsj-pvapsmtpgw01 (149.199.60.83) by BL2NAM02FT045.mail.protection.outlook.com (10.152.77.16) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.20.906.15 via Frontend Transport; Wed, 4 Jul 2018 12:02:02 +0000 Received: from unknown-38-66.xilinx.com ([149.199.38.66] helo=xsj-pvapsmtp01) by xsj-pvapsmtpgw01 with esmtp (Exim 4.63) (envelope-from ) id 1fagTy-0007wR-5i; Wed, 04 Jul 2018 05:02:02 -0700 Received: from [127.0.0.1] (helo=localhost) by xsj-pvapsmtp01 with smtp (Exim 4.63) (envelope-from ) id 1fagTt-0007fS-1Y; Wed, 04 Jul 2018 05:01:57 -0700 Received: from xsj-pvapsmtp01 (xsj-smtp1.xilinx.com [149.199.38.66]) by xsj-smtp-dlp2.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id w64C1ks1003124; Wed, 4 Jul 2018 05:01:46 -0700 Received: from [172.23.37.99] (helo=xhdsivadur40.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1fagTh-0007b3-Vy; Wed, 04 Jul 2018 05:01:46 -0700 From: Siva Durga Prasad Paladugu To: Date: Wed, 4 Jul 2018 17:31:23 +0530 Message-ID: <1530705684-26826-1-git-send-email-siva.durga.paladugu@xilinx.com> X-Mailer: git-send-email 2.7.4 X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(39860400002)(376002)(396003)(346002)(136003)(2980300002)(438002)(199004)(189003)(186003)(575784001)(478600001)(77096007)(26005)(305945005)(5660300001)(486006)(50226002)(51416003)(14444005)(336012)(126002)(36386004)(2616005)(106002)(54906003)(426003)(356003)(476003)(50466002)(8936002)(63266004)(16586007)(47776003)(36756003)(4326008)(6916009)(48376002)(9786002)(81156014)(316002)(7696005)(6666003)(8676002)(107886003)(2351001)(81166006)(2906002)(106466001)(107986001); DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR0201MB3511; H:xsj-pvapsmtpgw01; FPR:; SPF:Pass; LANG:en; PTR:unknown-60-83.xilinx.com; A:1; MX:1; X-Microsoft-Exchange-Diagnostics: 1; BL2NAM02FT045; 1:TXYeA7CF/aYVLPe1jr1v/kWRG3FUjDL4w9OXwUL8NE7WCXbJ5cy6/ZfVZ3OvluSsKBVwIoVYQRXIFQQP6RzzIvU/SSXdnZzSdKwB3tK6Qxs1zrF95d7EjfSOKY1AkCq1 MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 45f326d6-de59-47cc-e13a-08d5e1a5f488 X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989117)(4534165)(4627221)(201703031133081)(201702281549075)(8990107)(5600053)(711020)(4608076)(2017052603328)(7153060); SRVR:DM5PR0201MB3511; X-Microsoft-Exchange-Diagnostics: 1; DM5PR0201MB3511; 3:IseuZ3kqMGt7ebJIbsa6WAbjlXpCYVWWruLffjEJnhTRE7CHEo6v10lE/9Thzk4phlbtXv3msuD0FBkgB5CM4+uzb0OVNAfgUrOLJBPyIVbX7qondlqT6P1AJx7MJYHEqT/m4UgKoaL7cCe9p7NYgRKjk9QTfJVrIM6yIkK5Wjiz8EMF/bn5BfvlPkWxqrscVpYwpjAjdWMct8cK3M+krERSOiwW5nmEdGhG8xA+6Ig4QmcWdIe91VSh12FFrRTKqn3EP7wKoJfGTM9w7Xc7moGSIZfvAkm/HyaZFeuw75uQsXvhkB3ME59hetoxZPeO4R9x0uXjBJnvzn93Tr1q8/TAf+3IlAglLcszW6gdhto=; 25:nG4cBu8qOZ3o2kx/JEj8TJ1tHAeuD7W2U5pEmoev+tE207y0LFn/xQkDWtOPvv8xm+QSmHPkD4tjXvBJtbr4MNzX19/kVt55vdGxAQQmA4qanQhdCRoyJVm4jzDJUYfVHRSRDQnF8JIJGjngakiO31dxmnwM8VNTyfxOo+8Iqei++Qc5YdS8STo0AGUhW6+6u4fNtg3FD0S9Pz6wMlJrM6GArWoFdsE6cOFZSufzAXcmZ4gN9SfvWaFUnCQJZpsDYEAa4K6frvjPqTelTKS5pDXVxhUjIriE4b1NvnedrfV8u3BaQxUJ9FsuAeFiwqoe1cbGEr+57LdHMYexolUbFQ== X-MS-TrafficTypeDiagnostic: DM5PR0201MB3511: X-Microsoft-Exchange-Diagnostics: 1; DM5PR0201MB3511; 31:YuAUfbEuCjSrzPaHiX9pBcbc4HoKUW5donJWsr1tJrd3zogk8Umt/8A8QITk9T8SNipn/mzso2UwTpF4g8qG5kOZe0L/CoUCBM9DYX9x7+AG2MTQbiwS20uYJF7B5bwBTtaC+TzB4izmV0+GzBfR6S+YrXI9oTfwVcR7U8kMYMo1IYdLToZcvfBPwvF1JaZfMTrqkSWOo/DwwKF8epE637PI25TSVBMeNEoSEEnFdH4=; 20:4REAx1zu4fqCWV/NZLeocqks1QM7C92LJlDQFrRtNK9f+7G4jnVZZzdh8tcPFe4KSm2JQAq13wQn5UGId1sh4OtUY2rVx/KDSGWNyy30XiCvQ8ypWw7gQw0zG7cfCTp04whUSIW4u7a0/cki8hzk8jHDohDGjQ6T0Vggxksxy6Jb2sYXkryV0zFk7StSFEFBEujX9IRCBF8FTG+Ab4dYGeZARf0sbtrHzJolIlHnwdTebE5HXCnxJyWyGbIYgVimePYXeFDZlITHqQW/xHOI0qpTk0EdwEn+q5EeDFZhvpDYf15CIi7grN9fB8EF9ZMAgS989RI7ZOViQw8qd7+eulQ5puP9hU84Sxabue7pGMrtyCvMgmPXIZZ28GzTrz+jCphD/+5U63iquNKPsPwamNJDMIx17b9ja9AQ1QqOf0RAMGULCnAPErsBmWIuChqS9bpLHNDrFQBhRDmOiRVCq5tp13aWFeC4GHUZNnouI2L24L3thraWmQL60lKVtuAo X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(192813158149592)(21532816269658); X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(3002001)(3231254)(944501410)(52105095)(93006095)(93004095)(10201501046)(6055026)(149027)(150027)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123562045)(20161123558120)(20161123564045)(20161123560045)(6072148)(201708071742011)(7699016); SRVR:DM5PR0201MB3511; BCL:0; PCL:0; RULEID:; SRVR:DM5PR0201MB3511; X-Microsoft-Exchange-Diagnostics: 1; DM5PR0201MB3511; 4:ffPzR46Pyi2kI7r3jItXUBJEI6FbQHwvzDR61SC0KT+YzxqQoNnGSAb5kF2b8bXg7pCDomN8YscUY7m4T2hGx4AGCmKMQGB0t2PGuAa6HMEn3EOYQUqXApe8kRSAJnB1yt9TfVU39OUAPj002Tg1uQPO9/QVarprFIxCAhEk9qzQizlpWfewNIO+NPSp9TeSd2czW/VirUkQ0v9WObbhegDKFW/pKTOy9orkDjXYbYINSmY6Li6V4WNUCg+EQDUyztQW7Q5tv3cOauDF0FEDjgjXimoaz9ZmFCHYXC4Xi9kTeBOGVSmpIrLWfQaDh9bydsrgVd47pmaqQmT6lOcmYXMxmoBnOz0VQSRaD1nyAFs= X-Forefront-PRVS: 0723A02764 X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; DM5PR0201MB3511; 23:c5HGTHLMxItpAs+KYCaEOwnSUpoouAy3JMGuDRQ?= MyHc1ju0zNjWsAIGqECx2dxdIn2Z3MXggNcCDycyOKX8iUOi+utYqSgsG6HlOziD8lOGDPCGWrsQ/6yBSx1lnOe238hxv6yTNZM4ZMoQI/V2Pa0JkW1xbVOWPW7Q9uZN0ZyCBzR0XzTgCytQc5wf8C6zHKKcSGU0EjfWe2VoxQ2rIDBYVsyMBJf5M1hbfNIYpMblQF2gLyc0MOwJAWqtDb4WCn1ZeuFbWHQLkZtJ1swp3khVxAxNmWGHuHjywGwgCgGcryVeE856xTk3P+oKSqvz4w/YgOVV74Vr+1y5rZreb3d2hDhFAzQSdafTuie8OZdCnLM/s7TXZvV2n1CVPjjC5EnW7zTO50d2iJoyfgSPZ3H3URTCWrfrjkSY8e5t2rAW6WoCDR7ksF+d+XRv6BjB6Lk/ORU26xERKFMb807qE7heL30jM0NpB9M9IXF5wjEhv+xyGwQhMRC2wgSZyGgNbrCzQSPDqj2lOPe1kD23EhG6nNZIqq7L3btaivKqmoVgTI+55VVtP+Yo9lCzvyadwl9oq0md5tIVlMQh/34jmWh6N4qlA7l11GMxy405pb/l6sUR6LMxlmwyQ0CpOygr9qTd1zxlQAohFtWQhBSaxW25NVxC5GLySzfRJUTCuh6ryyqW4Jw2QSgK/RfYNuCGBRVriEj2BEVhisSObeExSmiYOTBDdAGYkA5QZIJ2BgzFflMmwP2fc4fmIjmwlAA33pWVSpg+XTeNw8rAskgRxIcJ0qanVfTmF57zGJ++W/2P9Dy+d0GsTVz7jBTXXqJWSrZYmkckeXpn7xrVXBiLZQ82q1eDWywdUzfd9jcmQuX4QqJNpIjUH0LKjOEnh09CC52yIQRM+7bAWnqZ1+bgRiO++ZEOhSOQ1sIK2HNOYogH0gClOxee5hmuG1e3ia6c6/Sv+4gbLdMcxtB19PgCtj+/PrudqZCG8EFEHoimfBVNep3wxL2UxKVljHBQCPIsrvNndksBENy7AENyI6rF7VeVkeHiiI1JDzzFNJpt+VXN7NTt65X/B5YorafQ8z4HmupecBHp+2X0rnDJsdtnMpw== X-Microsoft-Antispam-Message-Info: X39jGmCrliervlRUhHGjFiWcAozzNTRCnvEF/U9ivuuwPZlBSUeBdHE4N/YpTjtb4N5C2NRYTrdQ7tJDxwW1y+8o3VOPXgW6J/1h54j3y/YberMbsXu7bfX9x9mTpo3yomq9eIozr0LckCdoFq472/RvoWmsXSgxVgpFi+DGK802FnCxeRweVyAcRUJ9jZCtdWKeh1ephxmzWRzNr7TNuu6RTUXTO4YNCXmNkxpmtwNHYj2HpjdAj9RjQotpzj0a083BODv35fqAn+WgG4qo0pIgjXBBXzya3FT4ekmdx7Yp1NPwGuyPUcpi/qhWL1TPV2WHrlT1Cc+7ljexLYe1L9Zoadhop3sFT8clxhwGX78= X-Microsoft-Exchange-Diagnostics: 1; DM5PR0201MB3511; 6:XGaLlc6v8Km+2zBqMH5m4CK8DwpbdjgN0z+RVwrh88qoOjSLsqucXbq4wbbuJ3epFPlwoR9cbyfBLVYhcgejGAnBJa06ajnmydk7KFm4sXMJjWWGzpRb9uToCM5nSdFOScZDcoUCMPfLdPTHzYJfbyTWE+WnC0ChiGYQEiScGJ3JrrU8Y1KDmqQeQPGJkXHHLAkXJuwiEtrclf+6ZKFKfP6k7VEKF9MF3aQmwmhnG9G06CLirN4KwNFRd/8Yhgkx3Z3GRz2LthbzloTWvQofrwmlhh0DmFJtA90mEy8kmMD2D2oRXawTAthX5qAlURGKBU1H7AGYv+AYmpDC4KMYmr0ZyMlmpg87oICCxfKkdy1jZ0B3680y378JiUPns4L3Ym1s/Lp5bfzISLkvgYDcPZLjMMk/DZnipnNL0CdbcnON9yZlEKlSvQGuGBTNlHnuWvWHYFjuW8AmMx3o11kaDQ==; 5:cJrdPy0LNFV2RTSbIVXVfG4H+91YIDE4nf2p75cBL644xruntyraauMc/9ZE4hu6eBfk4zXe/KcTV1vLSKtry8PrBdgOeayci7qOq5PUqLPdQ8XYsmJkanQVB5DeYOAFZa/2vBJ5OawB7mvlGqnLKNgAG7/yS/kj+CE18vOhIaI=; 24:eE5UwH37YIy5+W1kBKQgBg7pVFCXbaLtRI4I3w29/Yj+Qef2iEF2DoFMP4qoiakAsKv3LwPbzfHJTmYaO3nRRetRMpkr1NOmT+TJgYlSrSE= SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-Microsoft-Exchange-Diagnostics: 1; DM5PR0201MB3511; 7:PElGv3tJDAX5t46lgvDC4TljV5lw4/v1Wgj6cohn49qxpAd83N8Jcm56ueORGICLlr7YhBVBw2sqhpDmQdWac+/rRaY2aFZpFge9/0fvxD0Rm/JoAtOugyOSLzKoEgzo3jcOKMe3RS1/VgQSEQr/uRaswM2y546+bNlofy+QSoUpOVyjSnDlef4THGee93HnjO813MmkAyLjW8hRqiP2Sc6XBFOm8c8cYSv/4Qwa6Zr5NZx9AOCXeZV6pzDL/zf6 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jul 2018 12:02:02.7507 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 45f326d6-de59-47cc-e13a-08d5e1a5f488 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR0201MB3511 Cc: jagan@openedev.com, michal.simek@xilinx.com Subject: [U-Boot] [PATCH v7 1/2] spi: zynqmp_gqspi: Add support for ZynqMP qspi driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch adds qspi driver support for ZynqMP SoC. This driver is responsible for communicating with qspi flash devices. Signed-off-by: Siva Durga Prasad Paladugu Reviewed-by: Jagan Teki --- Changes for v7: - Removed reading of mode, clock phase and polarity from ofdata_to_platdata as drivercan get from spi-uclass if required Changes for v6: - Removed spi_flash.h inclusion and other unused macros - Fixed coding style comments - Removed tx_rx_mode in plat and removed preprobe routine. - Used proper error codes Changed for v5: - Removed zynqm_gqspi.h file which was added by mistake. Changes for v4: - Moved macro definitions back to .c - Removed last_cmd and flash command checks in driver - Used macros and GENMASK as per comments - Removed debugs wherever commented. - Modified set_mode routine as per comment Changes for v3: - Renamed all macros, functions, files and configs as per comment - Used wait_for_bit wherever required - Removed unnecessary header inclusion Changes for v2: - Rebased on top of latest master - Moved macro definitions to .h file as per comment - Fixed magic values with macros as per comment --- drivers/spi/Kconfig | 7 + drivers/spi/Makefile | 1 + drivers/spi/zynqmp_gqspi.c | 734 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 742 insertions(+) create mode 100644 drivers/spi/zynqmp_gqspi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 3532c2a..c3c424e 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -223,6 +223,13 @@ config ZYNQ_QSPI Zynq QSPI IP core. This IP is used to connect the flash in 4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel. +config ZYNQMP_GQSPI + bool "Configure ZynqMP Generic QSPI" + depends on ARCH_ZYNQMP + help + This option is used to enable ZynqMP QSPI controller driver which + is used to communicate with qspi flash devices. + endif # if DM_SPI config SOFT_SPI diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 5a2c00e..2187633 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -51,3 +51,4 @@ obj-$(CONFIG_TI_QSPI) += ti_qspi.o obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o obj-$(CONFIG_ZYNQ_QSPI) += zynq_qspi.o +obj-$(CONFIG_ZYNQMP_GQSPI) += zynqmp_gqspi.o diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c new file mode 100644 index 0000000..665f98e --- /dev/null +++ b/drivers/spi/zynqmp_gqspi.c @@ -0,0 +1,734 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2018 Xilinx + * + * Xilinx ZynqMP Generic Quad-SPI(QSPI) controller driver(master mode only) + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define GQSPI_GFIFO_STRT_MODE_MASK BIT(29) +#define GQSPI_CONFIG_MODE_EN_MASK (3 << 30) +#define GQSPI_CONFIG_DMA_MODE (2 << 30) +#define GQSPI_CONFIG_CPHA_MASK BIT(2) +#define GQSPI_CONFIG_CPOL_MASK BIT(1) + +/* QSPI MIO's count for different connection topologies */ +#define GQSPI_MIO_NUM_QSPI0 6 +#define GQSPI_MIO_NUM_QSPI1 5 +#define GQSPI_MIO_NUM_QSPI1_CS 1 + +/* + * QSPI Interrupt Registers bit Masks + * + * All the four interrupt registers (Status/Mask/Enable/Disable) have the same + * bit definitions. + */ +#define GQSPI_IXR_TXNFULL_MASK 0x00000004 /* QSPI TX FIFO Overflow */ +#define GQSPI_IXR_TXFULL_MASK 0x00000008 /* QSPI TX FIFO is full */ +#define GQSPI_IXR_RXNEMTY_MASK 0x00000010 /* QSPI RX FIFO Not Empty */ +#define GQSPI_IXR_GFEMTY_MASK 0x00000080 /* QSPI Generic FIFO Empty */ +#define GQSPI_IXR_ALL_MASK (GQSPI_IXR_TXNFULL_MASK | \ + GQSPI_IXR_RXNEMTY_MASK) + +/* + * QSPI Enable Register bit Masks + * + * This register is used to enable or disable the QSPI controller + */ +#define GQSPI_ENABLE_ENABLE_MASK 0x00000001 /* QSPI Enable Bit Mask */ + +#define GQSPI_GFIFO_LOW_BUS BIT(14) +#define GQSPI_GFIFO_CS_LOWER BIT(12) +#define GQSPI_GFIFO_UP_BUS BIT(15) +#define GQSPI_GFIFO_CS_UPPER BIT(13) +#define GQSPI_SPI_MODE_QSPI (3 << 10) +#define GQSPI_SPI_MODE_SPI BIT(10) +#define GQSPI_SPI_MODE_DUAL_SPI (2 << 10) +#define GQSPI_IMD_DATA_CS_ASSERT 5 +#define GQSPI_IMD_DATA_CS_DEASSERT 5 +#define GQSPI_GFIFO_TX BIT(16) +#define GQSPI_GFIFO_RX BIT(17) +#define GQSPI_GFIFO_STRIPE_MASK BIT(18) +#define GQSPI_GFIFO_IMD_MASK 0xFF +#define GQSPI_GFIFO_EXP_MASK BIT(9) +#define GQSPI_GFIFO_DATA_XFR_MASK BIT(8) +#define GQSPI_STRT_GEN_FIFO BIT(28) +#define GQSPI_GEN_FIFO_STRT_MOD BIT(29) +#define GQSPI_GFIFO_WP_HOLD BIT(19) +#define GQSPI_BAUD_DIV_MASK (7 << 3) +#define GQSPI_DFLT_BAUD_RATE_DIV BIT(3) +#define GQSPI_GFIFO_ALL_INT_MASK 0xFBE +#define GQSPI_DMA_DST_I_STS_DONE BIT(1) +#define GQSPI_DMA_DST_I_STS_MASK 0xFE +#define MODEBITS 0x6 + +#define GQSPI_GFIFO_SELECT BIT(0) +#define GQSPI_FIFO_THRESHOLD 1 + +#define SPI_XFER_ON_BOTH 0 +#define SPI_XFER_ON_LOWER 1 +#define SPI_XFER_ON_UPPER 2 + +#define GQSPI_DMA_ALIGN 0x4 +#define GQSPI_MAX_BAUD_RATE_VAL 7 +#define GQSPI_DFLT_BAUD_RATE_VAL 2 + +#define GQSPI_TIMEOUT 100000000 + +#define GQSPI_BAUD_DIV_SHIFT 2 +#define GQSPI_LPBK_DLY_ADJ_LPBK_SHIFT 5 +#define GQSPI_LPBK_DLY_ADJ_DLY_1 0x2 +#define GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT 3 +#define GQSPI_LPBK_DLY_ADJ_DLY_0 0x3 +#define GQSPI_USE_DATA_DLY 0x1 +#define GQSPI_USE_DATA_DLY_SHIFT 31 +#define GQSPI_DATA_DLY_ADJ_VALUE 0x2 +#define GQSPI_DATA_DLY_ADJ_SHIFT 28 +#define TAP_DLY_BYPASS_LQSPI_RX_VALUE 0x1 +#define TAP_DLY_BYPASS_LQSPI_RX_SHIFT 2 +#define GQSPI_DATA_DLY_ADJ_OFST 0x000001F8 +#define IOU_TAPDLY_BYPASS_OFST 0xFF180390 +#define GQSPI_LPBK_DLY_ADJ_LPBK_MASK 0x00000020 +#define GQSPI_FREQ_40MHZ 40000000 +#define GQSPI_FREQ_100MHZ 100000000 +#define GQSPI_FREQ_150MHZ 150000000 +#define IOU_TAPDLY_BYPASS_MASK 0x7 + +#define GQSPI_REG_OFFSET 0x100 +#define GQSPI_DMA_REG_OFFSET 0x800 + +/* QSPI register offsets */ +struct zynqmp_qspi_regs { + u32 confr; /* 0x00 */ + u32 isr; /* 0x04 */ + u32 ier; /* 0x08 */ + u32 idisr; /* 0x0C */ + u32 imaskr; /* 0x10 */ + u32 enbr; /* 0x14 */ + u32 dr; /* 0x18 */ + u32 txd0r; /* 0x1C */ + u32 drxr; /* 0x20 */ + u32 sicr; /* 0x24 */ + u32 txftr; /* 0x28 */ + u32 rxftr; /* 0x2C */ + u32 gpior; /* 0x30 */ + u32 reserved0; /* 0x34 */ + u32 lpbkdly; /* 0x38 */ + u32 reserved1; /* 0x3C */ + u32 genfifo; /* 0x40 */ + u32 gqspisel; /* 0x44 */ + u32 reserved2; /* 0x48 */ + u32 gqfifoctrl; /* 0x4C */ + u32 gqfthr; /* 0x50 */ + u32 gqpollcfg; /* 0x54 */ + u32 gqpollto; /* 0x58 */ + u32 gqxfersts; /* 0x5C */ + u32 gqfifosnap; /* 0x60 */ + u32 gqrxcpy; /* 0x64 */ + u32 reserved3[36]; /* 0x68 */ + u32 gqspidlyadj; /* 0xF8 */ +}; + +struct zynqmp_qspi_dma_regs { + u32 dmadst; /* 0x00 */ + u32 dmasize; /* 0x04 */ + u32 dmasts; /* 0x08 */ + u32 dmactrl; /* 0x0C */ + u32 reserved0; /* 0x10 */ + u32 dmaisr; /* 0x14 */ + u32 dmaier; /* 0x18 */ + u32 dmaidr; /* 0x1C */ + u32 dmaimr; /* 0x20 */ + u32 dmactrl2; /* 0x24 */ + u32 dmadstmsb; /* 0x28 */ +}; + +DECLARE_GLOBAL_DATA_PTR; + +struct zynqmp_qspi_platdata { + struct zynqmp_qspi_regs *regs; + struct zynqmp_qspi_dma_regs *dma_regs; + u32 frequency; + u32 speed_hz; +}; + +struct zynqmp_qspi_priv { + struct zynqmp_qspi_regs *regs; + struct zynqmp_qspi_dma_regs *dma_regs; + const void *tx_buf; + void *rx_buf; + unsigned int len; + int bytes_to_transfer; + int bytes_to_receive; + unsigned int is_inst; + unsigned int cs_change:1; +}; + +static int zynqmp_qspi_ofdata_to_platdata(struct udevice *bus) +{ + struct zynqmp_qspi_platdata *plat = bus->platdata; + + debug("%s\n", __func__); + + plat->regs = (struct zynqmp_qspi_regs *)(devfdt_get_addr(bus) + + GQSPI_REG_OFFSET); + plat->dma_regs = (struct zynqmp_qspi_dma_regs *) + (devfdt_get_addr(bus) + GQSPI_DMA_REG_OFFSET); + + return 0; +} + +static void zynqmp_qspi_init_hw(struct zynqmp_qspi_priv *priv) +{ + u32 config_reg; + struct zynqmp_qspi_regs *regs = priv->regs; + + writel(GQSPI_GFIFO_SELECT, ®s->gqspisel); + writel(GQSPI_GFIFO_ALL_INT_MASK, ®s->idisr); + writel(GQSPI_FIFO_THRESHOLD, ®s->txftr); + writel(GQSPI_FIFO_THRESHOLD, ®s->rxftr); + writel(GQSPI_GFIFO_ALL_INT_MASK, ®s->isr); + + config_reg = readl(®s->confr); + config_reg &= ~(GQSPI_GFIFO_STRT_MODE_MASK | + GQSPI_CONFIG_MODE_EN_MASK); + config_reg |= GQSPI_CONFIG_DMA_MODE | + GQSPI_GFIFO_WP_HOLD | + GQSPI_DFLT_BAUD_RATE_DIV; + writel(config_reg, ®s->confr); + + writel(GQSPI_ENABLE_ENABLE_MASK, ®s->enbr); +} + +static u32 zynqmp_qspi_bus_select(struct zynqmp_qspi_priv *priv) +{ + u32 gqspi_fifo_reg = 0; + + gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS | + GQSPI_GFIFO_CS_LOWER; + + return gqspi_fifo_reg; +} + +static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv, + u32 gqspi_fifo_reg) +{ + struct zynqmp_qspi_regs *regs = priv->regs; + int ret = 0; + + ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_GFEMTY_MASK, 1, + GQSPI_TIMEOUT, 1); + if (ret) + printf("%s Timeout\n", __func__); + + writel(gqspi_fifo_reg, ®s->genfifo); +} + +static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on) +{ + u32 gqspi_fifo_reg = 0; + + if (is_on) { + gqspi_fifo_reg = zynqmp_qspi_bus_select(priv); + gqspi_fifo_reg |= GQSPI_SPI_MODE_SPI | + GQSPI_IMD_DATA_CS_ASSERT; + } else { + gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS; + gqspi_fifo_reg |= GQSPI_IMD_DATA_CS_DEASSERT; + } + + debug("GFIFO_CMD_CS: 0x%x\n", gqspi_fifo_reg); + + zynqmp_qspi_fill_gen_fifo(priv, gqspi_fifo_reg); +} + +void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval) +{ + struct zynqmp_qspi_platdata *plat = bus->platdata; + struct zynqmp_qspi_priv *priv = dev_get_priv(bus); + struct zynqmp_qspi_regs *regs = priv->regs; + u32 tapdlybypass = 0, lpbkdlyadj = 0, datadlyadj = 0, clk_rate; + u32 reqhz = 0; + + clk_rate = plat->frequency; + reqhz = (clk_rate / (GQSPI_BAUD_DIV_SHIFT << baudrateval)); + + debug("%s, req_hz:%d, clk_rate:%d, baudrateval:%d\n", + __func__, reqhz, clk_rate, baudrateval); + + if (reqhz < GQSPI_FREQ_40MHZ) { + zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass); + tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE << + TAP_DLY_BYPASS_LQSPI_RX_SHIFT); + } else if (reqhz < GQSPI_FREQ_100MHZ) { + zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass); + tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE << + TAP_DLY_BYPASS_LQSPI_RX_SHIFT); + lpbkdlyadj = readl(®s->lpbkdly); + lpbkdlyadj |= (GQSPI_LPBK_DLY_ADJ_LPBK_MASK); + datadlyadj = readl(®s->gqspidlyadj); + datadlyadj |= ((GQSPI_USE_DATA_DLY << GQSPI_USE_DATA_DLY_SHIFT) + | (GQSPI_DATA_DLY_ADJ_VALUE << + GQSPI_DATA_DLY_ADJ_SHIFT)); + } else if (reqhz < GQSPI_FREQ_150MHZ) { + lpbkdlyadj = readl(®s->lpbkdly); + lpbkdlyadj |= ((GQSPI_LPBK_DLY_ADJ_LPBK_MASK) | + GQSPI_LPBK_DLY_ADJ_DLY_0); + } + + zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST, IOU_TAPDLY_BYPASS_MASK, + tapdlybypass); + writel(lpbkdlyadj, ®s->lpbkdly); + writel(datadlyadj, ®s->gqspidlyadj); +} + +static int zynqmp_qspi_set_speed(struct udevice *bus, uint speed) +{ + struct zynqmp_qspi_platdata *plat = bus->platdata; + struct zynqmp_qspi_priv *priv = dev_get_priv(bus); + struct zynqmp_qspi_regs *regs = priv->regs; + u32 confr; + u8 baud_rate_val = 0; + + debug("%s\n", __func__); + if (speed > plat->frequency) + speed = plat->frequency; + + /* Set the clock frequency */ + confr = readl(®s->confr); + if (speed == 0) { + /* Set baudrate x8, if the freq is 0 */ + baud_rate_val = GQSPI_DFLT_BAUD_RATE_VAL; + } else if (plat->speed_hz != speed) { + while ((baud_rate_val < 8) && + ((plat->frequency / + (2 << baud_rate_val)) > speed)) + baud_rate_val++; + + if (baud_rate_val > GQSPI_MAX_BAUD_RATE_VAL) + baud_rate_val = GQSPI_DFLT_BAUD_RATE_VAL; + + plat->speed_hz = plat->frequency / (2 << baud_rate_val); + } + confr &= ~GQSPI_BAUD_DIV_MASK; + confr |= (baud_rate_val << 3); + writel(confr, ®s->confr); + + zynqmp_qspi_set_tapdelay(bus, baud_rate_val); + debug("regs=%p, speed=%d\n", priv->regs, plat->speed_hz); + + return 0; +} + +static int zynqmp_qspi_probe(struct udevice *bus) +{ + struct zynqmp_qspi_platdata *plat = dev_get_platdata(bus); + struct zynqmp_qspi_priv *priv = dev_get_priv(bus); + struct clk clk; + unsigned long clock; + int ret; + + debug("%s: bus:%p, priv:%p\n", __func__, bus, priv); + + priv->regs = plat->regs; + priv->dma_regs = plat->dma_regs; + + ret = clk_get_by_index(bus, 0, &clk); + if (ret < 0) { + dev_err(dev, "failed to get clock\n"); + return ret; + } + + clock = clk_get_rate(&clk); + if (IS_ERR_VALUE(clock)) { + dev_err(dev, "failed to get rate\n"); + return clock; + } + debug("%s: CLK %ld\n", __func__, clock); + + ret = clk_enable(&clk); + if (ret && ret != -ENOSYS) { + dev_err(dev, "failed to enable clock\n"); + return ret; + } + plat->frequency = clock; + plat->speed_hz = plat->frequency / 2; + + /* init the zynq spi hw */ + zynqmp_qspi_init_hw(priv); + + return 0; +} + +static int zynqmp_qspi_set_mode(struct udevice *bus, uint mode) +{ + struct zynqmp_qspi_priv *priv = dev_get_priv(bus); + struct zynqmp_qspi_regs *regs = priv->regs; + u32 confr; + + debug("%s\n", __func__); + /* Set the SPI Clock phase and polarities */ + confr = readl(®s->confr); + confr &= ~(GQSPI_CONFIG_CPHA_MASK | + GQSPI_CONFIG_CPOL_MASK); + + if (mode & SPI_CPHA) + confr |= GQSPI_CONFIG_CPHA_MASK; + if (mode & SPI_CPOL) + confr |= GQSPI_CONFIG_CPOL_MASK; + + writel(confr, ®s->confr); + + return 0; +} + +static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size) +{ + u32 data; + int ret = 0; + struct zynqmp_qspi_regs *regs = priv->regs; + u32 *buf = (u32 *)priv->tx_buf; + u32 len = size; + + debug("TxFIFO: 0x%x, size: 0x%x\n", readl(®s->isr), + size); + + while (size) { + ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_TXNFULL_MASK, 1, + GQSPI_TIMEOUT, 1); + if (ret) { + printf("%s: Timeout\n", __func__); + return ret; + } + + if (size >= 4) { + writel(*buf, ®s->txd0r); + buf++; + size -= 4; + } else { + switch (size) { + case 1: + data = *((u8 *)buf); + buf += 1; + data |= GENMASK(31, 8); + break; + case 2: + data = *((u16 *)buf); + buf += 2; + data |= GENMASK(31, 16); + break; + case 3: + data = *((u16 *)buf); + buf += 2; + data |= (*((u8 *)buf) << 16); + buf += 1; + data |= GENMASK(31, 24); + break; + } + writel(data, ®s->txd0r); + size = 0; + } + } + + priv->tx_buf += len; + return 0; +} + +static void zynqmp_qspi_genfifo_cmd(struct zynqmp_qspi_priv *priv) +{ + u32 gen_fifo_cmd; + u32 bytecount = 0; + + while (priv->len) { + gen_fifo_cmd = zynqmp_qspi_bus_select(priv); + gen_fifo_cmd |= GQSPI_GFIFO_TX | GQSPI_SPI_MODE_SPI; + gen_fifo_cmd |= *(u8 *)priv->tx_buf; + bytecount++; + priv->len--; + priv->tx_buf = (u8 *)priv->tx_buf + 1; + + debug("GFIFO_CMD_Cmd = 0x%x\n", gen_fifo_cmd); + + zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd); + } +} + +static u32 zynqmp_qspi_calc_exp(struct zynqmp_qspi_priv *priv, + u32 *gen_fifo_cmd) +{ + u32 expval = 8; + u32 len; + + while (1) { + if (priv->len > 255) { + if (priv->len & (1 << expval)) { + *gen_fifo_cmd &= ~GQSPI_GFIFO_IMD_MASK; + *gen_fifo_cmd |= GQSPI_GFIFO_EXP_MASK; + *gen_fifo_cmd |= expval; + priv->len -= (1 << expval); + return expval; + } + expval++; + } else { + *gen_fifo_cmd &= ~(GQSPI_GFIFO_IMD_MASK | + GQSPI_GFIFO_EXP_MASK); + *gen_fifo_cmd |= (u8)priv->len; + len = (u8)priv->len; + priv->len = 0; + return len; + } + } +} + +static int zynqmp_qspi_genfifo_fill_tx(struct zynqmp_qspi_priv *priv) +{ + u32 gen_fifo_cmd; + u32 len; + int ret = 0; + + gen_fifo_cmd = zynqmp_qspi_bus_select(priv); + gen_fifo_cmd |= GQSPI_GFIFO_TX | + GQSPI_GFIFO_DATA_XFR_MASK; + + gen_fifo_cmd |= GQSPI_SPI_MODE_SPI; + + while (priv->len) { + len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd); + zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd); + + debug("GFIFO_CMD_TX:0x%x\n", gen_fifo_cmd); + + if (gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK) + ret = zynqmp_qspi_fill_tx_fifo(priv, + 1 << len); + else + ret = zynqmp_qspi_fill_tx_fifo(priv, + len); + + if (ret) + return ret; + } + return ret; +} + +static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv, + u32 gen_fifo_cmd, u32 *buf) +{ + u32 addr; + u32 size, len; + u32 actuallen = priv->len; + int ret = 0; + struct zynqmp_qspi_dma_regs *dma_regs = priv->dma_regs; + + writel((unsigned long)buf, &dma_regs->dmadst); + writel(roundup(priv->len, ARCH_DMA_MINALIGN), &dma_regs->dmasize); + writel(GQSPI_DMA_DST_I_STS_MASK, &dma_regs->dmaier); + addr = (unsigned long)buf; + size = roundup(priv->len, ARCH_DMA_MINALIGN); + flush_dcache_range(addr, addr + size); + + while (priv->len) { + len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd); + if (!(gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK) && + (len % ARCH_DMA_MINALIGN)) { + gen_fifo_cmd &= ~GENMASK(7, 0); + gen_fifo_cmd |= roundup(len, ARCH_DMA_MINALIGN); + } + zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd); + + debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd); + } + + ret = wait_for_bit_le32(&dma_regs->dmaisr, GQSPI_DMA_DST_I_STS_DONE, + 1, GQSPI_TIMEOUT, 1); + if (ret) { + printf("DMA Timeout:0x%x\n", readl(&dma_regs->dmaisr)); + return -ETIMEDOUT; + } + + writel(GQSPI_DMA_DST_I_STS_DONE, &dma_regs->dmaisr); + + debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n", + (unsigned long)buf, (unsigned long)priv->rx_buf, *buf, + actuallen); + + if (buf != priv->rx_buf) + memcpy(priv->rx_buf, buf, actuallen); + + return 0; +} + +static int zynqmp_qspi_genfifo_fill_rx(struct zynqmp_qspi_priv *priv) +{ + u32 gen_fifo_cmd; + u32 *buf; + u32 actuallen = priv->len; + + gen_fifo_cmd = zynqmp_qspi_bus_select(priv); + gen_fifo_cmd |= GQSPI_GFIFO_RX | + GQSPI_GFIFO_DATA_XFR_MASK; + + gen_fifo_cmd |= GQSPI_SPI_MODE_SPI; + + /* + * Check if receive buffer is aligned to 4 byte and length + * is multiples of four byte as we are using dma to receive. + */ + if (!((unsigned long)priv->rx_buf & (GQSPI_DMA_ALIGN - 1)) && + !(actuallen % GQSPI_DMA_ALIGN)) { + buf = (u32 *)priv->rx_buf; + return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf); + } + + ALLOC_CACHE_ALIGN_BUFFER(u8, tmp, roundup(priv->len, + GQSPI_DMA_ALIGN)); + buf = (u32 *)tmp; + return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf); +} + +static int zynqmp_qspi_start_transfer(struct zynqmp_qspi_priv *priv) +{ + int ret = 0; + + if (priv->is_inst) { + if (priv->tx_buf) + zynqmp_qspi_genfifo_cmd(priv); + else + return -EINVAL; + } else { + if (priv->tx_buf) + ret = zynqmp_qspi_genfifo_fill_tx(priv); + else if (priv->rx_buf) + ret = zynqmp_qspi_genfifo_fill_rx(priv); + else + return -EINVAL; + } + return ret; +} + +static int zynqmp_qspi_transfer(struct zynqmp_qspi_priv *priv) +{ + static unsigned int cs_change = 1; + int status = 0; + + debug("%s\n", __func__); + + while (1) { + /* Select the chip if required */ + if (cs_change) + zynqmp_qspi_chipselect(priv, 1); + + cs_change = priv->cs_change; + + if (!priv->tx_buf && !priv->rx_buf && priv->len) { + status = -EINVAL; + break; + } + + /* Request the transfer */ + if (priv->len) { + status = zynqmp_qspi_start_transfer(priv); + priv->is_inst = 0; + if (status < 0) + break; + } + + if (cs_change) + /* Deselect the chip */ + zynqmp_qspi_chipselect(priv, 0); + break; + } + + return status; +} + +static int zynqmp_qspi_claim_bus(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct zynqmp_qspi_priv *priv = dev_get_priv(bus); + struct zynqmp_qspi_regs *regs = priv->regs; + + writel(GQSPI_ENABLE_ENABLE_MASK, ®s->enbr); + + return 0; +} + +static int zynqmp_qspi_release_bus(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct zynqmp_qspi_priv *priv = dev_get_priv(bus); + struct zynqmp_qspi_regs *regs = priv->regs; + + writel(~GQSPI_ENABLE_ENABLE_MASK, ®s->enbr); + + return 0; +} + +int zynqmp_qspi_xfer(struct udevice *dev, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct zynqmp_qspi_priv *priv = dev_get_priv(bus); + + debug("%s: priv: 0x%08lx bitlen: %d dout: 0x%08lx ", __func__, + (unsigned long)priv, bitlen, (unsigned long)dout); + debug("din: 0x%08lx flags: 0x%lx\n", (unsigned long)din, flags); + + priv->tx_buf = dout; + priv->rx_buf = din; + priv->len = bitlen / 8; + + /* + * Assume that the beginning of a transfer with bits to + * transmit must contain a device command. + */ + if (dout && flags & SPI_XFER_BEGIN) + priv->is_inst = 1; + else + priv->is_inst = 0; + + if (flags & SPI_XFER_END) + priv->cs_change = 1; + else + priv->cs_change = 0; + + zynqmp_qspi_transfer(priv); + + return 0; +} + +static const struct dm_spi_ops zynqmp_qspi_ops = { + .claim_bus = zynqmp_qspi_claim_bus, + .release_bus = zynqmp_qspi_release_bus, + .xfer = zynqmp_qspi_xfer, + .set_speed = zynqmp_qspi_set_speed, + .set_mode = zynqmp_qspi_set_mode, +}; + +static const struct udevice_id zynqmp_qspi_ids[] = { + { .compatible = "xlnx,zynqmp-qspi-1.0" }, + { } +}; + +U_BOOT_DRIVER(zynqmp_qspi) = { + .name = "zynqmp_qspi", + .id = UCLASS_SPI, + .of_match = zynqmp_qspi_ids, + .ops = &zynqmp_qspi_ops, + .ofdata_to_platdata = zynqmp_qspi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct zynqmp_qspi_platdata), + .priv_auto_alloc_size = sizeof(struct zynqmp_qspi_priv), + .probe = zynqmp_qspi_probe, +}; From patchwork Wed Jul 4 12:01:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siva Durga Prasad Paladugu X-Patchwork-Id: 939275 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=xilinx.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=xilinx.onmicrosoft.com header.i=@xilinx.onmicrosoft.com header.b="r6+d9xU5"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41LKNr2SBqz9s29 for ; Wed, 4 Jul 2018 22:02:18 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 2A746C21F8C; Wed, 4 Jul 2018 12:02:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=BAD_ENC_HEADER, SPF_HELO_PASS, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E4E10C21F05; Wed, 4 Jul 2018 12:02:07 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 33500C21F05; Wed, 4 Jul 2018 12:02:06 +0000 (UTC) Received: from NAM01-SN1-obe.outbound.protection.outlook.com (mail-sn1nam01on0058.outbound.protection.outlook.com [104.47.32.58]) by lists.denx.de (Postfix) with ESMTPS id 9821DC21C29 for ; Wed, 4 Jul 2018 12:02:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector1-xilinx-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=e0mPI+KiQ5bp+KVgv2ZNHRnDYg9y5G7gQV+lHUXb10g=; b=r6+d9xU5y7PXo2MRp2QurVNlQzTI2v66VC3jwmL9zGtuMuH8LlrA6qHngPhGdKN3+WdFrUgWwHJYnBtV8IVAf21oSX2tYKMtJSVUekktFJvVXh5L77+NS2qZqRAc8jGx49NaOgFtlZkRZMKJehvcO9DsdVKR2kfoe+rh/7ghQR8= Received: from MWHPR0201CA0090.namprd02.prod.outlook.com (2603:10b6:301:75::31) by DM5PR0201MB3511.namprd02.prod.outlook.com (2603:10b6:4:77::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.906.25; Wed, 4 Jul 2018 12:02:03 +0000 Received: from SN1NAM02FT064.eop-nam02.prod.protection.outlook.com (2a01:111:f400:7e44::209) by MWHPR0201CA0090.outlook.office365.com (2603:10b6:301:75::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.930.18 via Frontend Transport; Wed, 4 Jul 2018 12:02:03 +0000 Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; openedev.com; dkim=none (message not signed) header.d=none;openedev.com; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.83 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.83; helo=xsj-pvapsmtpgw01; Received: from xsj-pvapsmtpgw01 (149.199.60.83) by SN1NAM02FT064.mail.protection.outlook.com (10.152.72.143) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.20.906.15 via Frontend Transport; Wed, 4 Jul 2018 12:02:02 +0000 Received: from unknown-38-66.xilinx.com ([149.199.38.66] helo=xsj-pvapsmtp01) by xsj-pvapsmtpgw01 with esmtp (Exim 4.63) (envelope-from ) id 1fagTy-0007wQ-30; Wed, 04 Jul 2018 05:02:02 -0700 Received: from [127.0.0.1] (helo=localhost) by xsj-pvapsmtp01 with smtp (Exim 4.63) (envelope-from ) id 1fagTs-0007fS-Us; Wed, 04 Jul 2018 05:01:56 -0700 Received: from xsj-pvapsmtp01 (smtp2.xilinx.com [149.199.38.66]) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id w64C1mSK013146; Wed, 4 Jul 2018 05:01:48 -0700 Received: from [172.23.37.99] (helo=xhdsivadur40.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1fagTj-0007b3-Rv; Wed, 04 Jul 2018 05:01:48 -0700 From: Siva Durga Prasad Paladugu To: Date: Wed, 4 Jul 2018 17:31:24 +0530 Message-ID: <1530705684-26826-2-git-send-email-siva.durga.paladugu@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1530705684-26826-1-git-send-email-siva.durga.paladugu@xilinx.com> References: <1530705684-26826-1-git-send-email-siva.durga.paladugu@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(39860400002)(376002)(396003)(346002)(136003)(2980300002)(438002)(199004)(189003)(186003)(478600001)(77096007)(26005)(305945005)(5660300001)(486006)(50226002)(51416003)(14444005)(336012)(126002)(36386004)(2616005)(446003)(106002)(54906003)(11346002)(426003)(76176011)(356003)(476003)(50466002)(8936002)(63266004)(16586007)(47776003)(36756003)(4326008)(6916009)(48376002)(9786002)(81156014)(316002)(7696005)(6666003)(8676002)(107886003)(2351001)(81166006)(2906002)(106466001)(107986001); DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR0201MB3511; H:xsj-pvapsmtpgw01; FPR:; SPF:Pass; LANG:en; PTR:unknown-60-83.xilinx.com; A:1; MX:1; X-Microsoft-Exchange-Diagnostics: 1; SN1NAM02FT064; 1:ajOjv7AKjIU+bgWAND46yjDdlKUkVL8AhGmsVtntYXV4ZU+2uMAjsXwdE9cpuEJTV8ZwEJDlKN9Cb0m4fsOyvwC4XG36yfi2x6XRrUOMbzgqcszDZXNoRaTcdV9GqHql MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6b6aba54-77e0-4f39-017e-08d5e1a5f445 X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989117)(4534165)(4627221)(201703031133081)(201702281549075)(8990107)(5600053)(711020)(4608076)(2017052603328)(7153060); SRVR:DM5PR0201MB3511; X-Microsoft-Exchange-Diagnostics: 1; DM5PR0201MB3511; 3:c8cuVIF9VzlwIDDz3As4o4jKnwLJUfDujAvsruYpVDkA1O4BRI9tB4h5uF5wL1RYkq23wAP57fHtJbIzKJjiLDGgNbwRxXV0Sx0UiT+V8Rkeoq6+nJQQf1qW89mzm+DPRhiwxxiAAkre54qNlEx8MHoJWdLW8DLUvYbMHHDAdI9RwSc4CbT63cb3kYP1T52JXfjw+DUS5E8DC1VcAUdm5WxM/aNQi22oXLHwm4me9QWcgR91k1EvblGJ5wjUQuvOz0tqeqMhBzxirytsOIufraLcHfikbksAIKt/0rTOsX1IFEcBUHxp/I6ppaIgyM0P+9O42AC02f1VOdR9mpHWCS5j3iEunYV96uy0ZEyqByQ=; 25:mCrBU2xHdb/6FtEtF1kSqybdIpEh/9xq6VMthaoOoBNUPAGVXKGVJSV+o3GVJBQkI0uIwRVZUFEoRm51EIwY/z7zGjdE1QJQcTMKGNfvEMPql8P2v1hqoV4M+48nLoQT+lwUDCfTWlu5zapM5Eri4CHQNBmo897AKEE6ohvbmGrYqEBb01OUstzwRp+aCn3wGwXcTzG3MJuuPNjyuaImuwNwyJ0oMjCeNKO2jz2gY57YV7fFfobRVdAGsLZdX1Pz4C44iwEG0AJpLS7TS/TSlcHEoRhajBYOkDH7OnjHzytF9op/sI92Ynso8fh8AjQIQ3mUD27rAihxnxkc2CY4LA== X-MS-TrafficTypeDiagnostic: DM5PR0201MB3511: X-Microsoft-Exchange-Diagnostics: 1; DM5PR0201MB3511; 31:vPEw74ELZ3Oq0Ja0oS0UKDH0GtkewlkGsTscsPPVSzridxZxPzq+jBhYkvtmrDUXPnQj1C0J0jAgqsY05AAvGcbtMrGEEyHWPruUNtwkonTrFYA7fis5a3ejVRcirsT3wPeqJSMeI5OQhXmR7zC3xLIwe5QbQcigp5zk4zYQ7Wtf55uaDueNb5qfWApwlJCYPcwrFN19i4VNbT4NQ9gswlU7dtOCY90cq0/RIVrchrE=; 20:3eO6r4z3TPm9jerW0RzsP+GN/dD8Rbc8fLE/4R7hD+io22tROCPGtEktpDyv2NvlMnF0cIVNrXvGTiIAKQ92AHLZNzTEALjbX8JWfheHPoqFQWz8sBwzfLhVaFWKtPM7WUGetC+cidundx0xng2SFvawMp7q0ue8PqvwdQn0ofaDadvVTDrjx4pxsB0PIPHJDQDpcFrY0t4NucY4EVKjnP1goYJx/lkFmHRgSK4wR3yv0tohISNrll31W/fizUYSVu7IbEXbYEUO67f/V/IG0r6AL3vnbh4Zv+vz73MOeRFNJxX51Zd07I2D6c2/EBi5EzpE+n7PziZjWmXhymPLNWS2YY7bv0A2v2dlMhkA3xB15Cd2bRfWVTywgmMOF/IzKpX14+wJtnv1CHC2sTfjsz5DojFrux2xS8YEJx0o9KrTvf0MXkp2bOxbH6y1RVErPozD7xDQku7yu6BlZwPuGzCSF17uMbhQJ4pqJjZ37n7lvYaimobNACSXnDllsKtZ X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(192813158149592); X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(3002001)(3231254)(944501410)(52105095)(93006095)(93004095)(10201501046)(6055026)(149027)(150027)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123562045)(20161123558120)(20161123564045)(20161123560045)(6072148)(201708071742011)(7699016); SRVR:DM5PR0201MB3511; BCL:0; PCL:0; RULEID:; SRVR:DM5PR0201MB3511; X-Microsoft-Exchange-Diagnostics: 1; DM5PR0201MB3511; 4:OCcwZE7qYhme1/D6i02aMUR6EaXHk8AZAInOIXIBGTWShiD4ttqKcu1VG+n/HtUgYV/iiiQwPIm3plLgazZNPowYfcSvHRa7KWOwp8YCvAVSU30cAB2Ob0oH6XQJiuaud4uSkTEobCIc1M9Kn3ulVzJMsF6CecZdiaReD7PpMp/uwP16+c2bF4E1qHPkemfIIwv2t/wSZktGk/UoCHHh4psf7Fjh0p4L2UeXMV4iR1Ws+/l4Jt6A/G5jpOZ+h/mrg+sOwpsqeAdk82zCq2uLJrsGcc5KhZ/rJu1Jn8tJaK2aEyItGFN80elrrdtkG1JL X-Forefront-PRVS: 0723A02764 X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; DM5PR0201MB3511; 23:P4146Lx8PbAYocuSdg5Oa+QUdmPujwTIi0Bzoo8?= GpyIoGexZEi4M8/EdznPh0R3za77JFOFcoDokr3mjjaEVLdf28meq7z842iWqCWz9TvH9EkouEkct33KBB1oxv09u7Qm7QpVm+SCQng8vdgU00tyDu4y4n2LQlbtc2KPVH/2fxNQ52JV4F6imHJ7KjdvkIehz8mcagro2u3+6a7s+HaXLVJHOIEser6xd8K477HpgulkpbzzDrdY9wlP+CkE/Myiu+I21RJH/VMpfPcm4JL6TTjwGP53M927nUrcGucZgSsx2PXjKMxoec8sFN/kwxRA1vOQt+CNx15rTBA3ZJPW7cfiqM/0BWQTwmIkDLB6wamGjIvy2BOiWbpbckE3Ya05l9UQ/rc1+CKxsbE2zDEYG92D/Wa4FumGZxwk6WLyTIWB8cNRJlZvmeUuUCNz+wvsCn4yMr6lIncLk9Zos6y4ROosgJLhDBNr+2esVw1AhHmMJBGGX+taxj6sLhhHs0OPpqvHLMvaMIubgWzrnB2Zy1ipNJaTrMxYdvGPuh22ohaet889I58RwtAUCL3muiLFdfIDKtTf17bVfnPERAwDwp2evpXl4G3R+y6qHVDQlZMcvOjoufzmf7GKpxemy6hSPOM3ZqX/Y5TD25qzf73OVm9TF9TOz+I7uEUbQETkTOlggpDei9SejhuWnn3u60n4aqUhaCL3aDQzp8ucTZ7Hf6B2vIm/4wR4qSmL3YjVP4eyniUZm4VrN65scHXshAqhXCPL+Zs99j7emi1qof/12NythAJimnZilAMFaXpQMtFwanubTlN2hYShxXRdkMV+IgEHNJSTIcsD8iAyIGl76rW/7s73VcXTjULDSqFnJuGxWrSI3bqQe6B7d+yiLluteFCEqwZSXENmqNXcJNbRQ1YXyUdzsD5hiJa54GxHlGzLVIWzXGZaOnN/l737XAz+i93RWuJEkEuWgWHUbVBLMb0CWniTT6AVPeXBTTkswq9YYS9J09wOVByJiPlZmmdrS4I08f3rEUTBr5iCn71vq3IDrNm7nkiZ8175Pnwr4MowBTV7DgRxDN6zxJuetViPwczfFhVLefEWD1hrm63iXI0TV7Sq3MBxiWtlyhZ2vbfoSBdnX99JCESffbT18 X-Microsoft-Antispam-Message-Info: raVE0OQ2DMMzGnLjC98bQOPqux4H3DSuLZabuQK51NX/TwgsEhIF4tAfY/LUzD1gudHl+ldKPkihhTYtjYF1M67XvJDaoCeJyWLSwdGYAXjSph9DX945N0gVTq5BdmfQL+9uFeDyazv52lyTv6MqwrG6MdqLcLyJA7bcsvfUeHEFae1fFjARSaxDeRZX0GGtigAVDo12DazJ2qLdlEAbPyDUQ1ZYBuvIXzYhScrlgQQ0sdW+HW7hiOe1sLb9YO4x3CjtOOiTFGw6m9S0kObVhPerRN/iKFmiG6vxNR+PIzq0aDql02pLSBmBTcVwEj/rp5AGUPf4X8Nwx+ZnhfMFr1wPP2HdvJVTGhQl/Z4IQc4= X-Microsoft-Exchange-Diagnostics: 1; DM5PR0201MB3511; 6:soMRUXCy8zwiBz6NjRzQiHX9Nsvf49blTC71THA3/5UoKB5/m1J03FBYOBd8fARfPxqJUx3LO3G2Qnr7QMu2r1KMeeXBip4vrVUl/VwgjspXIArNCshJl9Aoi+8ob4tM7sgP/XGmrBDiZ0eKU6eZFQ8YCV3Yw9d9f4vBjkuwEugtzBNGF39lqg/ogO+BD/l2nzbcUc7z4WJMp3y1/Wquv+5d7447SLEmmbdyPOJssWd5jvqwSFJVD6gUBXM/wGpvLh2JiXU8w3Q0UbHeCm2W+aUU08feDi7QSg8VUaubYAlnlnY4T5tAkEJAQANXv4tBDf0S8xx2MwpcjwE5XFoaC7TUolgZfUuXORnpAt9Zfrf6A4C6zC9CUxTPnOfOk4NVa4iMu1v76hheXxtJoKmoHNQqAOKRxG+0BL5OMEy8BjWz5OIhPIxcyK+Wikr5/uRoj36/RKwCoFR9J32itJJY0w==; 5:wHvB7XJ+M9QN2SdFmcgcJePEaFzrvauCWL8XjRhFJ9BT80AtEgO4uJAQ3UwiYiaKPvMe1lNN+KgGnwV6Wf71gGeS2/HyHhOxdEz2C9rITy1RxRJp4/SQnRpEpcoyINgzH2Pj/bd0wkS6CTFmsBgdIZbeQ0RqN1WkLJkL5gO+sQ4=; 24:xJ+qOd8HtDTdMVtzI1KeQWsZSXbyKDtcTrLbWKgyxSFQ2/RG0igZjhOZ1XNdynUHOWU4/SUceJHTsqtB/ShN9RL50Q8CDCeSYRBQ/6ASrTI= SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-Microsoft-Exchange-Diagnostics: 1; DM5PR0201MB3511; 7:FAfQodOsZE2SH3xpslas20oKcGUGiGpwDlBY+ppf07dCLu5weeayvTNxa6qFwjqQnA6tdkeEDSZj/qnbcSm1UeIdHmb3fqwwC2r4SapKAb7VZCwzGXCOhIyojfGSzVqD3AY/82F+5dskET9FlRX8mLMAUMkxjwpUcL27IUnuHIt2Ia5umR5JrFO9HHy1YYfobYFPIJDUkebG8BGWPWQwernxbNBIhJlWXvqvpDplKuGitCRHiZ2D0g8Jx5138exs X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jul 2018 12:02:02.5090 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6b6aba54-77e0-4f39-017e-08d5e1a5f445 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR0201MB3511 Cc: jagan@openedev.com, michal.simek@xilinx.com Subject: [U-Boot] [PATCH v7 2/2] zynqmp: zcu102: Add qspi driver support for ZynqMP zcu102 boards X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch adds qspi driver support for all ZynqMP ZCU102 boards. Signed-off-by: Siva Durga Prasad Paladugu Acked-by: Michal Simek Reviewed-by: Jagan Teki --- Changes for v7: - Added "spi-flash" to compatible strings. Changes for v6: - None Changes for v5: - None Changes for v4: - None Changes for v3: - Changed as per latest changes in 1/2 Changes for v2: - Rebased on top of latest master and enabled qspi for all zcu102 boards. --- arch/arm/dts/zynqmp-zcu102-revA.dts | 2 +- configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 5 +++++ configs/xilinx_zynqmp_zcu102_revA_defconfig | 5 +++++ configs/xilinx_zynqmp_zcu102_revB_defconfig | 5 +++++ 4 files changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index ddc3fba..ac7035f 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -534,7 +534,7 @@ status = "okay"; is-dual = <1>; flash@0 { - compatible = "m25p80"; /* 32MB */ + compatible = "m25p80", "spi-flash"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig index 49a14d8..da53aa4 100644 --- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig +++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig @@ -36,6 +36,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SDRAM=y +CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y @@ -69,6 +70,7 @@ CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_MACRONIX=y @@ -90,6 +92,9 @@ CONFIG_DM_SCSI=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig b/configs/xilinx_zynqmp_zcu102_revA_defconfig index 05dad41..60e1269 100644 --- a/configs/xilinx_zynqmp_zcu102_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig @@ -35,6 +35,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SDRAM=y +CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y @@ -66,6 +67,7 @@ CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_MACRONIX=y @@ -87,6 +89,9 @@ CONFIG_DM_SCSI=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig index b3711b4..fa2804d 100644 --- a/configs/xilinx_zynqmp_zcu102_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig @@ -35,6 +35,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SDRAM=y +CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y @@ -66,6 +67,7 @@ CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_MACRONIX=y @@ -87,6 +89,9 @@ CONFIG_DM_SCSI=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y