From patchwork Wed Sep 27 07:34:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 818990 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="s9I2WE6c"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3y28rB0GR2z9sRg for ; Wed, 27 Sep 2017 17:40:42 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752330AbdI0HkZ (ORCPT ); Wed, 27 Sep 2017 03:40:25 -0400 Received: from mail-wr0-f195.google.com ([209.85.128.195]:35975 "EHLO mail-wr0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751922AbdI0Hgf (ORCPT ); Wed, 27 Sep 2017 03:36:35 -0400 Received: by mail-wr0-f195.google.com with SMTP id k10so509472wrk.3; Wed, 27 Sep 2017 00:36:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TCaq+L0ACn83URvot4Qh0PvleIfjU5dQTuprZW0mEnw=; b=s9I2WE6caM0BGuXRpWwABPA7/6KHeF2CZ+jsAxEJsW3Z39fSgtfljV9/haTuVosZ0h BMFK6z/KoWVEn2rPqtn/V6cJeuZ4rXT32n3mBYeV7JoRgV7cxxBR8d5Be2ReRG6kn8wN tkPJAYQVN1mYTk181N3LJUKh52eto2YZERXeqzleoCrD7gZeWEhgN2bwxRaMmJ0RHcYf IbvcoHcnffYhK+fVGikU2wjFitv9koUI60zzmMAbvkUssKmeiBHJX1a/vSY8z+otlZLx +4LUvSdDpZ8+wAov0gWrrqUGo2oAJov22RQKfVrIj740wuyDkVy85j7naRyKkMVbcpn9 engA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TCaq+L0ACn83URvot4Qh0PvleIfjU5dQTuprZW0mEnw=; b=VF9SABP6w8DrqyUpp5AFojqdhUUxpXzBw9Vm/lexG26gHbLJFvzqgWqF2p6r20CwP6 nKyY7Ls0SKANruX8NdE1QlY+wTE9X658wY0r+JmO9699MNoH3RZFLdkhAeMiiiOK7IX6 0n/r2KBhZvF/7keAb0+HYmGejoJsZ+kGEyAuCWpmuWivwmA90YwJjbBkyb5/7Rxf0QUj JG1bPnetVJ30wmvLJauwvxSgqJgyHCn5E5+ZFGgEGzfB67bZKaT3w+wy/x8J9BZKFilC bI2QuB5RgCSjopYJ3wLZE0h0P2MZueWUAoYEeasCszJvgrO8MmCNAClUHECPFf27EE/c p4+A== X-Gm-Message-State: AHPjjUjVebftyZE+bpsID1jmGlRUPLr4Kq5DmguTOIHZdbljLtr/qiCr rXczWBq2HvPvpePuncIuWeM= X-Google-Smtp-Source: AOwi7QCsG9EUrI9QUUo4WwymsnoPUypWNoaMSe3qguo6JWtBuh1sLH5oVl5wVMtHPv35DQaOXVLCzQ== X-Received: by 10.223.159.6 with SMTP id l6mr564203wrf.156.1506497793805; Wed, 27 Sep 2017 00:36:33 -0700 (PDT) Received: from Red.local (LFbn-MAR-1-580-96.w90-118.abo.wanadoo.fr. [90.118.159.96]) by smtp.googlemail.com with ESMTPSA id n9sm5660526wmd.12.2017.09.27.00.36.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 27 Sep 2017 00:36:33 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com, frowand.list@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Corentin Labbe Subject: [PATCH v6 01/11] dt-bindings: net: Restore sun8i dwmac binding Date: Wed, 27 Sep 2017 09:34:04 +0200 Message-Id: <20170927073414.17361-2-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170927073414.17361-1-clabbe.montjoie@gmail.com> References: <20170927073414.17361-1-clabbe.montjoie@gmail.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch restore dt-bindings documentation about dwmac-sun8i This reverts commit 8aa33ec2f481 ("dt-bindings: net: Revert sun8i dwmac binding") Signed-off-by: Corentin Labbe Acked-by: Rob Herring --- .../devicetree/bindings/net/dwmac-sun8i.txt | 84 ++++++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/dwmac-sun8i.txt diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt new file mode 100644 index 000000000000..725f3b187886 --- /dev/null +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt @@ -0,0 +1,84 @@ +* Allwinner sun8i GMAC ethernet controller + +This device is a platform glue layer for stmmac. +Please see stmmac.txt for the other unchanged properties. + +Required properties: +- compatible: should be one of the following string: + "allwinner,sun8i-a83t-emac" + "allwinner,sun8i-h3-emac" + "allwinner,sun8i-v3s-emac" + "allwinner,sun50i-a64-emac" +- reg: address and length of the register for the device. +- interrupts: interrupt for the device +- interrupt-names: should be "macirq" +- clocks: A phandle to the reference clock for this device +- clock-names: should be "stmmaceth" +- resets: A phandle to the reset control for this device +- reset-names: should be "stmmaceth" +- phy-mode: See ethernet.txt +- phy-handle: See ethernet.txt +- #address-cells: shall be 1 +- #size-cells: shall be 0 +- syscon: A phandle to the syscon of the SoC with one of the following + compatible string: + - allwinner,sun8i-h3-system-controller + - allwinner,sun8i-v3s-system-controller + - allwinner,sun50i-a64-system-controller + - allwinner,sun8i-a83t-system-controller + +Optional properties: +- allwinner,tx-delay-ps: TX clock delay chain value in ps. Range value is 0-700. Default is 0) +- allwinner,rx-delay-ps: RX clock delay chain value in ps. Range value is 0-3100. Default is 0) +Both delay properties need to be a multiple of 100. They control the delay for +external PHY. + +Optional properties for the following compatibles: + - "allwinner,sun8i-h3-emac", + - "allwinner,sun8i-v3s-emac": +- allwinner,leds-active-low: EPHY LEDs are active low + +Required child node of emac: +- mdio bus node: should be named mdio + +Required properties of the mdio node: +- #address-cells: shall be 1 +- #size-cells: shall be 0 + +The device node referenced by "phy" or "phy-handle" should be a child node +of the mdio node. See phy.txt for the generic PHY bindings. + +Required properties of the phy node with the following compatibles: + - "allwinner,sun8i-h3-emac", + - "allwinner,sun8i-v3s-emac": +- clocks: a phandle to the reference clock for the EPHY +- resets: a phandle to the reset control for the EPHY + +Example: + +emac: ethernet@1c0b000 { + compatible = "allwinner,sun8i-h3-emac"; + syscon = <&syscon>; + reg = <0x01c0b000 0x104>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + int_mii_phy: ethernet-phy@1 { + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + }; + }; +}; From patchwork Wed Sep 27 07:34:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 818984 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="r2K1lJHP"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3y28pW0Wgvz9t4b for ; Wed, 27 Sep 2017 17:39:15 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752335AbdI0Hi6 (ORCPT ); Wed, 27 Sep 2017 03:38:58 -0400 Received: from mail-wr0-f193.google.com ([209.85.128.193]:38901 "EHLO mail-wr0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751797AbdI0Hgk (ORCPT ); Wed, 27 Sep 2017 03:36:40 -0400 Received: by mail-wr0-f193.google.com with SMTP id p37so3667399wrb.5; Wed, 27 Sep 2017 00:36:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=32R5TgMDZYCR9hvyqW2q/ceSSSJ6voqy3f/ojhl7Mu4=; b=r2K1lJHPgJxZmkrEIyVfdD0CX6a3zli3Y+hFzdCJvL4AvVB/uxgf1q0acfX44MlS3g 6lCh2g00Vo2cGhdwzrFrvCK72EQAVEH5FYOq2BdUMczTwtUsIWxiW+QUj5NwO9LmFrxY L9Y/l8h6QI+SOk9vHlN3duw6sN/peoPTg6BH1L9xAA8bkPfp0gAZQGm9+n1Dx4XvAqB9 ILX3gQtS/Xk6Vvzd7sEASAI3L/D33D+WafSO6SEftMOc7eiQ00Mwjwl1xMAAPvA1enLl FkS5yUPY2RJm7OZQFmh7/TTpDFywunRbKHLdkX4d9McLc4QLhYOzyj2xXtO9Cd+d6SqE 5j/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=32R5TgMDZYCR9hvyqW2q/ceSSSJ6voqy3f/ojhl7Mu4=; b=SRu7oi96hrpYexY9Vq3K/pO76qjdt3MYwEcceKmTm3h7mrRxXA+jqbXUjDZfZZ1sX2 XF3wKCQ/aulrOIks1T3TqKRctSgm7sMMlJ4gqon+WvHev1uTFnJzfKRWnEHgZO6YHFEz 3P/HHDcRkLaj8087qqaUsJMy3BgKzRkBKk1h1PnymU5c+0iMsg9St3ELadi5NL0+eLi7 vs5/R1omSTMGGw59yIEGtWXpgqiBQKLmJ0PQm/6ANUT4D00JWtGp8wPuxEiJAF3vHulX Onw4BohnSUJLk06ongNuJCBBOxdM191fRCDXQd8c8jEcMPN5f/9j5Loy1O+tEICHc30/ 9Wpg== X-Gm-Message-State: AHPjjUiUs3Yfo/97P68sArtQE0Nuj8j2W89Q6E+W9JJ9nNTXt9xx+w2F 2E5OxTnxe3Iv7WKPIAh0z6Y= X-Google-Smtp-Source: AOwi7QCqIEwkvnXqe/ldfz+9v//c0DIl86m5v4pS5NeeVgqK+0dbxib1sbRSFOHUhi9ETXhGl0EwBw== X-Received: by 10.223.176.98 with SMTP id g31mr500107wra.117.1506497798742; Wed, 27 Sep 2017 00:36:38 -0700 (PDT) Received: from Red.local (LFbn-MAR-1-580-96.w90-118.abo.wanadoo.fr. [90.118.159.96]) by smtp.googlemail.com with ESMTPSA id n9sm5660526wmd.12.2017.09.27.00.36.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 27 Sep 2017 00:36:38 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com, frowand.list@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Corentin Labbe Subject: [PATCH v6 05/11] dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY Date: Wed, 27 Sep 2017 09:34:08 +0200 Message-Id: <20170927073414.17361-6-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170927073414.17361-1-clabbe.montjoie@gmail.com> References: <20170927073414.17361-1-clabbe.montjoie@gmail.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch add documentation about the MDIO switch used on sun8i-h3-emac for integrated PHY. Signed-off-by: Corentin Labbe --- .../devicetree/bindings/net/dwmac-sun8i.txt | 138 +++++++++++++++++++-- 1 file changed, 126 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt index 725f3b187886..e2ef4683df08 100644 --- a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt @@ -4,18 +4,18 @@ This device is a platform glue layer for stmmac. Please see stmmac.txt for the other unchanged properties. Required properties: -- compatible: should be one of the following string: +- compatible: must be one of the following string: "allwinner,sun8i-a83t-emac" "allwinner,sun8i-h3-emac" "allwinner,sun8i-v3s-emac" "allwinner,sun50i-a64-emac" - reg: address and length of the register for the device. - interrupts: interrupt for the device -- interrupt-names: should be "macirq" +- interrupt-names: must be "macirq" - clocks: A phandle to the reference clock for this device -- clock-names: should be "stmmaceth" +- clock-names: must be "stmmaceth" - resets: A phandle to the reset control for this device -- reset-names: should be "stmmaceth" +- reset-names: must be "stmmaceth" - phy-mode: See ethernet.txt - phy-handle: See ethernet.txt - #address-cells: shall be 1 @@ -39,23 +39,38 @@ Optional properties for the following compatibles: - allwinner,leds-active-low: EPHY LEDs are active low Required child node of emac: -- mdio bus node: should be named mdio +- mdio bus node: with compatible "snps,dwmac-mdio" Required properties of the mdio node: - #address-cells: shall be 1 - #size-cells: shall be 0 -The device node referenced by "phy" or "phy-handle" should be a child node +The device node referenced by "phy" or "phy-handle" must be a child node of the mdio node. See phy.txt for the generic PHY bindings. -Required properties of the phy node with the following compatibles: +The following compatibles require that the mdio node have a mdio-mux child +node called "mdio-mux": + - "allwinner,sun8i-h3-emac" + - "allwinner,sun8i-v3s-emac": +Required properties for the mdio-mux node: + - compatible = "mdio-mux" + - one child mdio for the integrated mdio + - one child mdio for the external mdio if present (V3s have none) +Required properties for the mdio-mux children node: + - reg: 1 for internal MDIO bus, 2 for external MDIO bus + +The following compatibles require a PHY node representing the integrated +PHY, under the integrated MDIO bus node if an mdio-mux node is used: - "allwinner,sun8i-h3-emac", - "allwinner,sun8i-v3s-emac": + +Required properties of the integrated phy node: - clocks: a phandle to the reference clock for the EPHY - resets: a phandle to the reset control for the EPHY +- phy-is-integrated +- Must be a child of the integrated mdio -Example: - +Example with integrated PHY: emac: ethernet@1c0b000 { compatible = "allwinner,sun8i-h3-emac"; syscon = <&syscon>; @@ -72,13 +87,112 @@ emac: ethernet@1c0b000 { phy-handle = <&int_mii_phy>; phy-mode = "mii"; allwinner,leds-active-low; + + mdio0: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + mdio-mux { + compatible = "mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + + int_mdio: mdio@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + int_mii_phy: ethernet-phy@1 { + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + phy-is-integrated; + }; + }; + ext_mdio: mdio@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; +}; + +Example with external PHY: +emac: ethernet@1c0b000 { + compatible = "allwinner,sun8i-h3-emac"; + syscon = <&syscon>; + reg = <0x01c0b000 0x104>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + allwinner,leds-active-low; + + mdio0: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + mdio-mux { + compatible = "mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + + int_mdio: mdio@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + int_mii_phy: ethernet-phy@1 { + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + phy-is-integrated; + }; + }; + ext_mdio: mdio@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + ext_rgmii_phy: ethernet-phy@1 { + reg = <1>; + }; + }: + }; + }; +}; + +Example with SoC without integrated PHY + +emac: ethernet@1c0b000 { + compatible = "allwinner,sun8i-a83t-emac"; + syscon = <&syscon>; + reg = <0x01c0b000 0x104>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + mdio: mdio { + compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; - int_mii_phy: ethernet-phy@1 { + ext_rgmii_phy: ethernet-phy@1 { reg = <1>; - clocks = <&ccu CLK_BUS_EPHY>; - resets = <&ccu RST_BUS_EPHY>; }; }; };