From patchwork Fri Jun 22 23:20:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 933626 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="GmCwYfh0"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41CF1t0qDXz9s3R for ; Sat, 23 Jun 2018 09:21:22 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754753AbeFVXVT (ORCPT ); Fri, 22 Jun 2018 19:21:19 -0400 Received: from mail-pl0-f66.google.com ([209.85.160.66]:33367 "EHLO mail-pl0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754552AbeFVXVR (ORCPT ); Fri, 22 Jun 2018 19:21:17 -0400 Received: by mail-pl0-f66.google.com with SMTP id 6-v6so4147821plb.0 for ; Fri, 22 Jun 2018 16:21:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=subject:date:message-id:in-reply-to:references:cc:from:to; bh=RmVnwqJu4yqdbEAPb8IWT5L/4G0BYyAhUPrkzFcI3ys=; b=GmCwYfh0eVRzgaNtdjZsY66NFfKR2UPs2IpxOB7qTnaWi35UJxh2+MIjsVq+WPjyAY KmXVgskby6PfeSBOBmBTrxMLTjOWguA9WlAlW0AjuPX/iR7k8WnMDVpnPTXABqVAz/9o H8eea+ydJ1Yxw5ppb6hpkc/OyqiyESr1l66RDv7q0HTEZixmXc6/cCBWIZFWFy8W/W+l 7jVW/MCxJp74pOjER7ILcc82pSW5+en6kqfmI2SbblXloWVphEOz92fZIAxWd71cm92H NfgUcmxMtICB3diBU/JLoSwtSApE/fy+TN1w+fxyGNpWR87HTBrpNREvsQEaigWZKERA gtpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :cc:from:to; bh=RmVnwqJu4yqdbEAPb8IWT5L/4G0BYyAhUPrkzFcI3ys=; b=J0uBfHXZ73hZ51/Q2qp2vvD7EXIjM/GfVl8szZZmPRi/x01UQUk5KBPEQfGUKS6j4x rvOxZpDE1AeD95ujcjIRfqB7WnFJOobz2h7VOYw4c5Eh98vYumb8dMk/59yt0TcUbGGc 2YTIFcDLW68mUgFXBAnIRBKspKgjE6yaMORdO7IG0uF1m3kUqna5t1V+BLptuPDR2oCw lKgqoDjFLzZqLev8y9cIKhl0iMIYC6/FSjyqhgNklaIL0upoki1PY7WSGChyaorOnG8e 35Xys30kyuknAlKK68LCEFrOBBKxi39f9mMNr1Va0+Ci4qsSd+ASF7YfelBLXDhLP7UV Xw3g== X-Gm-Message-State: APt69E0L6ZZ2gWpsZSHdo3/tmJrbzJXBLOFqaTpLenBeqvqAqwF36BAQ r5hbB3gSDHKxqgSVN0we34Mjfg== X-Google-Smtp-Source: ADUXVKLKpbmMdKSI17oTGeZGy/uo1vvmZq3FNSDXO9XDVjhfGlnQHpqo6QCqEHUQBPW3KgsurU1jKg== X-Received: by 2002:a17:902:b949:: with SMTP id h9-v6mr3448353pls.321.1529709676187; Fri, 22 Jun 2018 16:21:16 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id d23-v6sm22104635pfe.2.2018.06.22.16.21.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 22 Jun 2018 16:21:15 -0700 (PDT) Subject: [PATCH 2/3] dt-bindings: interrupt-controller: RISC-V local interrupt controller docs Date: Fri, 22 Jun 2018 16:20:05 -0700 Message-Id: <20180622232006.12158-3-palmer@sifive.com> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20180622232006.12158-1-palmer@sifive.com> References: <20180622232006.12158-1-palmer@sifive.com> Cc: Palmer Dabbelt , aou@eecs.berkeley.edu, shorne@gmail.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Palmer Dabbelt From: Palmer Dabbelt To: tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, robh+dt@kernel.org, mark.rutland@arm.com Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Palmer Dabbelt This patch adds documentation on the RISC-V local interrupt controller, which is a per-hart interrupt controller that manages all interrupts entering a RISC-V hart. This interrupt controller is present on all RISC-V systems. Signed-off-by: Palmer Dabbelt --- .../interrupt-controller/riscv,cpu-intc.txt | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt new file mode 100644 index 000000000000..61900e2e3868 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt @@ -0,0 +1,41 @@ +RISC-V Hart-Level Interrupt Controller (HLIC) +--------------------------------------------- + +RISC-V cores include Control Status Registers (CSRs) which are local to each +hart and can be read or written by software. Some of these CSRs are used to +control local interrupts connected to the core. Every interrupt is ultimately +routed through a hart's HLIC before it interrupts that hart. + +The RISC-V supervisor ISA manual specifies three interrupt sources that are +attached to every HLIC: software interrupts, the timer interrupt, and external +interrupts. Software interrupts are used to send IPIs between cores. The +timer interrupt comes from an architecturally mandated real-time timer that is +controller via SBI calls and CSR reads. External interrupts connect all other +device interrupts to the HLIC, which are routed via the platform-level +interrupt controller (PLIC). + +All RISC-V systems that conform to the supervisor ISA specification are +required to have a HLIC with these three interrupt sources present. Since the +interrupt map is defined by the ISA it's not listed in the HLIC's device tree +entry, though external interrupt controllers (like the PLIC, for example) will +need to define how their interrupts map to the relevant HLICs. + +Required properties: +- compatible : "riscv,cpu-intc" +- #interrupt-cells : should be <1> +- interrupt-controller : Identifies the node as an interrupt controller + +Furthermore, this interrupt-controller MUST be embedded inside the cpu +definition of the hart whose CSRs control these local interrupts. + +An example device tree entry for a HLIC is show below. + + cpu1: cpu@1 { + compatible = "riscv"; + ... + cpu1-intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + };