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[176.162.151.233]) by smtp.gmail.com with ESMTPSA id r10-v6sm1075345wrm.66.2018.06.04.03.01.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 Jun 2018 03:01:00 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Colin Didier , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Daniel Lezcano , Thomas Gleixner , Fabio Estevam , Vladimir Zapolskiy , Sascha Hauer , Rob Herring , NXP Linux Team , Pengutronix Kernel Team , =?utf-8?q?Cl=C3=A9ment_Peron?= Subject: [PATCH v5 2/4] dt-bindings: timer: add i.MX EPIT timer binding Date: Mon, 4 Jun 2018 12:00:33 +0200 Message-Id: <20180604100035.19558-3-peron.clem@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180604100035.19558-1-peron.clem@gmail.com> References: <20180604100035.19558-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Clément Peron Add devicetree binding document for NXP's i.MX SoC specific EPIT timer driver. Signed-off-by: Clément Peron --- .../devicetree/bindings/timer/fsl,imxepit.txt | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/fsl,imxepit.txt diff --git a/Documentation/devicetree/bindings/timer/fsl,imxepit.txt b/Documentation/devicetree/bindings/timer/fsl,imxepit.txt new file mode 100644 index 000000000000..de2e6ef68d24 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/fsl,imxepit.txt @@ -0,0 +1,21 @@ +Binding for the i.MX Enhanced Periodic Interrupt Timer (EPIT) + +The Enhanced Periodic Interrupt Timer (EPIT) is a 32-bit set-and-forget timer +that is capable of providing precise interrupts at regular intervals with +minimal processor intervention. + +Required properties: +- compatible: should be "fsl,-epit", "fsl,imx31-epit" where is + imx25, imx6qdl, imx6sl, imx6sul or imx6sx. +- reg: physical base address of the controller and length of memory mapped + region. +- interrupts: Should contain EPIT controller interrupt +- clocks : The clock provided by the SoC to drive the timer. + +Example for i.MX6QDL: + epit1: epit@20d0000 { + compatible = "fsl,imx6qdl-epit", "fsl,imx31-epit"; + reg = <0x020d0000 0x4000>; + interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_EPIT1>; + };