From patchwork Sat May 12 10:15:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramon Fried X-Patchwork-Id: 912403 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="vTacLfq9"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 40jjZl2V0Fz9rxs for ; Sat, 12 May 2018 20:17:51 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id E215CC220CF; Sat, 12 May 2018 10:16:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 69034C22404; Sat, 12 May 2018 10:16:33 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 67005C223EB; Sat, 12 May 2018 10:16:27 +0000 (UTC) Received: from mail-wr0-f195.google.com (mail-wr0-f195.google.com [209.85.128.195]) by lists.denx.de (Postfix) with ESMTPS id 16605C223C4 for ; Sat, 12 May 2018 10:16:23 +0000 (UTC) Received: by mail-wr0-f195.google.com with SMTP id o4-v6so7586155wrm.0 for ; Sat, 12 May 2018 03:16:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=L1zgBqCAT01f9o3KawNLBxT8/c91p05pE6jOH1z1bEs=; b=vTacLfq9deczrnXOZOH+EJP0/hhGKUKxVG9OgXKnPTbperoRf2VPL73x8XY2ngq3EH ucrxRd/a/aBw9yXeStx2is/dHjxznDn+Vbx3kZsEoFPCbIMp7RBzyaHFsMeN5Ldv6AaP xTgBoh8vkz5ROAkvVujQ+bkx4pKje5ASpAnZ0TJ7+Q8jE6kmBSbIBWEY4VgDG9hmY5B9 xDVUSXPx99CFMuoxYkVWYvUnLT8/SwBlkb5zNkOJa72OE7vfa1RvPbmpeOgTLAaSxSmO cGFW4ch+zYLt3RCv2EVu4+la0fc7R6QWNPyzQRhOTPFIOsZtJsXx3ntZHud+EiJd9+Bh BEcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=L1zgBqCAT01f9o3KawNLBxT8/c91p05pE6jOH1z1bEs=; b=BMox+Bzt3XA6e3/AuzpUzP1Oyc2XIU4qgA4FPQVsic8mWsjLJJ5Fp6QOgBVwjno+4N 9wJO6C1ZwCrN6vSuGFKC4TQOf3M3jHufL038s5hakNOF1cr1c3yO4K2DYJereyCtBrRP 5/NNKyXXIwBZXwbv6AsyrF1YvQcYTXzkHjB63sQml8KJ/5tIAb2OF82Twn2ZRTNY9sV7 iqHeKzt3RlLoaJSAvLxJTpmZvsOEUopvpK5vO3scicVdEDPuDnwJkdAyztwJIUPheXpY 7lV6Kt8EghPHBSiSKPlNnAxn1UigkDDadatRj7OxIP2Tn0g88r/nCHnvLDNkZaBbMH76 aIMA== X-Gm-Message-State: ALKqPwcDcmq801y2SfR6R4kev/isgytfg+ZdYfX6AW9QceRp+H3x2XYv 9+VjFIlEgbKQduwdU8RLbAM= X-Google-Smtp-Source: AB8JxZrQU3uce9SS6VxqSPFHIs5hVZRzko305Z0FfHDE5oWLrDzIM+V8X9nqMHzevkhNAqHJW4x13Q== X-Received: by 2002:adf:b8b0:: with SMTP id i45-v6mr1682114wrf.105.1526120182742; Sat, 12 May 2018 03:16:22 -0700 (PDT) Received: from localhost.localdomain ([141.226.166.38]) by smtp.gmail.com with ESMTPSA id h67-v6sm2881280wmg.41.2018.05.12.03.16.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 12 May 2018 03:16:22 -0700 (PDT) From: Ramon Fried To: albert.u.boot@aribaud.net, mateusz.kulikowski@gmail.com, jramirez@baylibre.com, robdclark@gmail.com, sjg@chromium.org Date: Sat, 12 May 2018 13:15:52 +0300 Message-Id: <20180512101558.24375-2-ramon.fried@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180512101558.24375-1-ramon.fried@gmail.com> References: <20180512101558.24375-1-ramon.fried@gmail.com> Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 1/7] db820c: set clk node to be probed before relocation X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The clock and serial nodes are needed before relocation. This patch ensures that the msm-serial driver will probe and provide uart output before relocation. Signed-off-by: Ramon Fried --- arch/arm/dts/dragonboard820c-uboot.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/dts/dragonboard820c-uboot.dtsi b/arch/arm/dts/dragonboard820c-uboot.dtsi index 88312b3fa1..81df788fca 100644 --- a/arch/arm/dts/dragonboard820c-uboot.dtsi +++ b/arch/arm/dts/dragonboard820c-uboot.dtsi @@ -5,6 +5,20 @@ * (C) Copyright 2017 Jorge Ramirez-Ortiz */ +/ { + soc { + u-boot,dm-pre-reloc; + + clock-controller@300000 { + u-boot,dm-pre-reloc; + }; + + serial@75b0000 { + u-boot,dm-pre-reloc; + }; + }; +}; + &pm8994_pon { key_vol_down { gpios = <&pm8994_pon 1 0>; From patchwork Sat May 12 10:15:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramon Fried X-Patchwork-Id: 912406 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; 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This patch ensures that we don't touch these registers if clock setting failed. Signed-off-by: Ramon Fried --- drivers/serial/serial_msm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c index 119e6b9846..250e48c996 100644 --- a/drivers/serial/serial_msm.c +++ b/drivers/serial/serial_msm.c @@ -183,8 +183,8 @@ static int msm_serial_probe(struct udevice *dev) { struct msm_serial_data *priv = dev_get_priv(dev); - msm_uart_clk_init(dev); /* Ignore return value and hope clock was - properly initialized by earlier loaders */ + if (msm_uart_clk_init(dev)) + return -EINVAL; if (readl(priv->base + UARTDM_SR) & UARTDM_SR_UART_OVERRUN) writel(UARTDM_CR_CMD_RESET_ERR, priv->base + UARTDM_CR); From patchwork Sat May 12 10:15:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramon Fried X-Patchwork-Id: 912404 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Sat, 12 May 2018 03:16:24 -0700 (PDT) From: Ramon Fried To: albert.u.boot@aribaud.net, mateusz.kulikowski@gmail.com, jramirez@baylibre.com, robdclark@gmail.com, sjg@chromium.org Date: Sat, 12 May 2018 13:15:54 +0300 Message-Id: <20180512101558.24375-4-ramon.fried@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180512101558.24375-1-ramon.fried@gmail.com> References: <20180512101558.24375-1-ramon.fried@gmail.com> Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 3/7] serial: serial_msm: initialize uart only before relocation X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The uart is already initialized prior to relocation, reinitialization after relocation is unnecessary. Signed-off-by: Ramon Fried Reviewed-by: Simon Glass --- drivers/serial/serial_msm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c index 250e48c996..22301c0e37 100644 --- a/drivers/serial/serial_msm.c +++ b/drivers/serial/serial_msm.c @@ -183,6 +183,10 @@ static int msm_serial_probe(struct udevice *dev) { struct msm_serial_data *priv = dev_get_priv(dev); + /* No need to reinitialize the UART after relocation */ + if ((gd->flags & GD_FLG_RELOC)) + return 0; + if (msm_uart_clk_init(dev)) return -EINVAL; From patchwork Sat May 12 10:15:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramon Fried X-Patchwork-Id: 912405 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ijacQrw/"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 40jjc9556bz9rxs for ; Sat, 12 May 2018 20:19:05 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 58ECFC223CB; Sat, 12 May 2018 10:17:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 3E0CCC223CC; Sat, 12 May 2018 10:16:43 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id BD19DC223CB; Sat, 12 May 2018 10:16:31 +0000 (UTC) Received: from mail-wm0-f66.google.com (mail-wm0-f66.google.com [74.125.82.66]) by lists.denx.de (Postfix) with ESMTPS id 794CCC2242A for ; Sat, 12 May 2018 10:16:27 +0000 (UTC) Received: by mail-wm0-f66.google.com with SMTP id j4-v6so6154660wme.1 for ; Sat, 12 May 2018 03:16:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nLw82uSgpesM4w1jaYHSAsISYl2RnhcygXVQJz5cJsg=; b=ijacQrw/hyTptlvY9PYn/EMUDcIYe67FQ+f5FMapq8yRT1QFGlhiOSsxrsP77LIQkq dO3rJPTOyqjOCB7GQLoRHwtZovIaXeEt/im2JzJxjvIM/kv+HDkG4ijgApxWOKPfH2nY 6MYaA5txs5I1bhZncGJuJYtei8oelKpuAmhRgd7A4g2V3tU8/UovU7kbkFhFm1fqw0N0 t00zJPh+jJW8DBpBubm8fFpHYRiEDC/RYc5u98X9S3HROw/DMCEwnmSRKoQ3GP3P26VX dEhBn4K0qrbAuPm2RHBId9GCP4d4JGOG8IABQKEc8GRGaYMFDaOLJCKYy4abCV3j6wtu dkIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nLw82uSgpesM4w1jaYHSAsISYl2RnhcygXVQJz5cJsg=; b=exiUrwUfne5n4glNHY1eYy5As2N6ZGONqDwKbTsUBw6igz9de9zDH3ajRoALUqHyl9 8ggw6AJF6DALa6CWRPcdKhM9IaWv2YqhmjNAu8MeMnbrfxEO3rknB3HODWZbIjVy0Hpj Q8wy7kwpXAjXry71dq/GWU6+bfS1fE2owlOCk1/G/lmTKEXaJNpmNjwIfMFSwgoJLSXs 8y7/lW6d88fGrT1HXIziIqhMvXfQU3OtHDB2Z4E5l+G1dvERPjsW1fMelrD6aazA4xlF V8S31bYEP5N97DJu8Idn6/6pV3G2HMCSegN4ORH/YY2jKsOQ9xXahlj53kuveKgJVStp 6Erw== X-Gm-Message-State: ALKqPweR+B9yVNCZ9zl6iZyOdKvPG5ZJHypNrazGXE0aP/GT7k9CFrIX vJC60UUaVTI9eZ9on73aLMw= X-Google-Smtp-Source: AB8JxZoxxMwHKXfXPVAy1nD9uXtTCCU1M1jHzMdkQbdiYEC9hJX84kxIqxlIn0IELxnBWelw1MyFrQ== X-Received: by 2002:a1c:8d90:: with SMTP id p138-v6mr1038930wmd.153.1526120187025; Sat, 12 May 2018 03:16:27 -0700 (PDT) Received: from localhost.localdomain ([141.226.166.38]) by smtp.gmail.com with ESMTPSA id h67-v6sm2881280wmg.41.2018.05.12.03.16.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 12 May 2018 03:16:26 -0700 (PDT) From: Ramon Fried To: albert.u.boot@aribaud.net, mateusz.kulikowski@gmail.com, jramirez@baylibre.com, robdclark@gmail.com, sjg@chromium.org Date: Sat, 12 May 2018 13:15:55 +0300 Message-Id: <20180512101558.24375-5-ramon.fried@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180512101558.24375-1-ramon.fried@gmail.com> References: <20180512101558.24375-1-ramon.fried@gmail.com> Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 4/7] mach-snapdragon: Fix UART clock flow X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" UART clock enabling flow was wrong. Changed the flow according to downstream implementation in LK. Signed-off-by: Ramon Fried --- arch/arm/mach-snapdragon/clock-apq8016.c | 23 +++++++++++++++------- arch/arm/mach-snapdragon/clock-apq8096.c | 4 ++-- arch/arm/mach-snapdragon/clock-snapdragon.c | 17 +++++++++++++++- arch/arm/mach-snapdragon/clock-snapdragon.h | 9 +++++++-- .../mach-snapdragon/include/mach/sysmap-apq8016.h | 1 + 5 files changed, 42 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-snapdragon/clock-apq8016.c b/arch/arm/mach-snapdragon/clock-apq8016.c index 9c0cc1c22c..6e4a0ccb90 100644 --- a/arch/arm/mach-snapdragon/clock-apq8016.c +++ b/arch/arm/mach-snapdragon/clock-apq8016.c @@ -17,7 +17,6 @@ /* GPLL0 clock control registers */ #define GPLL0_STATUS_ACTIVE BIT(17) -#define APCS_GPLL_ENA_VOTE_GPLL0 BIT(0) static const struct bcr_regs sdc_regs[] = { { @@ -36,11 +35,17 @@ static const struct bcr_regs sdc_regs[] = { } }; -static struct gpll0_ctrl gpll0_ctrl = { +static struct pll_vote_clk gpll0_vote_clk = { .status = GPLL0_STATUS, .status_bit = GPLL0_STATUS_ACTIVE, .ena_vote = APCS_GPLL_ENA_VOTE, - .vote_bit = APCS_GPLL_ENA_VOTE_GPLL0, + .vote_bit = BIT(0), +}; + +static struct vote_clk gcc_blsp1_ahb_clk = { + .cbcr_reg = BLSP1_AHB_CBCR, + .ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE, + .vote_bit = BIT(10), }; /* SDHCI */ @@ -55,7 +60,7 @@ static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate) /* 800Mhz/div, gpll0 */ clk_rcg_set_rate_mnd(priv->base, &sdc_regs[slot], div, 0, 0, CFG_CLK_SRC_GPLL0); - clk_enable_gpll0(priv->base, &gpll0_ctrl); + clk_enable_gpll0(priv->base, &gpll0_vote_clk); clk_enable_cbc(priv->base + SDCC_APPS_CBCR(slot)); return rate; @@ -72,12 +77,16 @@ static const struct bcr_regs uart2_regs = { /* UART: 115200 */ static int clk_init_uart(struct msm_clk_priv *priv) { - /* Enable iface clk */ - clk_enable_cbc(priv->base + BLSP1_AHB_CBCR); + /* Enable AHB clock */ + clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk); + /* 7372800 uart block clock @ GPLL0 */ clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 144, 15625, CFG_CLK_SRC_GPLL0); - clk_enable_gpll0(priv->base, &gpll0_ctrl); + + /* Vote for gpll0 clock */ + clk_enable_gpll0(priv->base, &gpll0_vote_clk); + /* Enable core clk */ clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR); diff --git a/arch/arm/mach-snapdragon/clock-apq8096.c b/arch/arm/mach-snapdragon/clock-apq8096.c index 008649a4c6..628c38785b 100644 --- a/arch/arm/mach-snapdragon/clock-apq8096.c +++ b/arch/arm/mach-snapdragon/clock-apq8096.c @@ -27,7 +27,7 @@ static const struct bcr_regs sdc_regs = { .D = SDCC2_D, }; -static const struct gpll0_ctrl gpll0_ctrl = { +static const struct pll_vote_clk gpll0_vote_clk = { .status = GPLL0_STATUS, .status_bit = GPLL0_STATUS_ACTIVE, .ena_vote = APCS_GPLL_ENA_VOTE, @@ -41,7 +41,7 @@ static int clk_init_sdc(struct msm_clk_priv *priv, uint rate) clk_enable_cbc(priv->base + SDCC2_AHB_CBCR); clk_rcg_set_rate_mnd(priv->base, &sdc_regs, div, 0, 0, CFG_CLK_SRC_GPLL0); - clk_enable_gpll0(priv->base, &gpll0_ctrl); + clk_enable_gpll0(priv->base, &gpll0_vote_clk); clk_enable_cbc(priv->base + SDCC2_APPS_CBCR); return rate; diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c b/arch/arm/mach-snapdragon/clock-snapdragon.c index f738f57043..85526186c6 100644 --- a/arch/arm/mach-snapdragon/clock-snapdragon.c +++ b/arch/arm/mach-snapdragon/clock-snapdragon.c @@ -30,7 +30,7 @@ void clk_enable_cbc(phys_addr_t cbcr) ; } -void clk_enable_gpll0(phys_addr_t base, const struct gpll0_ctrl *gpll0) +void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0) { if (readl(base + gpll0->status) & gpll0->status_bit) return; /* clock already enabled */ @@ -41,6 +41,21 @@ void clk_enable_gpll0(phys_addr_t base, const struct gpll0_ctrl *gpll0) ; } +#define BRANCH_ON_VAL (0) +#define BRANCH_NOC_FSM_ON_VAL BIT(29) +#define BRANCH_CHECK_MASK GENMASK(31, 28) + +void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk) +{ + u32 val; + + setbits_le32(base + vclk->ena_vote, vclk->vote_bit); + do { + val = readl(base + vclk->cbcr_reg); + val &= BRANCH_CHECK_MASK; + } while ((val != BRANCH_ON_VAL) && (val != BRANCH_NOC_FSM_ON_VAL)); +} + #define APPS_CMD_RGCR_UPDATE BIT(0) /* Update clock command via CMD_RGCR */ diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.h b/arch/arm/mach-snapdragon/clock-snapdragon.h index 2cff4f8a06..3ae21099c2 100644 --- a/arch/arm/mach-snapdragon/clock-snapdragon.h +++ b/arch/arm/mach-snapdragon/clock-snapdragon.h @@ -11,13 +11,18 @@ #define CFG_CLK_SRC_GPLL0 (1 << 8) #define CFG_CLK_SRC_MASK (7 << 8) -struct gpll0_ctrl { +struct pll_vote_clk { uintptr_t status; int status_bit; uintptr_t ena_vote; int vote_bit; }; +struct vote_clk { + uintptr_t cbcr_reg; + uintptr_t ena_vote; + int vote_bit; +}; struct bcr_regs { uintptr_t cfg_rcgr; uintptr_t cmd_rcgr; @@ -30,7 +35,7 @@ struct msm_clk_priv { phys_addr_t base; }; -void clk_enable_gpll0(phys_addr_t base, const struct gpll0_ctrl *pll0); +void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0); void clk_bcr_update(phys_addr_t apps_cmd_rgcr); void clk_enable_cbc(phys_addr_t cbcr); void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h index ae784387fa..520e2e6bd7 100644 --- a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h +++ b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h @@ -13,6 +13,7 @@ /* Clocks: (from CLK_CTL_BASE) */ #define GPLL0_STATUS (0x2101C) #define APCS_GPLL_ENA_VOTE (0x45000) +#define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004) #define SDCC_BCR(n) ((n * 0x1000) + 0x41000) #define SDCC_CMD_RCGR(n) ((n * 0x1000) + 0x41004) From patchwork Sat May 12 10:15:56 2018 Content-Type: text/plain; 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Sat, 12 May 2018 03:16:27 -0700 (PDT) From: Ramon Fried To: albert.u.boot@aribaud.net, mateusz.kulikowski@gmail.com, jramirez@baylibre.com, robdclark@gmail.com, sjg@chromium.org Date: Sat, 12 May 2018 13:15:56 +0300 Message-Id: <20180512101558.24375-6-ramon.fried@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180512101558.24375-1-ramon.fried@gmail.com> References: <20180512101558.24375-1-ramon.fried@gmail.com> Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 5/7] mach-snapdragon: Introduce pinctrl driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch adds pinmux and pinctrl driver for TLMM subsystem in snapdragon chipsets. Currently, supporting only 8016, but implementation is generic and 8096 can be added easily. Driver is using the generic dt-bindings and doesn't introduce any new bindings (yet). Signed-off-by: Ramon Fried --- arch/arm/mach-snapdragon/Makefile | 2 + arch/arm/mach-snapdragon/pinctrl-apq8016.c | 162 +++++++++++++++++++++++ arch/arm/mach-snapdragon/pinctrl-snapdragon.c | 118 +++++++++++++++++ arch/arm/mach-snapdragon/pinctrl-snapdragon.h | 21 +++ configs/dragonboard410c_defconfig | 5 + include/dt-bindings/pinctrl/pinctrl-snapdragon.h | 22 +++ 6 files changed, 330 insertions(+) create mode 100644 arch/arm/mach-snapdragon/pinctrl-apq8016.c create mode 100644 arch/arm/mach-snapdragon/pinctrl-snapdragon.c create mode 100644 arch/arm/mach-snapdragon/pinctrl-snapdragon.h create mode 100644 include/dt-bindings/pinctrl/pinctrl-snapdragon.h diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile index 1c23dc52cf..1d35fea912 100644 --- a/arch/arm/mach-snapdragon/Makefile +++ b/arch/arm/mach-snapdragon/Makefile @@ -6,4 +6,6 @@ obj-$(CONFIG_TARGET_DRAGONBOARD820C) += clock-apq8096.o obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o obj-$(CONFIG_TARGET_DRAGONBOARD410C) += clock-apq8016.o obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o +obj-$(CONFIG_TARGET_DRAGONBOARD410C) += pinctrl-apq8016.o +obj-$(CONFIG_TARGET_DRAGONBOARD410C) += pinctrl-snapdragon.o obj-y += clock-snapdragon.o diff --git a/arch/arm/mach-snapdragon/pinctrl-apq8016.c b/arch/arm/mach-snapdragon/pinctrl-apq8016.c new file mode 100644 index 0000000000..8e57e2338c --- /dev/null +++ b/arch/arm/mach-snapdragon/pinctrl-apq8016.c @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm APQ8016 pinctrl + * + * (C) Copyright 2018 Ramon Fried + * + */ + +#include "pinctrl-snapdragon.h" +#include + +const char * const msm_pinctrl_pins[] = { + "GPIO_0", + "GPIO_1", + "GPIO_2", + "GPIO_3", + "GPIO_4", + "GPIO_5", + "GPIO_6", + "GPIO_7", + "GPIO_8", + "GPIO_9", + "GPIO_10", + "GPIO_11", + "GPIO_12", + "GPIO_13", + "GPIO_14", + "GPIO_15", + "GPIO_16", + "GPIO_17", + "GPIO_18", + "GPIO_19", + "GPIO_20", + "GPIO_21", + "GPIO_22", + "GPIO_23", + "GPIO_24", + "GPIO_25", + "GPIO_26", + "GPIO_27", + "GPIO_28", + "GPIO_29", + "GPIO_30", + "GPIO_31", + "GPIO_32", + "GPIO_33", + "GPIO_34", + "GPIO_35", + "GPIO_36", + "GPIO_37", + "GPIO_38", + "GPIO_39", + "GPIO_40", + "GPIO_41", + "GPIO_42", + "GPIO_43", + "GPIO_44", + "GPIO_45", + "GPIO_46", + "GPIO_47", + "GPIO_48", + "GPIO_49", + "GPIO_50", + "GPIO_51", + "GPIO_52", + "GPIO_53", + "GPIO_54", + "GPIO_55", + "GPIO_56", + "GPIO_57", + "GPIO_58", + "GPIO_59", + "GPIO_60", + "GPIO_61", + "GPIO_62", + "GPIO_63", + "GPIO_64", + "GPIO_65", + "GPIO_66", + "GPIO_67", + "GPIO_68", + "GPIO_69", + "GPIO_70", + "GPIO_71", + "GPIO_72", + "GPIO_73", + "GPIO_74", + "GPIO_75", + "GPIO_76", + "GPIO_77", + "GPIO_78", + "GPIO_79", + "GPIO_80", + "GPIO_81", + "GPIO_82", + "GPIO_83", + "GPIO_84", + "GPIO_85", + "GPIO_86", + "GPIO_87", + "GPIO_88", + "GPIO_89", + "GPIO_90", + "GPIO_91", + "GPIO_92", + "GPIO_93", + "GPIO_94", + "GPIO_95", + "GPIO_96", + "GPIO_97", + "GPIO_98", + "GPIO_99", + "GPIO_100", + "GPIO_101", + "GPIO_102", + "GPIO_103", + "GPIO_104", + "GPIO_105", + "GPIO_106", + "GPIO_107", + "GPIO_108", + "GPIO_109", + "GPIO_110", + "GPIO_111", + "GPIO_112", + "GPIO_113", + "GPIO_114", + "GPIO_115", + "GPIO_116", + "GPIO_117", + "GPIO_118", + "GPIO_119", + "GPIO_120", + "GPIO_121", + "GPIO_122", + "GPIO_123", + "GPIO_124", + "GPIO_125", + "GPIO_126", + "GPIO_127", + "GPIO_128", + "GPIO_129", + "SDC1_CLK", + "SDC1_CMD", + "SDC1_DATA", + "SDC2_CLK", + "SDC2_CMD", + "SDC2_DATA", + "QDSD_CLK", + "QDSD_CMD", + "QDSD_DATA0", + "QDSD_DATA1", + "QDSD_DATA2", + "QDSD_DATA3", +}; + +const struct pinctrl_function msm_pinctrl_functions[] = { + {"blsp1_uart", 2}, +}; + +const int msm_functions_count = ARRAY_SIZE(msm_pinctrl_functions); +const int msm_pins_count = ARRAY_SIZE(msm_pinctrl_pins); diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c new file mode 100644 index 0000000000..8aa6f9a7bd --- /dev/null +++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * TLMM driver for Qualcomm APQ8016, APQ8096 + * + * (C) Copyright 2018 Ramon Fried + * + */ + +#include +#include +#include +#include +#include +#include "pinctrl-snapdragon.h" + +struct msm_pinctrl_priv { + phys_addr_t base; +}; + +#define GPIO_CONFIG_OFFSET(x) ((x) * 0x1000) +#define TLMM_GPIO_PULL_MASK GENMASK(1, 0) +#define TLMM_FUNC_SEL_MASK GENMASK(5, 2) +#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6) +#define TLMM_GPIO_ENABLE BIT(9) + +static const struct pinconf_param msm_conf_params[] = { + { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 3 }, + { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, +}; + +static int msm_get_functions_count(struct udevice *dev) +{ + return msm_functions_count; +} + +static int msm_get_pins_count(struct udevice *dev) +{ + return msm_pins_count; +} + +static const char *msm_get_function_name(struct udevice *dev, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].name; +} + +static int msm_pinctrl_probe(struct udevice *dev) +{ + struct msm_pinctrl_priv *priv = dev_get_priv(dev); + + priv->base = devfdt_get_addr(dev); + + return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0; +} + +static const char *msm_get_pin_name(struct udevice *dev, unsigned int selector) +{ + return msm_pinctrl_pins[selector]; +} + +static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector, + unsigned int func_selector) +{ + struct msm_pinctrl_priv *priv = dev_get_priv(dev); + + clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), + TLMM_FUNC_SEL_MASK | TLMM_GPIO_ENABLE, + msm_pinctrl_functions[func_selector].val << 2); + return 0; +} + +static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector, + unsigned int param, unsigned int argument) +{ + struct msm_pinctrl_priv *priv = dev_get_priv(dev); + + switch (param) { + case PIN_CONFIG_DRIVE_STRENGTH: + clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), + TLMM_DRV_STRENGTH_MASK, argument << 6); + break; + case PIN_CONFIG_BIAS_DISABLE: + clrbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), + TLMM_GPIO_PULL_MASK); + break; + default: + return 0; + } + + return 0; +} + +static struct pinctrl_ops msm_pinctrl_ops = { + .get_pins_count = msm_get_pins_count, + .get_pin_name = msm_get_pin_name, + .set_state = pinctrl_generic_set_state, + .pinmux_set = msm_pinmux_set, + .pinconf_num_params = ARRAY_SIZE(msm_conf_params), + .pinconf_params = msm_conf_params, + .pinconf_set = msm_pinconf_set, + .get_functions_count = msm_get_functions_count, + .get_function_name = msm_get_function_name, +}; + +static const struct udevice_id msm_pinctrl_ids[] = { + { .compatible = "qcom,tlmm-msm8916" }, + { .compatible = "qcom,tlmm-apq8016" }, + { } +}; + +U_BOOT_DRIVER(pinctrl_snapdraon) = { + .name = "pinctrl_msm", + .id = UCLASS_PINCTRL, + .of_match = msm_pinctrl_ids, + .priv_auto_alloc_size = sizeof(struct msm_pinctrl_priv), + .ops = &msm_pinctrl_ops, + .probe = msm_pinctrl_probe, +}; diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h new file mode 100644 index 0000000000..3d0527148a --- /dev/null +++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Qualcomm Pin control + * + * (C) Copyright 2018 Ramon Fried + * + */ +#ifndef _PINCTRL_SNAPDRAGON_H +#define _PINCTRL_SNAPDRAGON_H + +struct pinctrl_function { + const char *name; + int val; +}; + +extern const char * const msm_pinctrl_pins[]; +extern const struct pinctrl_function msm_pinctrl_functions[]; +extern const int msm_functions_count; +extern const int msm_pins_count; + +#endif diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig index e6114db2ce..4b3de64dd5 100644 --- a/configs/dragonboard410c_defconfig +++ b/configs/dragonboard410c_defconfig @@ -45,3 +45,8 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_FULL=y +CONFIG_PINCTRL_GENERIC=y +CONFIG_PINMUX=y +CONFIG_PINCONF=y diff --git a/include/dt-bindings/pinctrl/pinctrl-snapdragon.h b/include/dt-bindings/pinctrl/pinctrl-snapdragon.h new file mode 100644 index 0000000000..615affb6f2 --- /dev/null +++ b/include/dt-bindings/pinctrl/pinctrl-snapdragon.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * This header provides constants for Qualcomm Snapdragon pinctrl bindings. + * + * (C) Copyright 2018 Ramon Fried + * + */ + +#ifndef _DT_BINDINGS_PINCTRL_SNAPDRAGON_H +#define _DT_BINDINGS_PINCTRL_SNAPDRAGON_H + +/* GPIO Drive Strength */ +#define DRIVE_STRENGTH_2MA 0 +#define DRIVE_STRENGTH_4MA 1 +#define DRIVE_STRENGTH_6MA 2 +#define DRIVE_STRENGTH_8MA 3 +#define DRIVE_STRENGTH_10MA 4 +#define DRIVE_STRENGTH_12MA 5 +#define DRIVE_STRENGTH_14MA 6 +#define DRIVE_STRENGTH_16MA 7 + +#endif From patchwork Sat May 12 10:15:57 2018 Content-Type: text/plain; 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Sat, 12 May 2018 03:16:29 -0700 (PDT) From: Ramon Fried To: albert.u.boot@aribaud.net, mateusz.kulikowski@gmail.com, jramirez@baylibre.com, robdclark@gmail.com, sjg@chromium.org Date: Sat, 12 May 2018 13:15:57 +0300 Message-Id: <20180512101558.24375-7-ramon.fried@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180512101558.24375-1-ramon.fried@gmail.com> References: <20180512101558.24375-1-ramon.fried@gmail.com> Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 6/7] db410: added pinctrl node and serial bindings X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Added TLMM pinctrl node for pin muxing & config. Additionally, added a serial node for uart. Signed-off-by: Ramon Fried Reviewed-by: Simon Glass --- arch/arm/dts/dragonboard410c.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts index d9d5831f4f..182a865b0a 100644 --- a/arch/arm/dts/dragonboard410c.dts +++ b/arch/arm/dts/dragonboard410c.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "skeleton64.dtsi" +#include / { model = "Qualcomm Technologies, Inc. Dragonboard 410c"; @@ -38,6 +39,17 @@ ranges = <0x0 0x0 0x0 0xffffffff>; compatible = "simple-bus"; + pinctrl: qcom,tlmm@1000000 { + compatible = "qcom,tlmm-apq8016"; + reg = <0x1000000 0x400000>; + + blsp1_uart: uart { + function = "blsp1_uart"; + pins = "GPIO_4", "GPIO_5"; + drive-strength = ; + bias-disable; + }; + }; clkc: qcom,gcc@1800000 { compatible = "qcom,gcc-apq8016"; reg = <0x1800000 0x80000>; @@ -49,6 +61,8 @@ compatible = "qcom,msm-uartdm-v1.4"; reg = <0x78b0000 0x200>; clock = <&clkc 4>; + pinctrl-names = "uart"; + pinctrl-0 = <&blsp1_uart>; }; soc_gpios: pinctrl@1000000 { From patchwork Sat May 12 10:15:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramon Fried X-Patchwork-Id: 912408 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="XPu7y63R"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 40jjdF0g6rz9rxs for ; Sat, 12 May 2018 20:20:01 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id BE71DC223E8; Sat, 12 May 2018 10:18:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 762C9C22410; Sat, 12 May 2018 10:17:00 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 15C6FC2245B; Sat, 12 May 2018 10:16:36 +0000 (UTC) Received: from mail-wm0-f66.google.com (mail-wm0-f66.google.com [74.125.82.66]) by lists.denx.de (Postfix) with ESMTPS id E208FC2242A for ; Sat, 12 May 2018 10:16:31 +0000 (UTC) Received: by mail-wm0-f66.google.com with SMTP id x12-v6so5687205wmc.0 for ; Sat, 12 May 2018 03:16:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=QGxFHnlRFEeFUIdydJBhS7pxXgB3+iLF0lm1+HvlHd4=; b=XPu7y63R6oL5PCh0ICP1z+OYdtN7W8KhlneOcSYqki0WBLpv9dIxu3ocyAYJ/UGQvI fMd+UBnmJ/YQX8JEdMDCczTfJgQFvkiy5rhroE5EP7UeR+FyU1Hsp3EEupawYlxiTWPe m3sa/28KjU6m8mqrZSkSE3KCchvpfbuWs4Lpy8/dIEBAwC1Gagb1XpFGJ1n8MgtiE7v8 Ai8GQOlLTC96wh0C3UudC6EHbrSefrJtgUTkWxEL3bR62/vfbwCcqhUm7ZP2cNu5aek1 oFscFZXAXZ+wfB3Qx3Hxb2EleCRiNVOxl/zvH5l6je5Af3gE2SUr93Y1LPwDqmYSKHWG zHhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QGxFHnlRFEeFUIdydJBhS7pxXgB3+iLF0lm1+HvlHd4=; b=BaBE9m7SC0ENliAsFh3jpVeKPa191XeEtLCEeeaDo72EQFsp39BBYIIJPXgdwha2Ch 5goGSQbNbdW9dpv1GXjx1cBGZHJWlVcT2+wERwE4xo4VhV9igfwlRgBlGTJthOR5Vb2E +HmUYzo0TJSQtShTFHFllSuJR+AzvZ9Ya10sQNWFUFsYo6b8OguYr/9/357PWaxp+zdE ndTjhGh+D9Y/pRm9mzkJqebEeRKgz1zA6o5l7TP3b1/30eBMevP5gAkwQrZU4ndvL+hr pr4Bhg2oVe33o8tyutzlj4VsIi3rUonK2Xa0WGQZkKwbkzn8b0SRa2BNsdD4+3aW8pF5 13xQ== X-Gm-Message-State: ALKqPwdcl1Ivs0ARqmaShn2R0OieVOeEX68Z9o6ohg1kmX9aE2XhvwGR Z75bbcIyDswtoPQxE4U/gh7M8MK8Uh4= X-Google-Smtp-Source: AB8JxZqf2PqNiL1xMWrjnplgYgb7t1Q8fEmzzYYTiCJ2UzWaCDgesxQsDicTHjHXIn9ZKT8/xAlaqA== X-Received: by 2002:a1c:4ad9:: with SMTP id n86-v6mr1133493wmi.0.1526120191565; Sat, 12 May 2018 03:16:31 -0700 (PDT) Received: from localhost.localdomain ([141.226.166.38]) by smtp.gmail.com with ESMTPSA id h67-v6sm2881280wmg.41.2018.05.12.03.16.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 12 May 2018 03:16:30 -0700 (PDT) From: Ramon Fried To: albert.u.boot@aribaud.net, mateusz.kulikowski@gmail.com, jramirez@baylibre.com, robdclark@gmail.com, sjg@chromium.org Date: Sat, 12 May 2018 13:15:58 +0300 Message-Id: <20180512101558.24375-8-ramon.fried@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180512101558.24375-1-ramon.fried@gmail.com> References: <20180512101558.24375-1-ramon.fried@gmail.com> Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 7/7] serial: serial_msm: added pinmux & config X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Serial port configuration was missing from previous implementation. It only worked because it was preconfigured by LK. This patch configures the uart for 115200 8N1. It also configures the pin mux for uart pins using DT bindings. Signed-off-by: Ramon Fried Reviewed-by: Simon Glass --- drivers/serial/serial_msm.c | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c index 22301c0e37..4a0a2cc450 100644 --- a/drivers/serial/serial_msm.c +++ b/drivers/serial/serial_msm.c @@ -16,6 +16,7 @@ #include #include #include +#include /* Serial registers - this driver works in uartdm mode*/ @@ -25,6 +26,9 @@ #define UARTDM_RXFS 0x50 /* RX channel status register */ #define UARTDM_RXFS_BUF_SHIFT 0x7 /* Number of bytes in the packing buffer */ #define UARTDM_RXFS_BUF_MASK 0x7 +#define UARTDM_MR1 0x00 +#define UARTDM_MR2 0x04 +#define UARTDM_CSR 0xA0 #define UARTDM_SR 0xA4 /* Status register */ #define UARTDM_SR_RX_READY (1 << 0) /* Word is the receiver FIFO */ @@ -45,6 +49,10 @@ #define UARTDM_TF 0x100 /* UART Transmit FIFO register */ #define UARTDM_RF 0x140 /* UART Receive FIFO register */ +#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC +#define MSM_BOOT_UART_DM_8_N_1_MODE 0x34 +#define MSM_BOOT_UART_DM_CMD_RESET_RX 0x10 +#define MSM_BOOT_UART_DM_CMD_RESET_TX 0x20 DECLARE_GLOBAL_DATA_PTR; @@ -179,6 +187,14 @@ static int msm_uart_clk_init(struct udevice *dev) return 0; } +static void uart_dm_init(struct msm_serial_data *priv) +{ + writel(UART_DM_CLK_RX_TX_BIT_RATE, priv->base + UARTDM_CSR); + writel(0x0, priv->base + UARTDM_MR1); + writel(MSM_BOOT_UART_DM_8_N_1_MODE, priv->base + UARTDM_MR2); + writel(MSM_BOOT_UART_DM_CMD_RESET_RX, priv->base + UARTDM_CR); + writel(MSM_BOOT_UART_DM_CMD_RESET_TX, priv->base + UARTDM_CR); +} static int msm_serial_probe(struct udevice *dev) { struct msm_serial_data *priv = dev_get_priv(dev); @@ -190,12 +206,8 @@ static int msm_serial_probe(struct udevice *dev) if (msm_uart_clk_init(dev)) return -EINVAL; - if (readl(priv->base + UARTDM_SR) & UARTDM_SR_UART_OVERRUN) - writel(UARTDM_CR_CMD_RESET_ERR, priv->base + UARTDM_CR); - - writel(0, priv->base + UARTDM_IMR); - writel(UARTDM_CR_CMD_STALE_EVENT_DISABLE, priv->base + UARTDM_CR); - msm_serial_fetch(dev); + pinctrl_select_state(dev, "uart"); + uart_dm_init(priv); return 0; }