From patchwork Fri Nov 8 06:57:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Li Xu X-Patchwork-Id: 2008285 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Xl8sf5nNhz1xy0 for ; Fri, 8 Nov 2024 17:58:14 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2F1433858403 for ; Fri, 8 Nov 2024 06:58:12 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from zg8tmja5ljk3lje4ms43mwaa.icoremail.net (zg8tmja5ljk3lje4ms43mwaa.icoremail.net [209.97.181.73]) by sourceware.org (Postfix) with ESMTP id 7D40D3858D20 for ; Fri, 8 Nov 2024 06:57:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7D40D3858D20 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=eswincomputing.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 7D40D3858D20 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=209.97.181.73 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1731049074; cv=none; b=Ux/JK8frw4eOVn8IANJZY6Z3jDxh7JeHNqKrQV8fh+f4bKfbOWzChCNBMbP5GKnU5C5j9IGHQrsXWum57/rg0ueIpHuOBTeBDXBZzjl8glJ3p2kzEjpa1OklrJMEzXFjLzVMUXe9nDOGTZfXf6fddJJ4OgeAvAI9FrXZ4ZXRv6A= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1731049074; c=relaxed/simple; bh=tqINIANIFg2caGfdb+TsMNtrSa6X4eACAc3sLoLVf4M=; h=From:To:Subject:Date:Message-Id; b=xoQ7snoOrIaIm7N0CO19cxUeqAkenqqwB6U9uPVOq3ek57TOt4aYKfQm4fC2+ZR9UtjlixwXJCm6vumDZ75u9eixRJ9kHWFMKf7SHpw7azqnlC1ik41ZPKHSAa23VcDIVuXlJOzp/ZYqBzwt2qcTWJxxifvEzH+IvUCqYoKmll0= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from host014-ubuntu-1804.lxd (unknown [10.12.130.31]) by app1 (Coremail) with SMTP id TAJkCgAXR+Voti1n2isUAA--.29861S4; Fri, 08 Nov 2024 14:57:45 +0800 (CST) From: Li Xu To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, juzhe.zhong@rivai.ai, xuli Subject: [PATCH] RISC-V: Add testcases for unsigned imm vec SAT_SUB form1 Date: Fri, 8 Nov 2024 06:57:42 +0000 Message-Id: <20241108065742.6299-1-xuli1@eswincomputing.com> X-Mailer: git-send-email 2.17.1 X-CM-TRANSID: TAJkCgAXR+Voti1n2isUAA--.29861S4 X-Coremail-Antispam: 1UD129KBjvAXoWfGw4xCFW8Gr1fKry5tryrZwb_yoW8Wry5Jo WkXrs3G3WxWwnIkryxu3WfG3Wfur1xAw13XFZYyF1DGF4rCa15Cwn0q3WxZFW8Gr43JF4Y vr42yFZ8WrWvq3y3n29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUY87AC8VAFwI0_Gr0_Xr1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2 x7M28EF7xvwVC0I7IYx2IY67AKxVWDJVCq3wA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVW8 Jr0_Cr1UM28EF7xvwVC2z280aVAFwI0_GcCE3s1l84ACjcxK6I8E87Iv6xkF7I0E14v26r xl6s0DM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj 6xIIjxv20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr 0_Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxkIecxEwVCm-wCF 04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r 18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw1lIxkGc2Ij64vI r41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr 1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvE x4A2jsIEc7CjxVAFwI0_Jr0_GrUvcSsGvfC2KfnxnUUI43ZEXa7VUbXdbUUUUUU== X-CM-SenderInfo: 50xoxi46hv4xpqfrz1xxwl0woofrz/ X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: xuli form1: void __attribute__((noinline)) \ vec_sat_u_sub_imm##IMM##_##T##_fmt_1 (T *out, T *in, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \ out[i] = (T)IMM >= in[i] ? (T)IMM - in[i] : 0; \ } Passed the rv64gcv full regression test. Signed-off-by: Li Xu gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h: add data for vec sat_sub. * gcc.target/riscv/rvv/autovec/vec_sat_arith.h: add unsigned imm vec sat_sub form1. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-1.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-2.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-3.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-4.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-1.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-2.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-3.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-4.c: New test. Signed-off-by: Li Xu --- .../riscv/rvv/autovec/binop/vec_sat_data.h | 240 ++++++++++++++++++ .../rvv/autovec/binop/vec_sat_u_sub_imm-1.c | 9 + .../rvv/autovec/binop/vec_sat_u_sub_imm-2.c | 9 + .../rvv/autovec/binop/vec_sat_u_sub_imm-3.c | 9 + .../rvv/autovec/binop/vec_sat_u_sub_imm-4.c | 9 + .../autovec/binop/vec_sat_u_sub_imm-run-1.c | 28 ++ .../autovec/binop/vec_sat_u_sub_imm-run-2.c | 28 ++ .../autovec/binop/vec_sat_u_sub_imm-run-3.c | 28 ++ .../autovec/binop/vec_sat_u_sub_imm-run-4.c | 28 ++ .../riscv/rvv/autovec/vec_sat_arith.h | 18 ++ 10 files changed, 406 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-4.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h index 32edc358a08..bcb4a3f3f1d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h @@ -253,6 +253,246 @@ uint64_t TEST_UNARY_DATA(uint64_t, sat_u_add_imm)[][2][N] = }, }; +uint8_t TEST_UNARY_DATA(uint8_t, sat_u_sub_imm)[][2][N] = +{ + { /* For sub imm 0 */ + { + 0, 1, 5, 255, + 0, 1, 5, 255, + 0, 1, 5, 255, + 0, 1, 5, 255, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, + { /* For sub imm 1 */ + { + 0, 1, 2, 8, + 0, 1, 2, 8, + 0, 1, 2, 8, + 0, 1, 2, 8, + }, + { + 1, 0, 0, 0, + 1, 0, 0, 0, + 1, 0, 0, 0, + 1, 0, 0, 0, + }, + }, + { /* For sub imm 254 */ + { + 0, 1, 254, 255, + 0, 1, 254, 255, + 0, 1, 254, 255, + 0, 1, 254, 255, + }, + { + 254, 253, 0, 0, + 254, 253, 0, 0, + 254, 253, 0, 0, + 254, 253, 0, 0, + }, + }, + { /* For sub imm 255 */ + { + 0, 1, 5, 255, + 0, 1, 5, 255, + 0, 1, 5, 255, + 0, 1, 5, 255, + }, + { + 255, 254, 250, 0, + 255, 254, 250, 0, + 255, 254, 250, 0, + 255, 254, 250, 0, + }, + }, +}; + +uint16_t TEST_UNARY_DATA(uint16_t, sat_u_sub_imm)[][2][N] = +{ + { /* For sub imm 0 */ + { + 0, 1, 5, 65535, + 0, 1, 5, 65535, + 0, 1, 5, 65535, + 0, 1, 5, 65535, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, + { /* For sub imm 1 */ + { + 0, 1, 5, 8, + 0, 1, 5, 8, + 0, 1, 5, 8, + 0, 1, 5, 8, + }, + { + 1, 0, 0, 0, + 1, 0, 0, 0, + 1, 0, 0, 0, + 1, 0, 0, 0, + }, + }, + { /* For sub imm 65534 */ + { + 0, 1, 65534, 65535, + 0, 1, 65534, 65535, + 0, 1, 65534, 65535, + 0, 1, 65534, 65535, + }, + { + 65534, 65533, 0, 0, + 65534, 65533, 0, 0, + 65534, 65533, 0, 0, + 65534, 65533, 0, 0, + }, + }, + { /* For sub imm 65535 */ + { + 0, 1, 65534, 65535, + 0, 1, 65534, 65535, + 0, 1, 65534, 65535, + 0, 1, 65534, 65535, + }, + { + 65535, 65534, 1, 0, + 65535, 65534, 1, 0, + 65535, 65534, 1, 0, + 65535, 65534, 1, 0, + }, + }, +}; + +uint32_t TEST_UNARY_DATA(uint32_t, sat_u_sub_imm)[][2][N] = +{ + { /* For sub imm 0 */ + { + 0, 1, 5, 4294967295, + 0, 1, 5, 4294967295, + 0, 1, 5, 4294967295, + 0, 1, 5, 4294967295, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, + { /* For sub imm 1 */ + { + 0, 1, 5, 8, + 0, 1, 5, 8, + 0, 1, 5, 8, + 0, 1, 5, 8, + }, + { + 1, 0, 0, 0, + 1, 0, 0, 0, + 1, 0, 0, 0, + 1, 0, 0, 0, + }, + }, + { /* For sub imm 4294967294 */ + { + 0, 1, 4294967294, 4294967295, + 0, 1, 4294967294, 4294967295, + 0, 1, 4294967294, 4294967295, + 0, 1, 4294967294, 4294967295, + }, + { + 4294967294, 4294967293, 0, 0, + 4294967294, 4294967293, 0, 0, + 4294967294, 4294967293, 0, 0, + 4294967294, 4294967293, 0, 0, + }, + }, + { /* For sub imm 4294967295 */ + { + 0, 1, 4294967294, 4294967295, + 0, 1, 4294967294, 4294967295, + 0, 1, 4294967294, 4294967295, + 0, 1, 4294967294, 4294967295, + }, + { + 4294967295, 4294967294, 1, 0, + 4294967295, 4294967294, 1, 0, + 4294967295, 4294967294, 1, 0, + 4294967295, 4294967294, 1, 0, + }, + }, +}; + +uint64_t TEST_UNARY_DATA(uint64_t, sat_u_sub_imm)[][2][N] = +{ + { /* For sub imm 0 */ + { + 0, 1, 5, 18446744073709551615u, + 0, 1, 5, 18446744073709551615u, + 0, 1, 5, 18446744073709551615u, + 0, 1, 5, 18446744073709551615u, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, + { /* For sub imm 1 */ + { + 0, 1, 5, 8, + 0, 1, 5, 8, + 0, 1, 5, 8, + 0, 1, 5, 8, + }, + { + 1, 0, 0, 0, + 1, 0, 0, 0, + 1, 0, 0, 0, + 1, 0, 0, 0, + }, + }, + { /* For sub imm 18446744073709551614 */ + { + 0, 1, 18446744073709551614u, 18446744073709551615u, + 0, 1, 18446744073709551614u, 18446744073709551615u, + 0, 1, 18446744073709551614u, 18446744073709551615u, + 0, 1, 18446744073709551614u, 18446744073709551615u, + }, + { + 18446744073709551614u, 18446744073709551613u, 0, 0, + 18446744073709551614u, 18446744073709551613u, 0, 0, + 18446744073709551614u, 18446744073709551613u, 0, 0, + 18446744073709551614u, 18446744073709551613u, 0, 0, + }, + }, + { /* For sub imm 18446744073709551615 */ + { + 0, 1, 18446744073709551614u, 18446744073709551615u, + 0, 1, 18446744073709551614u, 18446744073709551615u, + 0, 1, 18446744073709551614u, 18446744073709551615u, + 0, 1, 18446744073709551614u, 18446744073709551615u, + }, + { + 18446744073709551615u, 18446744073709551614u, 1, 0, + 18446744073709551615u, 18446744073709551614u, 1, 0, + 18446744073709551615u, 18446744073709551614u, 1, 0, + 18446744073709551615u, 18446744073709551614u, 1, 0, + }, + }, +}; + #define TEST_BINARY_DATA_NAME(T1, T2, NAME) test_bin_##T1##_##T2##_##NAME##_data #define TEST_BINARY_DATA_NAME_WRAP(T1, T2, NAME) \ TEST_BINARY_DATA_NAME(T1, T2, NAME) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-1.c new file mode 100644 index 00000000000..52192d76d50 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_IMM_FMT_1(uint8_t, 10) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-2.c new file mode 100644 index 00000000000..b161ff0410f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-2.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_IMM_FMT_1(uint16_t, 70) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-3.c new file mode 100644 index 00000000000..13c8cf5753e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-3.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_IMM_FMT_1(uint32_t, 5) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-4.c new file mode 100644 index 00000000000..5ed237b6262 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-4.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_IMM_FMT_1(uint64_t, 9) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-1.c new file mode 100644 index 00000000000..19d3bb087da --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-1.c @@ -0,0 +1,28 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint8_t +#define RUN(T, out, in, expect, IMM, N) \ + RUN_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, out, in, expect, IMM, N) + +DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 0) +DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 1) +DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 254) +DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 255) + +int +main () +{ + T out[N]; + T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_sub_imm); + + RUN (T, out, d[0][0], d[0][1], 0, N); + RUN (T, out, d[1][0], d[1][1], 1, N); + RUN (T, out, d[2][0], d[2][1], 254, N); + RUN (T, out, d[3][0], d[3][1], 255, N); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-2.c new file mode 100644 index 00000000000..f304d82f7d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-2.c @@ -0,0 +1,28 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint16_t +#define RUN(T, out, in, expect, IMM, N) \ + RUN_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, out, in, expect, IMM, N) + +DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 0) +DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 1) +DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 65534) +DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 65535) + +int +main () +{ + T out[N]; + T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_sub_imm); + + RUN (T, out, d[0][0], d[0][1], 0, N); + RUN (T, out, d[1][0], d[1][1], 1, N); + RUN (T, out, d[2][0], d[2][1], 65534, N); + RUN (T, out, d[3][0], d[3][1], 65535, N); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-3.c new file mode 100644 index 00000000000..283d37f34d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-3.c @@ -0,0 +1,28 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint32_t +#define RUN(T, out, in, expect, IMM, N) \ + RUN_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, out, in, expect, IMM, N) + +DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 0) +DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 1) +DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 4294967294) +DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 4294967295) + +int +main () +{ + T out[N]; + T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_sub_imm); + + RUN (T, out, d[0][0], d[0][1], 0, N); + RUN (T, out, d[1][0], d[1][1], 1, N); + RUN (T, out, d[2][0], d[2][1], 4294967294, N); + RUN (T, out, d[3][0], d[3][1], 4294967295, N); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-4.c new file mode 100644 index 00000000000..2512975abcf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-4.c @@ -0,0 +1,28 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint64_t +#define RUN(T, out, in, expect, IMM, N) \ + RUN_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, out, in, expect, IMM, N) + +DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 0) +DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 1) +DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 18446744073709551614u) +DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 18446744073709551615u) + +int +main () +{ + T out[N]; + T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_sub_imm); + + RUN (T, out, d[0][0], d[0][1], 0, N); + RUN (T, out, d[1][0], d[1][1], 1, N); + RUN (T, out, d[2][0], d[2][1], 18446744073709551614u, N); + RUN (T, out, d[3][0], d[3][1], 18446744073709551615u, N); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h index c2e52a4ba96..cb419553926 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h @@ -468,6 +468,24 @@ vec_sat_u_sub_##T1##_##T2##_fmt_zip (T1 *x, T2 b, unsigned limit) \ } #define DEF_VEC_SAT_U_SUB_ZIP_WRAP(T1, T2) DEF_VEC_SAT_U_SUB_ZIP(T1, T2) +#define DEF_VEC_SAT_U_SUB_IMM_FMT_1(T, IMM) \ +void __attribute__((noinline)) \ +vec_sat_u_sub_imm##IMM##_##T##_fmt_1 (T *out, T *in, unsigned limit) \ +{ \ + unsigned i; \ + for (i = 0; i < limit; i++) \ + out[i] = (T)IMM >= in[i] ? (T)IMM - in[i] : 0; \ +} + +#define DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP(T, IMM) \ + DEF_VEC_SAT_U_SUB_IMM_FMT_1(T, IMM) + +#define RUN_VEC_SAT_U_SUB_IMM_FMT_1(T, out, op_1, expect, IMM, N) \ + vec_sat_u_sub_imm##IMM##_##T##_fmt_1(out, op_1, N); \ + VALIDATE_RESULT (out, expect, N) +#define RUN_VEC_SAT_U_SUB_IMM_FMT_1_WRAP(T, out, op_1, expect, IMM, N) \ + RUN_VEC_SAT_U_SUB_IMM_FMT_1(T, out, op_1, expect, IMM, N) + #define DEF_VEC_SAT_S_SUB_FMT_1(T, UT, MIN, MAX) \ void __attribute__((noinline)) \ vec_sat_s_sub_##T##_fmt_1 (T *out, T *op_1, T *op_2, unsigned limit) \