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dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Received: by mail.gandi.net (Postfix) with ESMTPSA id D5EEC4000C; Wed, 6 Nov 2024 16:03:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1730909038; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=w0h0STs8I6iL7FEbvTaex0RoYlDDG69yp2h2qtyDFI4=; b=bqCjkOeOTmbg6o34HMblXg+UIczqzp8EpjQc5cA002RhOOccz3hjwm41UNPcf+IbrAZc2+ mT4uALzCzA/zKyO9kY84zmAIsccp+I/1/aCf+HsnRYAlDieEs+Rd9jE9RjlrJKlXOrKo7X Lyl4jGM2LDpc7qaPT1qh8UDQvoF3pAWZZX+qeNm0W29bglpCYZAO5lYUUJDU8rcyTRwcOj /k31gB8zi366G/kb3A21EFe0dXWg1AOnXlp5BMu8UNxNJyaiv+UTB63UWdyMkx50pvnYv8 NReSAsPLN5oBIK+FNDXP8y7clAelYbuLiLFQSd6U83D1rYPmo3xSAQmj1ccNdw== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Wed, 06 Nov 2024 17:03:52 +0100 Subject: [PATCH v2 01/10] dt-bindings: soc: mobileye: set `#clock-cells = <1>` for all compatibles Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241106-mbly-clk-v2-1-84cfefb3f485@bootlin.com> References: <20241106-mbly-clk-v2-0-84cfefb3f485@bootlin.com> In-Reply-To: <20241106-mbly-clk-v2-0-84cfefb3f485@bootlin.com> To: Vladimir Kondratiev , =?utf-8?q?Gr?= =?utf-8?q?=C3=A9gory_Clement?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Thomas Bogendoerfer Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.14.2 X-GND-Sasl: theo.lebrun@bootlin.com Some compatibles expose a single clock. For those, we used to let them using `#clock-cells = <0>` (ie <&olb> reference rather than <&olb 0>). Switch away from that: enforce a cell for all compatibles. This is more straight forward, and avoids devicetree changes whenever a compatible goes from exposing a single clock to multiple ones. Also, dt-bindings get simpler. *This is an ABI break*. Change it while EyeQ5 platform support is at its infancy, without any user. More clocks might hide in each OLB as some registers are still unknown. Signed-off-by: Théo Lebrun Reviewed-by: Krzysztof Kozlowski Reviewed-by: Rob Herring (Arm) --- .../bindings/soc/mobileye/mobileye,eyeq5-olb.yaml | 24 +--------------------- 1 file changed, 1 insertion(+), 23 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml index f7e606d45ebcfc46ffe076e23a2ed514bfff9b8f..6d11472ba5a704d5d20f43776e5867f507a39242 100644 --- a/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml +++ b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml @@ -41,9 +41,7 @@ properties: enum: [ 1, 2 ] '#clock-cells': - description: - Cell is clock index. Optional if compatible has a single clock. - enum: [ 0, 1 ] + const: 1 clocks: maxItems: 1 @@ -312,26 +310,6 @@ allOf: properties: '#reset-cells': false - # Compatibles exposing a single clock. - - if: - properties: - compatible: - contains: - enum: - - mobileye,eyeq6h-central-olb - - mobileye,eyeq6h-east-olb - - mobileye,eyeq6h-west-olb - - mobileye,eyeq6h-ddr0-olb - - mobileye,eyeq6h-ddr1-olb - then: - properties: - '#clock-cells': - const: 0 - else: - properties: - '#clock-cells': - const: 1 - # Only EyeQ5 has pinctrl in OLB. - if: not: From patchwork Wed Nov 6 16:03:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 2007615 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=bootlin.com header.i=@bootlin.com header.a=rsa-sha256 header.s=gm1 header.b=BZ67JaIl; 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bh=XbSQpx6+P5te4JBOfJJ+Yvd01YB99e7I0NZ06uZJ9QI=; b=BZ67JaIlG3gOsJQ7UFS/LgdHQFisOepCXrAJKo38yPsnFzJOevKPFiFrleYEoczlhp6i8O iAgJFB/+1H4g7kU5Iqx4TjqXf0tpr3YBBxpULQVzc4v+73Q5kLbhjmu/EqV/fjsJVQRh+6 /mujgXGxPJ9grQ8xnVvk26i+gSiCDW5x1z2IW3x0JTCIv9Xwt7JYUrpSo0OWeFdz7D8PqA r/0zjQkaxTA3ALSEDswlBDNkR1LMsFFQAYnB4IwkMAqUwpvM470cjcABC0mlCUU8MnmBXO IP2cbEwF3InywmQriZokF9o35byOxMpDKtiXa9QyWr1KumO7YlOnGRV842cNWw== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Wed, 06 Nov 2024 17:03:53 +0100 Subject: [PATCH v2 02/10] dt-bindings: clock: eyeq: add more Mobileye EyeQ5/EyeQ6H clocks Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241106-mbly-clk-v2-2-84cfefb3f485@bootlin.com> References: <20241106-mbly-clk-v2-0-84cfefb3f485@bootlin.com> In-Reply-To: <20241106-mbly-clk-v2-0-84cfefb3f485@bootlin.com> To: Vladimir Kondratiev , =?utf-8?q?Gr?= =?utf-8?q?=C3=A9gory_Clement?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Thomas Bogendoerfer Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.14.2 X-GND-Sasl: theo.lebrun@bootlin.com Add #defines for Mobileye clock controller: - EyeQ5 core 0 thru 3 clocks. Internally: EQ5C_PLL_CPU: already exposed └── EQ5C_CPU_OCC: unexposed, no reason to do so ├── EQ5C_CPU_CORE0: new! ├── EQ5C_CPU_CORE1: new! ├── EQ5C_CPU_CORE2: new! └── EQ5C_CPU_CORE3: new! - EyeQ5 peripheral clocks. Internally: EQ5C_PLL_PER: already exposed ├── EQ5C_PER_OCC: new! │ ├── EQ5C_PER_SPI: new! │ ├── EQ5C_PER_I2C: new! │ ├── EQ5C_PER_GPIO: new! │ └── EQ5C_PER_UART: new! ├── EQ5C_PER_EMMC: new! └── EQ5C_PER_OCC_PCI: new! - EyeQ6H central OLB. Internally: EQ6HC_CENTRAL_PLL_CPU: new! └── EQ6HC_CENTRAL_CPU_OCC: new! - EyeQ6H west OLB. Internally: EQ6HC_WEST_PLL_PER: new! └── EQ6HC_WEST_PER_OCC: new! └── EQ6HC_WEST_PER_UART: new! Signed-off-by: Théo Lebrun Acked-by: Krzysztof Kozlowski --- include/dt-bindings/clock/mobileye,eyeq5-clk.h | 44 +++++++++++++++++++------- 1 file changed, 33 insertions(+), 11 deletions(-) diff --git a/include/dt-bindings/clock/mobileye,eyeq5-clk.h b/include/dt-bindings/clock/mobileye,eyeq5-clk.h index b433c1772c28fae818b3a6ba428d1f89000f9206..f353c2988035f7c9fb84e4b59c6c4a220436454b 100644 --- a/include/dt-bindings/clock/mobileye,eyeq5-clk.h +++ b/include/dt-bindings/clock/mobileye,eyeq5-clk.h @@ -6,24 +6,46 @@ #ifndef _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ5_CLK_H #define _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ5_CLK_H -#define EQ5C_PLL_CPU 0 -#define EQ5C_PLL_VMP 1 -#define EQ5C_PLL_PMA 2 -#define EQ5C_PLL_VDI 3 -#define EQ5C_PLL_DDR0 4 -#define EQ5C_PLL_PCI 5 -#define EQ5C_PLL_PER 6 -#define EQ5C_PLL_PMAC 7 -#define EQ5C_PLL_MPC 8 -#define EQ5C_PLL_DDR1 9 +#define EQ5C_PLL_CPU 0 +#define EQ5C_PLL_VMP 1 +#define EQ5C_PLL_PMA 2 +#define EQ5C_PLL_VDI 3 +#define EQ5C_PLL_DDR0 4 +#define EQ5C_PLL_PCI 5 +#define EQ5C_PLL_PER 6 +#define EQ5C_PLL_PMAC 7 +#define EQ5C_PLL_MPC 8 +#define EQ5C_PLL_DDR1 9 -#define EQ5C_DIV_OSPI 10 +#define EQ5C_DIV_OSPI 10 + +/* EQ5C_PLL_CPU children */ +#define EQ5C_CPU_CORE0 11 +#define EQ5C_CPU_CORE1 12 +#define EQ5C_CPU_CORE2 13 +#define EQ5C_CPU_CORE3 14 + +/* EQ5C_PLL_PER children */ +#define EQ5C_PER_OCC 15 +#define EQ5C_PER_UART 16 +#define EQ5C_PER_SPI 17 +#define EQ5C_PER_I2C 18 +#define EQ5C_PER_GPIO 19 +#define EQ5C_PER_EMMC 20 +#define EQ5C_PER_OCC_PCI 21 #define EQ6LC_PLL_DDR 0 #define EQ6LC_PLL_CPU 1 #define EQ6LC_PLL_PER 2 #define EQ6LC_PLL_VDI 3 +#define EQ6HC_CENTRAL_PLL_CPU 0 +#define EQ6HC_CENTRAL_CPU_OCC 1 + +#define EQ6HC_WEST_PLL_PER 0 +#define EQ6HC_WEST_PER_OCC 1 +#define EQ6HC_WEST_PER_UART 2 + #define EQ6HC_SOUTH_PLL_VDI 0 #define EQ6HC_SOUTH_PLL_PCIE 1 #define EQ6HC_SOUTH_PLL_PER 2