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Wed, 6 Nov 2024 11:47:57 +0000 (GMT) X-AuditID: cbfec7f5-ed1d670000004fad-89-672b576e9c71 Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id F6.BB.19920.D675B276; Wed, 6 Nov 2024 11:47:57 +0000 (GMT) Received: from amerzlyakov-PC (unknown [106.109.129.19]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20241106114757eusmtip2692048d68f40111bf21691a7aa1ee0aa~FXqEJWd9D2788127881eusmtip2g; Wed, 6 Nov 2024 11:47:57 +0000 (GMT) Date: Wed, 6 Nov 2024 14:47:57 +0300 From: Alexey Merzlyakov To: Jeff Law Cc: gcc-patches@gcc.gnu.org, alexey.merzlyakov@samsung.com Subject: [PATCH v2] RISC-V: zero_extend(not) -> xor optimization [PR112398] Message-ID: MIME-Version: 1.0 In-Reply-To: <79e85c69-6fcb-4aff-86b4-84d186948f10@gmail.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuplleLIzCtJLcpLzFFi42LZduzned28cO10g8fbxC1W9Wxjsvj0P91i z6ydjA7MHkfvb2Ty2DnrLrtH35ZVjAHMUVw2Kak5mWWpRfp2CVwZaz/MYyx4ZFYx8cB5pgbG bdpdjJwcEgImEgenbmHuYuTiEBJYwSjx/OACdgjnC6PEkidHoDKfGSX+Nm9khGm5fOw+VGI5 o8Tnu8ugWt4ySpw6u4sJpIpFQEXi2c6jYDabgLnEiZNTWUBsEaD4t+49zCA2s4CVxOeJ88Gm Cgt4S3TcvsfWxcjBwSugK7HoOA9ImFdAUOLkzCdgrZwCthJT300H2yUhsJRD4tqHyVAXuUhc O3SJBcIWlnh1fAs7hC0jcXpyDwtEQzujRN+9vUwQzgRGic7v29ggquwluu43sENclCHx8sQF Voi4o8SMe4fYQS6SEOCTuPFWEKKET2LStunMEGFeiY42IYhqbYndBzdATVSU2Pv9HtQ9HhJ7 L7QzQgLoKKPEr82PWSYwys9C8twsJJshbD2JG1OnsEHY8hLNW2czzwJaxywgLbH8HweEqSmx fpf+Aka2VYziqaXFuempxcZ5qeV6xYm5xaV56XrJ+bmbGIEp5vS/4193MK549VHvECMTB+Mh RgkOZiUR3nmp6ulCvCmJlVWpRfnxRaU5qcWHGKU5WJTEeVVT5FOFBNITS1KzU1MLUotgskwc nFINTPpK0w/9mtfLJO3wdb5tMHNxleS8xvcnurZct5LWLpqz9Qj/QVNPP98Hl9acCeP6mXWg 6OvVXuF4RXuvhi3c9vyF0UwefRrluid5fPQuHP5TKxa2ooRpm1fq1IPPOT9WP/JP/fyz5tiU QK+KR3utnkjtX+nlOOHhY+0Upb9Cq8/WyQhyss2V8n3xMK/C4JBn9dsl3qb+VQ6LX8nxbTqW uL/h4nnmAycLZ5YIdqk2LxZiUz2/6xYbc629mdrrqoRUw0Mbft74afVr2gr+V72Z79fWCzQ8 j563vn2XXFbhohsRkxSis/vz9GQWGP3v8eHri3F8YrTxWNk88WV8GyP2PWhrbGBPX+i0bxm3 rtc5JZbijERDLeai4kQAmcZaSaADAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpmkeLIzCtJLcpLzFFi42I5/e/4Pd3ccO10gwsPTCxW9Wxjsvj0P91i z6ydjA7MHkfvb2Ty2DnrLrtH35ZVjAHMUXo2RfmlJakKGfnFJbZK0YYWRnqGlhZ6RiaWeobG 5rFWRqZK+nY2Kak5mWWpRfp2CXoZOzcdZyz4b1xxadZc5gbG9xpdjJwcEgImEpeP3WfuYuTi EBJYyihx78YaFoiEosTc/e9ZIWxhiT/XuthAbCGB14wST6fHgtgsAioSz3YeZQKx2QTMJU6c nArWKwIU/9a9hxnEZhawkvg8cT4jiC0s4C3Rcfse0BwODl4BXYlFx3kg9h5llDh08i07SA2v gKDEyZlPWCB6dSR2br0DVs8sIC2x/B8HRFheonnrbLDxnAK2ElPfTWefwCg4C0n3LCTdsxC6 ZyHpXsDIsopRJLW0ODc9t9hQrzgxt7g0L10vOT93EyMwNrYd+7l5B+O8Vx/1DjEycTAeYpTg YFYS4Z2Xqp4uxJuSWFmVWpQfX1Sak1p8iNEUGBITmaVEk/OB0ZlXEm9oZmBqaGJmaWBqaWas JM7rdvl8mpBAemJJanZqakFqEUwfEwenVAOTUn7a3+LvNx+/+1L+9JHPd6ENVVtkbk4rmrrs Xcvu5K8uvlKXH53YvvFfdOnUGq9J5ke530wx8327r7tC+GPq7PjuO6nVbmtZ3b6bXYk5Jma+ tF3n16QJa1xUHO4xvOfeXhjw2carS3du1uRDOvs/dLjPzu+LjbqwpPzHrjdHplRNS7LoFK46 l3hmVb7Xl1crcwOPtypt6D43u7hah/XjnYk/fsloGJ4u+2/Xd4J5yf+yDSufRVc2HmJqyRVY 1JOjfeZZYa5ZTW/X1knm0/wSD6QxC+i71TgZuK8sPxso1l72obquwqFWRnx2xezKxVXtVk9c 1zgd3z0z+S+n6dbaqReXbk5szeHtT97/vVNMiaU4I9FQi7moOBEAx9S5LBYDAAA= X-CMS-MailID: 20241106114757eucas1p2532cfb7a1e113c54411298db4f72b69c X-Msg-Generator: CA X-RootMTR: 20241102085841eucas1p18073a29ca676e921a1ccb49dfa28d520 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20241102085841eucas1p18073a29ca676e921a1ccb49dfa28d520 References: <3ebcb202-d6e5-4368-9217-033345fa308a@samsung.com> <79e85c69-6fcb-4aff-86b4-84d186948f10@gmail.com> X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Hi, Jeff, Thank you for the review! All items were met, please find the comments and PATCH v2 in the message below: On Mon, Nov 04, 2024 at 04:48:31PM -0700, Jeff Law wrote: > > +      /* Trying to optimize: > > +     (zero_extend:M (subreg:N (not:M (X:M)))) -> > > +     (xor:M (zero_extend:M (subreg:N (X:M)), 0xffff)) > > +     where mask takes 0xffff bits of N mode bitsize. > "where the mask is GET_MODE_MASK (N)" is probably clearer to folks that have > been working on GCC for a while. GET_MODE_MASK is the bits set in mode N. > So for QI -> 0xff, HI would be 0xffff and so-on. Fixed comment to GET_MODE_MASK (N). Also, used the same macro to obtain the mask instead of ~0 << ... calculations. > > +     For the cases when X:M doesn't have any non-zero bits > > +     outside of mode N, (zero_extend:M (subreg:N (X:M)) > > +     will be simplified to just (X:M) > > +     and whole optimization will be -> (xor:M (X:M), 0xffff). */ > > +      if (GET_CODE (op) == SUBREG > Write this as "SUBREG_P (op)" Done > > +      && GET_CODE (XEXP (op, 0)) == NOT > > +      && GET_MODE (XEXP (op, 0)) == mode > > +      && GET_MODE (XEXP (XEXP (op, 0), 0)) == mode > I suspect the last mode check is redundant. We're not supposed to have the > argument of a code like NOT have a different mode than the code. Yep, all right. The operand of NOT should be in the same as operation itself mode. Also checked the logic for other NOT cases in simplify-rtx: there are no NOT operand's mode checks for all cases. So, removed the excess check. > > +      && (nonzero_bits (XEXP (XEXP (op, 0), 0), mode) > > +          & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (op, 0), 0)))) == 0) > Isn't GET_MODE (XEXP (XEXP (op, 0), 0)) the same as "mode"? Use the value > in the local variable, it's easier to read IMHO. Fixed > I suspect the formatting is off as well. We format conditionals like this: > > if (a > && b > && c) > > Note how the "&&" lines up under the first argument to the IF. This was the issue of my email client settings: it was intentionally replaced all tabs with spaces. This also, seem to the cause CI issues as well. Trying to use another client in plain text mode. > > +      { > > +    const uint64_t mask > > +      = ~((uint64_t)~0 << GET_MODE_BITSIZE (GET_MODE (op)).coeffs[0]); > Probably shouldn't be looking directly at .coeffs field. Instead there are > methods to convert that value to an integer. Look for the "to_constant ()" > method. so > GET_MODE_SIZE (GET_MODE (op)).to_constant () Replaced these calculations to mask = GET_MODE_MASK (N), so it's not needed anymore > > Note that this transformation may not work for modes with nonconstant sizes. > So you might need to check the is_constant () method. Missed it. Added in the last patch. > > +    return simplify_gen_binary (XOR, mode, > > +                    XEXP (XEXP (op, 0), 0), > > +                    gen_int_mode (mask, mode)); > Formatting looks goofy here too. > > Line up each argument under the argument in the prior line ie > > foo (XOR, mode > XEXP (XEXP (op, 0), 0) > get_int_mode (mask, mode)) The same issue of my email client. Fixed. -- >8 -- This patch adds optimization of the following patterns: (zero_extend:M (subreg:N (not:O==M (X:Q==M)))) -> (xor:M (zero_extend:M (subreg:N (X:M)), mask)) ... where the mask is GET_MODE_MASK (N). For the cases when X:M doesn't have any non-zero bits outside of mode N, (zero_extend:M (subreg:N (X:M)) could be simplified to just (X:M) and whole optimization will be: (zero_extend:M (subreg:N (not:M (X:M)))) -> (xor:M (X:M, mask)) Patch targets to handle code patterns like: not a0,a0 andi a0,a0,0xff to be optimized to: xori a0,a0,255 Change was locally tested for x86_64 and AArch64 (as most common) and for RV-64 and MIPS-32 targets (as having an effect from this optimization): no regressions for all cases. gcc/ChangeLog: * simplify-rtx.cc (simplify_context::simplify_unary_operation_1): Simplify ZERO_EXTEND (SUBREG (NOT X)) to XOR (X, GET_MODE_MASK(SUBREG)) when X doesn't have any non-zero bits outside of SUBREG mode. gcc/testsuite/ChangeLog: * gcc.target/riscv/pr112398.c: New test. Signed-off-by: Alexey Merzlyakov --- gcc/simplify-rtx.cc | 22 ++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/pr112398.c | 14 ++++++++++++++ 2 files changed, 36 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/pr112398.c diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc index a20a61c5ddd..e622d9554f1 100644 --- a/gcc/simplify-rtx.cc +++ b/gcc/simplify-rtx.cc @@ -1842,6 +1842,28 @@ simplify_context::simplify_unary_operation_1 (rtx_code code, machine_mode mode, & ~GET_MODE_MASK (op_mode)) == 0) return SUBREG_REG (op); + /* Trying to optimize: + (zero_extend:M (subreg:N (not:M (X:M)))) -> + (xor:M (zero_extend:M (subreg:N (X:M)), mask)) + where the mask is GET_MODE_MASK (N). + For the cases when X:M doesn't have any non-zero bits + outside of mode N, (zero_extend:M (subreg:N (X:M)) + will be simplified to just (X:M) + and whole optimization will be -> (xor:M (X:M, mask)). */ + if (SUBREG_P (op) + && GET_CODE (XEXP (op, 0)) == NOT + && GET_MODE (XEXP (op, 0)) == mode + && subreg_lowpart_p (op) + && GET_MODE_SIZE (GET_MODE (op)).is_constant () + && (nonzero_bits (XEXP (XEXP (op, 0), 0), mode) + & ~GET_MODE_MASK (mode)) == 0) + { + const uint64_t mask = GET_MODE_MASK (GET_MODE (op)); + return simplify_gen_binary (XOR, mode, + XEXP (XEXP (op, 0), 0), + gen_int_mode (mask, mode)); + } + #if defined(POINTERS_EXTEND_UNSIGNED) /* As we do not know which address space the pointer is referring to, we can do this only if the target does not support different pointer diff --git a/gcc/testsuite/gcc.target/riscv/pr112398.c b/gcc/testsuite/gcc.target/riscv/pr112398.c new file mode 100644 index 00000000000..624a665b76c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr112398.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ + +#include + +uint8_t neg_u8 (const uint8_t src) +{ + return ~src; +} + +/* { dg-final { scan-assembler-times "xori\t" 1 } } */ +/* { dg-final { scan-assembler-not "not\t" } } */ +/* { dg-final { scan-assembler-not "andi\t" } } */