From patchwork Wed Nov 6 10:26:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 2007401 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Xk1cH4MVmz1xyM for ; Wed, 6 Nov 2024 21:27:43 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CFEA53858414 for ; Wed, 6 Nov 2024 10:27:41 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id A71BD3858D37; Wed, 6 Nov 2024 10:27:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A71BD3858D37 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org A71BD3858D37 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1730888837; cv=none; b=c/gtK7WFsLYiD0TfcGXxi0RCYsUcn55Dk36RYiomKQwwnjOumytO4sdgaUpdTfaYwqSVraImolyB0ls3gR6fmya/lH15T/2Ad3/NluwzBH0mq5WVFe6/g4Rbhubr5qymFkWo06XOLE3jdpXeNj4l6Y6xNUKYD/JlIjfpbgYObCc= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1730888837; c=relaxed/simple; bh=EXC5nRKxoAH6Zy0poPosYcgLVz5P6LLApBIKgBWOfD0=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=OiIaVp/H2tL2F6EBS9BPvlSZCdhK063IYsRGiOVg/q1WUIvIXrdRNrCRUK9AmkA7qEF62YM0YML3cjyI1DRFq34YQXQMlu7hMOseWVxT4QnQ4oyp/2NxgHLjZ/gp5dQCJ/c5nB2GoMAkgNuwVtzjVU2nMosiy2YHvPJNB4epEuk= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2B14D1063; Wed, 6 Nov 2024 02:27:39 -0800 (PST) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 962BF3F66E; Wed, 6 Nov 2024 02:27:08 -0800 (PST) From: Richard Sandiford To: richard.earnshaw@arm.com, ktkachov@gcc.gnu.org, gcc-patches@gcc.gnu.org Cc: Richard Sandiford Subject: [PATCH 1/3] aarch64: Restrict FCLAMP to SME2 Date: Wed, 6 Nov 2024 10:26:39 +0000 Message-Id: <20241106102641.511909-2-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241106102641.511909-1-richard.sandiford@arm.com> References: <20241106102641.511909-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org There are two sets of patterns for FCLAMP: one set for single registers and one set for multiple registers. The multiple-register set was correctly gated on SME2, but the single-register set only required SME. This doesn't matter for ACLE usage, since the intrinsic definitions are correctly gated. But it does matter for automatic generation of FCLAMP from separate minimum and maximum operations (either ACLE intrinsics or autovectorised code). gcc/ * config/aarch64/aarch64-sve2.md (@aarch64_sve_fclamp) (*aarch64_sve_fclamp_x): Require TARGET_STREAMING_SME2 rather than TARGET_STREAMING_SME. gcc/testsuite/ * gcc.target/aarch64/sme/clamp_3.c: Force sme2 * gcc.target/aarch64/sme/clamp_4.c: Likewise. * gcc.target/aarch64/sme/clamp_5.c: New test. --- gcc/config/aarch64/aarch64-sve2.md | 4 ++-- .../gcc.target/aarch64/sme/clamp_3.c | 2 ++ .../gcc.target/aarch64/sme/clamp_4.c | 2 ++ .../gcc.target/aarch64/sme/clamp_5.c | 24 +++++++++++++++++++ 4 files changed, 30 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/sme/clamp_5.c diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md index 8047f405a17..08f83fc7ca0 100644 --- a/gcc/config/aarch64/aarch64-sve2.md +++ b/gcc/config/aarch64/aarch64-sve2.md @@ -1117,7 +1117,7 @@ (define_insn "@aarch64_sve_fclamp" UNSPEC_FMAXNM) (match_operand:SVE_FULL_F 3 "register_operand")] UNSPEC_FMINNM))] - "TARGET_STREAMING_SME" + "TARGET_STREAMING_SME2" {@ [cons: =0, 1, 2, 3; attrs: movprfx] [ w, %0, w, w; * ] fclamp\t%0., %2., %3. [ ?&w, w, w, w; yes ] movprfx\t%0, %1\;fclamp\t%0., %2., %3. @@ -1137,7 +1137,7 @@ (define_insn_and_split "*aarch64_sve_fclamp_x" UNSPEC_COND_FMAXNM) (match_operand:SVE_FULL_F 3 "register_operand")] UNSPEC_COND_FMINNM))] - "TARGET_STREAMING_SME" + "TARGET_STREAMING_SME2" {@ [cons: =0, 1, 2, 3; attrs: movprfx] [ w, %0, w, w; * ] # [ ?&w, w, w, w; yes ] # diff --git a/gcc/testsuite/gcc.target/aarch64/sme/clamp_3.c b/gcc/testsuite/gcc.target/aarch64/sme/clamp_3.c index 44959f79490..162de6224d5 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme/clamp_3.c +++ b/gcc/testsuite/gcc.target/aarch64/sme/clamp_3.c @@ -2,6 +2,8 @@ #include +#pragma GCC target "+sme2" + #define TEST(TYPE) \ TYPE \ tied1_##TYPE(TYPE a, TYPE b, TYPE c) __arm_streaming \ diff --git a/gcc/testsuite/gcc.target/aarch64/sme/clamp_4.c b/gcc/testsuite/gcc.target/aarch64/sme/clamp_4.c index 643b2635b90..453c82cd860 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme/clamp_4.c +++ b/gcc/testsuite/gcc.target/aarch64/sme/clamp_4.c @@ -2,6 +2,8 @@ #include +#pragma GCC target "+sme2" + #define TEST(TYPE) \ TYPE \ untied_##TYPE(TYPE a, TYPE b, TYPE c, TYPE d) __arm_streaming \ diff --git a/gcc/testsuite/gcc.target/aarch64/sme/clamp_5.c b/gcc/testsuite/gcc.target/aarch64/sme/clamp_5.c new file mode 100644 index 00000000000..7c5464bdc36 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme/clamp_5.c @@ -0,0 +1,24 @@ +// { dg-options "-O" } + +#include + +#pragma GCC target "+nosme2" + +#define TEST(TYPE) \ + TYPE \ + tied1_##TYPE(TYPE a, TYPE b, TYPE c) __arm_streaming \ + { \ + return svminnm_x(svptrue_b8(), svmaxnm_x(svptrue_b8(), a, b), c); \ + } \ + \ + TYPE \ + tied2_##TYPE(TYPE a, TYPE b, TYPE c) __arm_streaming \ + { \ + return svminnm_x(svptrue_b8(), svmaxnm_x(svptrue_b8(), b, a), c); \ + } + +TEST(svfloat16_t) +TEST(svfloat32_t) +TEST(svfloat64_t) + +/* { dg-final { scan-assembler-not {\tfclamp\t} } } */ From patchwork Wed Nov 6 10:26:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 2007403 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Xk1df0pH8z1xyW for ; Wed, 6 Nov 2024 21:28:54 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4B5063858403 for ; Wed, 6 Nov 2024 10:28:52 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 150F13858C60; Wed, 6 Nov 2024 10:27:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 150F13858C60 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 150F13858C60 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1730888843; cv=none; b=mTF7Y8YtBiiPnQQePGIgaoZ2K4ZsAlQ4/H9/kSOLbDPcnLu+RdbPkB6ZQ6LBIDMvMoUcT1KSaI3LsPE2QAvhjiYDkK5E7EgDYl+Rd5ZLz1rbVSpeP6qhP0Y2J3nipQOjCaz5hBev3I38V8XPcx/ix4C+PAxYfZdUGgEfx5pU694= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1730888843; c=relaxed/simple; bh=YxetCK2XxIAgt1G62bti1u4ycbNbw5GErgd8vwPAY7M=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=peQ3amtqaigzVyMimvX/hNHoKy/1i7h1JIV8Isu9hD40fUK2rpZoXU7lYxX3R39y95/aJY4Q8oSFLZhzm9pZXnbL7Xoqu44c3b5iafV63QlX1KMNJWmM9+rpPdACKNhwDuzZBcnMB1d+Y4BT4HJCEI06KKRkQ2a5o+qXvy9ItM8= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A73291063; Wed, 6 Nov 2024 02:27:50 -0800 (PST) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0871B3F66E; Wed, 6 Nov 2024 02:27:19 -0800 (PST) From: Richard Sandiford To: richard.earnshaw@arm.com, ktkachov@gcc.gnu.org, gcc-patches@gcc.gnu.org Cc: Richard Sandiford Subject: [PATCH 2/3] aarch64: Make PSEL dependent on SME rather than SME2 Date: Wed, 6 Nov 2024 10:26:40 +0000 Message-Id: <20241106102641.511909-3-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241106102641.511909-1-richard.sandiford@arm.com> References: <20241106102641.511909-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org The svpsel_lane intrinsics were wrongly classified as SME2+ only, rather than as base SME intrinsics. They should always be available in streaming mode. gcc/ * config/aarch64/aarch64-sve2.md (@aarch64_sve_psel) (*aarch64_sve_psel_plus): Require TARGET_STREAMING rather than TARGET_STREAMING_SME2. gcc/testsuite/ * gcc.target/aarch64/sme2/acle-asm/psel_lane_b16.c: Move to... * gcc.target/aarch64/sme/acle-asm/psel_lane_b16.c: ...here. * gcc.target/aarch64/sme2/acle-asm/psel_lane_b32.c: Move to... * gcc.target/aarch64/sme/acle-asm/psel_lane_b32.c: ...here. * gcc.target/aarch64/sme2/acle-asm/psel_lane_b64.c: Move to... * gcc.target/aarch64/sme/acle-asm/psel_lane_b64.c: ...here. * gcc.target/aarch64/sme2/acle-asm/psel_lane_b8.c: Move to... * gcc.target/aarch64/sme/acle-asm/psel_lane_b8.c: ...here. * gcc.target/aarch64/sme2/acle-asm/psel_lane_c16.c: Move to... * gcc.target/aarch64/sme/acle-asm/psel_lane_c16.c: ...here. * gcc.target/aarch64/sme2/acle-asm/psel_lane_c32.c: Move to... * gcc.target/aarch64/sme/acle-asm/psel_lane_c32.c: ...here. * gcc.target/aarch64/sme2/acle-asm/psel_lane_c64.c: Move to... * gcc.target/aarch64/sme/acle-asm/psel_lane_c64.c: ...here. * gcc.target/aarch64/sme2/acle-asm/psel_lane_c8.c: Move to... * gcc.target/aarch64/sme/acle-asm/psel_lane_c8.c: ...here. --- gcc/config/aarch64/aarch64-sve2.md | 4 ++-- .../gcc.target/aarch64/{sme2 => sme}/acle-asm/psel_lane_b16.c | 2 +- .../gcc.target/aarch64/{sme2 => sme}/acle-asm/psel_lane_b32.c | 2 +- .../gcc.target/aarch64/{sme2 => sme}/acle-asm/psel_lane_b64.c | 2 +- .../gcc.target/aarch64/{sme2 => sme}/acle-asm/psel_lane_b8.c | 2 +- .../gcc.target/aarch64/{sme2 => sme}/acle-asm/psel_lane_c16.c | 2 +- .../gcc.target/aarch64/{sme2 => sme}/acle-asm/psel_lane_c32.c | 2 +- .../gcc.target/aarch64/{sme2 => sme}/acle-asm/psel_lane_c64.c | 2 +- .../gcc.target/aarch64/{sme2 => sme}/acle-asm/psel_lane_c8.c | 2 +- 9 files changed, 10 insertions(+), 10 deletions(-) rename gcc/testsuite/gcc.target/aarch64/{sme2 => sme}/acle-asm/psel_lane_b16.c (98%) rename gcc/testsuite/gcc.target/aarch64/{sme2 => sme}/acle-asm/psel_lane_b32.c (98%) rename gcc/testsuite/gcc.target/aarch64/{sme2 => sme}/acle-asm/psel_lane_b64.c (98%) rename gcc/testsuite/gcc.target/aarch64/{sme2 => sme}/acle-asm/psel_lane_b8.c (98%) rename gcc/testsuite/gcc.target/aarch64/{sme2 => sme}/acle-asm/psel_lane_c16.c (98%) rename gcc/testsuite/gcc.target/aarch64/{sme2 => sme}/acle-asm/psel_lane_c32.c (98%) rename gcc/testsuite/gcc.target/aarch64/{sme2 => sme}/acle-asm/psel_lane_c64.c (98%) rename gcc/testsuite/gcc.target/aarch64/{sme2 => sme}/acle-asm/psel_lane_c8.c (98%) diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md index 08f83fc7ca0..ac27124fb74 100644 --- a/gcc/config/aarch64/aarch64-sve2.md +++ b/gcc/config/aarch64/aarch64-sve2.md @@ -418,7 +418,7 @@ (define_insn "@aarch64_sve_psel" (match_operand:SI 3 "register_operand" "Ucj") (const_int BHSD_BITS)] UNSPEC_PSEL))] - "TARGET_STREAMING_SME2" + "TARGET_STREAMING" "psel\t%0, %1, %2.[%w3, 0]" ) @@ -432,7 +432,7 @@ (define_insn "*aarch64_sve_psel_plus" (match_operand:SI 4 "const_int_operand")) (const_int BHSD_BITS)] UNSPEC_PSEL))] - "TARGET_STREAMING_SME2 + "TARGET_STREAMING && UINTVAL (operands[4]) < 128 / " "psel\t%0, %1, %2.[%w3, %4]" ) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/psel_lane_b16.c b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/psel_lane_b16.c similarity index 98% rename from gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/psel_lane_b16.c rename to gcc/testsuite/gcc.target/aarch64/sme/acle-asm/psel_lane_b16.c index 704e9e375f5..45dda808d2a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/psel_lane_b16.c +++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/psel_lane_b16.c @@ -1,6 +1,6 @@ /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ -#include "test_sme2_acle.h" +#include "test_sme_acle.h" /* ** psel_lane_p0_p2_p7_0: diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/psel_lane_b32.c b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/psel_lane_b32.c similarity index 98% rename from gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/psel_lane_b32.c rename to gcc/testsuite/gcc.target/aarch64/sme/acle-asm/psel_lane_b32.c index 7d9c7a129ea..d3d1b7b42ca 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/psel_lane_b32.c +++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/psel_lane_b32.c @@ -1,6 +1,6 @@ /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ -#include "test_sme2_acle.h" +#include "test_sme_acle.h" /* ** psel_lane_p0_p2_p7_0: diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/psel_lane_b64.c b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/psel_lane_b64.c similarity index 98% rename from gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/psel_lane_b64.c rename to gcc/testsuite/gcc.target/aarch64/sme/acle-asm/psel_lane_b64.c index a59032a57f6..8c1e014db65 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/psel_lane_b64.c +++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/psel_lane_b64.c @@ -1,6 +1,6 @@ /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ -#include "test_sme2_acle.h" +#include "test_sme_acle.h" /* ** psel_lane_p0_p2_p7_0: diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/psel_lane_b8.c b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/psel_lane_b8.c similarity index 98% rename from gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/psel_lane_b8.c rename to gcc/testsuite/gcc.target/aarch64/sme/acle-asm/psel_lane_b8.c index 0dea85c4f1f..aadfd3515ad 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/psel_lane_b8.c +++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/psel_lane_b8.c @@ -1,6 +1,6 @@ /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ -#include "test_sme2_acle.h" +#include "test_sme_acle.h" /* ** psel_lane_p0_p2_p7_0: diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/psel_lane_c16.c b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/psel_lane_c16.c similarity index 98% rename from gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/psel_lane_c16.c rename to gcc/testsuite/gcc.target/aarch64/sme/acle-asm/psel_lane_c16.c index 039c72b83c8..68c875eccf5 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/psel_lane_c16.c +++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/psel_lane_c16.c @@ -1,6 +1,6 @@ /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ -#include "test_sme2_acle.h" +#include "test_sme_acle.h" /* ** psel_lane_p0_p2_p7_0: diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/psel_lane_c32.c b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/psel_lane_c32.c similarity index 98% rename from gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/psel_lane_c32.c rename to gcc/testsuite/gcc.target/aarch64/sme/acle-asm/psel_lane_c32.c index eaf195d93d2..af044fb34ec 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/psel_lane_c32.c +++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/psel_lane_c32.c @@ -1,6 +1,6 @@ /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ -#include "test_sme2_acle.h" +#include "test_sme_acle.h" /* ** psel_lane_p0_p2_p7_0: diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/psel_lane_c64.c b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/psel_lane_c64.c similarity index 98% rename from gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/psel_lane_c64.c rename to gcc/testsuite/gcc.target/aarch64/sme/acle-asm/psel_lane_c64.c index 70cfeca4fc8..911336900b7 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/psel_lane_c64.c +++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/psel_lane_c64.c @@ -1,6 +1,6 @@ /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ -#include "test_sme2_acle.h" +#include "test_sme_acle.h" /* ** psel_lane_p0_p2_p7_0: diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/psel_lane_c8.c b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/psel_lane_c8.c similarity index 98% rename from gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/psel_lane_c8.c rename to gcc/testsuite/gcc.target/aarch64/sme/acle-asm/psel_lane_c8.c index b017962629f..31f95408a67 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/psel_lane_c8.c +++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/psel_lane_c8.c @@ -1,6 +1,6 @@ /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ -#include "test_sme2_acle.h" +#include "test_sme_acle.h" /* ** psel_lane_p0_p2_p7_0: From patchwork Wed Nov 6 10:26:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 2007402 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org 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server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0D9C01063; Wed, 6 Nov 2024 02:28:03 -0800 (PST) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F0DC13F66E; Wed, 6 Nov 2024 02:27:31 -0800 (PST) From: Richard Sandiford To: richard.earnshaw@arm.com, ktkachov@gcc.gnu.org, gcc-patches@gcc.gnu.org Cc: Richard Sandiford Subject: [PATCH 3/3] aarch64: Fix gcc.target/aarch64/sme2/acle-asm/bfmlslb_f32.c Date: Wed, 6 Nov 2024 10:26:41 +0000 Message-Id: <20241106102641.511909-4-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241106102641.511909-1-richard.sandiford@arm.com> References: <20241106102641.511909-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org I missed a search-and-replace on this test, meaning that it was duplicating bfmlalb_f32.c. gcc/testsuite/ * gcc.target/aarch64/sme2/acle-asm/bfmlslb_f32.c: Replace bfmla* with bfmls* --- .../aarch64/sme2/acle-asm/bfmlslb_f32.c | 60 +++++++++---------- 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bfmlslb_f32.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bfmlslb_f32.c index f67316cd33c..946af545141 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bfmlslb_f32.c +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bfmlslb_f32.c @@ -3,63 +3,63 @@ #include "test_sme2_acle.h" /* -** bfmlalb_f32_tied1: -** bfmlalb z0\.s, z4\.h, z5\.h +** bfmlslb_f32_tied1: +** bfmlslb z0\.s, z4\.h, z5\.h ** ret */ -TEST_DUAL_Z (bfmlalb_f32_tied1, svfloat32_t, svbfloat16_t, - z0 = svbfmlalb_f32 (z0, z4, z5), - z0 = svbfmlalb (z0, z4, z5)) +TEST_DUAL_Z (bfmlslb_f32_tied1, svfloat32_t, svbfloat16_t, + z0 = svbfmlslb_f32 (z0, z4, z5), + z0 = svbfmlslb (z0, z4, z5)) /* -** bfmlalb_f32_tied2: +** bfmlslb_f32_tied2: ** mov (z[0-9]+)\.d, z0\.d ** movprfx z0, z4 -** bfmlalb z0\.s, \1\.h, z1\.h +** bfmlslb z0\.s, \1\.h, z1\.h ** ret */ -TEST_DUAL_Z_REV (bfmlalb_f32_tied2, svfloat32_t, svbfloat16_t, - z0_res = svbfmlalb_f32 (z4, z0, z1), - z0_res = svbfmlalb (z4, z0, z1)) +TEST_DUAL_Z_REV (bfmlslb_f32_tied2, svfloat32_t, svbfloat16_t, + z0_res = svbfmlslb_f32 (z4, z0, z1), + z0_res = svbfmlslb (z4, z0, z1)) /* -** bfmlalb_f32_tied3: +** bfmlslb_f32_tied3: ** mov (z[0-9]+)\.d, z0\.d ** movprfx z0, z4 -** bfmlalb z0\.s, z1\.h, \1\.h +** bfmlslb z0\.s, z1\.h, \1\.h ** ret */ -TEST_DUAL_Z_REV (bfmlalb_f32_tied3, svfloat32_t, svbfloat16_t, - z0_res = svbfmlalb_f32 (z4, z1, z0), - z0_res = svbfmlalb (z4, z1, z0)) +TEST_DUAL_Z_REV (bfmlslb_f32_tied3, svfloat32_t, svbfloat16_t, + z0_res = svbfmlslb_f32 (z4, z1, z0), + z0_res = svbfmlslb (z4, z1, z0)) /* -** bfmlalb_f32_untied: +** bfmlslb_f32_untied: ** movprfx z0, z1 -** bfmlalb z0\.s, z4\.h, z5\.h +** bfmlslb z0\.s, z4\.h, z5\.h ** ret */ -TEST_DUAL_Z (bfmlalb_f32_untied, svfloat32_t, svbfloat16_t, - z0 = svbfmlalb_f32 (z1, z4, z5), - z0 = svbfmlalb (z1, z4, z5)) +TEST_DUAL_Z (bfmlslb_f32_untied, svfloat32_t, svbfloat16_t, + z0 = svbfmlslb_f32 (z1, z4, z5), + z0 = svbfmlslb (z1, z4, z5)) /* -** bfmlalb_h7_f32_tied1: +** bfmlslb_h7_f32_tied1: ** mov (z[0-9]+\.h), h7 -** bfmlalb z0\.s, z4\.h, \1 +** bfmlslb z0\.s, z4\.h, \1 ** ret */ -TEST_DUAL_ZD (bfmlalb_h7_f32_tied1, svfloat32_t, svbfloat16_t, bfloat16_t, - z0 = svbfmlalb_n_f32 (z0, z4, d7), - z0 = svbfmlalb (z0, z4, d7)) +TEST_DUAL_ZD (bfmlslb_h7_f32_tied1, svfloat32_t, svbfloat16_t, bfloat16_t, + z0 = svbfmlslb_n_f32 (z0, z4, d7), + z0 = svbfmlslb (z0, z4, d7)) /* -** bfmlalb_h7_f32_untied: +** bfmlslb_h7_f32_untied: ** mov (z[0-9]+\.h), h7 ** movprfx z0, z1 -** bfmlalb z0\.s, z4\.h, \1 +** bfmlslb z0\.s, z4\.h, \1 ** ret */ -TEST_DUAL_ZD (bfmlalb_h7_f32_untied, svfloat32_t, svbfloat16_t, bfloat16_t, - z0 = svbfmlalb_n_f32 (z1, z4, d7), - z0 = svbfmlalb (z1, z4, d7)) +TEST_DUAL_ZD (bfmlslb_h7_f32_untied, svfloat32_t, svbfloat16_t, bfloat16_t, + z0 = svbfmlslb_n_f32 (z1, z4, d7), + z0 = svbfmlslb (z1, z4, d7))