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The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Unlike other platforms, Ariane and OpenPiton enable all IRQs by default. This was described in commit b44e844880d0 ("Add support for Ariane FPGA SoC") as "due to some issue of the design." Add this wo [...] Content analysis details: (-2.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:62f listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Unlike other platforms, Ariane and OpenPiton enable all IRQs by default. This was described in commit b44e844880d0 ("Add support for Ariane FPGA SoC") as "due to some issue of the design." Add this workaround behind a flag in plic_warm_irqchip_init(), so every platform can use the same warm init function. Signed-off-by: Samuel Holland --- include/sbi_utils/irqchip/plic.h | 7 ++++--- lib/utils/irqchip/plic.c | 17 +++++++++++------ platform/fpga/ariane/platform.c | 25 +++---------------------- platform/fpga/openpiton/platform.c | 25 +++---------------------- 4 files changed, 21 insertions(+), 53 deletions(-) diff --git a/include/sbi_utils/irqchip/plic.h b/include/sbi_utils/irqchip/plic.h index 2eda6310..5da09055 100644 --- a/include/sbi_utils/irqchip/plic.h +++ b/include/sbi_utils/irqchip/plic.h @@ -16,8 +16,12 @@ struct plic_data { unsigned long addr; unsigned long size; unsigned long num_src; + unsigned long flags; }; +/** Work around a bug on Ariane that requires enabling interrupts at boot */ +#define PLIC_FLAG_ARIANE_BUG BIT(0) + /* So far, priorities on all consumers of these functions fit in 8 bits. */ void plic_priority_save(const struct plic_data *plic, u8 *priority, u32 num); @@ -30,9 +34,6 @@ void plic_context_save(const struct plic_data *plic, int context_id, void plic_context_restore(const struct plic_data *plic, int context_id, const u32 *enable, u32 threshold, u32 num); -int plic_context_init(const struct plic_data *plic, int context_id, - bool enable, u32 threshold); - int plic_warm_irqchip_init(const struct plic_data *plic, int m_cntx_id, int s_cntx_id); diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c index 193e3201..c66a6886 100644 --- a/lib/utils/irqchip/plic.c +++ b/lib/utils/irqchip/plic.c @@ -121,8 +121,8 @@ void plic_context_restore(const struct plic_data *plic, int context_id, plic_set_thresh(plic, context_id, threshold); } -int plic_context_init(const struct plic_data *plic, int context_id, - bool enable, u32 threshold) +static int plic_context_init(const struct plic_data *plic, int context_id, + bool enable, u32 threshold) { u32 ie_words, ie_value; @@ -143,18 +143,23 @@ int plic_context_init(const struct plic_data *plic, int context_id, int plic_warm_irqchip_init(const struct plic_data *plic, int m_cntx_id, int s_cntx_id) { + bool enable; int ret; - /* By default, disable all IRQs for M-mode of target HART */ + /* + * By default, disable all IRQs for the target HART. Ariane + * has a bug which requires enabling all interrupts at boot. + */ + enable = plic->flags & PLIC_FLAG_ARIANE_BUG; + if (m_cntx_id > -1) { - ret = plic_context_init(plic, m_cntx_id, false, 0x7); + ret = plic_context_init(plic, m_cntx_id, enable, 0x7); if (ret) return ret; } - /* By default, disable all IRQs for S-mode of target HART */ if (s_cntx_id > -1) { - ret = plic_context_init(plic, s_cntx_id, false, 0x7); + ret = plic_context_init(plic, s_cntx_id, enable, 0x7); if (ret) return ret; } diff --git a/platform/fpga/ariane/platform.c b/platform/fpga/ariane/platform.c index ec0584ab..b21d9ba9 100644 --- a/platform/fpga/ariane/platform.c +++ b/platform/fpga/ariane/platform.c @@ -39,6 +39,7 @@ static struct plic_data plic = { .addr = ARIANE_PLIC_ADDR, .size = ARIANE_PLIC_SIZE, .num_src = ARIANE_PLIC_NUM_SOURCES, + .flags = PLIC_FLAG_ARIANE_BUG, }; static struct aclint_mswi_data mswi = { @@ -93,27 +94,6 @@ static int ariane_final_init(bool cold_boot) return 0; } -static int plic_ariane_warm_irqchip_init(int m_cntx_id, int s_cntx_id) -{ - int ret; - - /* By default, enable all IRQs for M-mode of target HART */ - if (m_cntx_id > -1) { - ret = plic_context_init(&plic, m_cntx_id, true, 0x1); - if (ret) - return ret; - } - - /* Enable all IRQs for S-mode of target HART */ - if (s_cntx_id > -1) { - ret = plic_context_init(&plic, s_cntx_id, true, 0x0); - if (ret) - return ret; - } - - return 0; -} - /* * Initialize the ariane interrupt controller for current HART. */ @@ -127,7 +107,8 @@ static int ariane_irqchip_init(bool cold_boot) if (ret) return ret; } - return plic_ariane_warm_irqchip_init(2 * hartid, 2 * hartid + 1); + + return plic_warm_irqchip_init(&plic, 2 * hartid, 2 * hartid + 1); } /* diff --git a/platform/fpga/openpiton/platform.c b/platform/fpga/openpiton/platform.c index 81cc48f4..c1e84b61 100644 --- a/platform/fpga/openpiton/platform.c +++ b/platform/fpga/openpiton/platform.c @@ -43,6 +43,7 @@ static struct plic_data plic = { .addr = OPENPITON_DEFAULT_PLIC_ADDR, .size = OPENPITON_DEFAULT_PLIC_SIZE, .num_src = OPENPITON_DEFAULT_PLIC_NUM_SOURCES, + .flags = PLIC_FLAG_ARIANE_BUG, }; static struct aclint_mswi_data mswi = { @@ -124,27 +125,6 @@ static int openpiton_final_init(bool cold_boot) return 0; } -static int plic_openpiton_warm_irqchip_init(int m_cntx_id, int s_cntx_id) -{ - int ret; - - /* By default, enable all IRQs for M-mode of target HART */ - if (m_cntx_id > -1) { - ret = plic_context_init(&plic, m_cntx_id, true, 0x1); - if (ret) - return ret; - } - - /* Enable all IRQs for S-mode of target HART */ - if (s_cntx_id > -1) { - ret = plic_context_init(&plic, s_cntx_id, true, 0x0); - if (ret) - return ret; - } - - return 0; -} - /* * Initialize the openpiton interrupt controller for current HART. */ @@ -158,7 +138,8 @@ static int openpiton_irqchip_init(bool cold_boot) if (ret) return ret; } - return plic_openpiton_warm_irqchip_init(2 * hartid, 2 * hartid + 1); + + return plic_warm_irqchip_init(&plic, 2 * hartid, 2 * hartid + 1); } /* From patchwork Tue Nov 5 04:10:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 2006629 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Mon, 04 Nov 2024 20:10:18 -0800 (PST) From: Samuel Holland To: opensbi@lists.infradead.org Subject: [PATCH 2/9] lib: utils/irqchip: plic: Move delegation to base PLIC driver Date: Mon, 4 Nov 2024 20:10:03 -0800 Message-ID: <20241105041015.2949808-3-samuel.holland@sifive.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20241105041015.2949808-1-samuel.holland@sifive.com> References: <20241105041015.2949808-1-samuel.holland@sifive.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241104_201021_003801_9681C9BA X-CRM114-Status: GOOD ( 17.16 ) X-Spam-Score: -2.1 (--) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: This needs to be in the base PLIC driver as part of the power management save/restore flow. This is also in preparation for moving the PLIC information in the scratch area to the base PLIC driver. After that change, the FDT PLIC layer will be unable to look up the `struct plic_data` after co [...] Content analysis details: (-2.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:1036 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org This needs to be in the base PLIC driver as part of the power management save/restore flow. This is also in preparation for moving the PLIC information in the scratch area to the base PLIC driver. After that change, the FDT PLIC layer will be unable to look up the `struct plic_data` after cold boot. Signed-off-by: Samuel Holland --- include/sbi_utils/irqchip/plic.h | 4 ++++ lib/utils/irqchip/fdt_irqchip_plic.c | 16 +++------------- lib/utils/irqchip/plic.c | 11 +++++++++++ 3 files changed, 18 insertions(+), 13 deletions(-) diff --git a/include/sbi_utils/irqchip/plic.h b/include/sbi_utils/irqchip/plic.h index 5da09055..cbe66761 100644 --- a/include/sbi_utils/irqchip/plic.h +++ b/include/sbi_utils/irqchip/plic.h @@ -21,6 +21,8 @@ struct plic_data { /** Work around a bug on Ariane that requires enabling interrupts at boot */ #define PLIC_FLAG_ARIANE_BUG BIT(0) +/** PLIC must be delegated to S-mode like T-HEAD C906 and C910 */ +#define PLIC_FLAG_THEAD_DELEGATION BIT(1) /* So far, priorities on all consumers of these functions fit in 8 bits. */ void plic_priority_save(const struct plic_data *plic, u8 *priority, u32 num); @@ -28,6 +30,8 @@ void plic_priority_save(const struct plic_data *plic, u8 *priority, u32 num); void plic_priority_restore(const struct plic_data *plic, const u8 *priority, u32 num); +void plic_delegate(const struct plic_data *plic); + void plic_context_save(const struct plic_data *plic, int context_id, u32 *enable, u32 *threshold, u32 num); diff --git a/lib/utils/irqchip/fdt_irqchip_plic.c b/lib/utils/irqchip/fdt_irqchip_plic.c index a8aa4fcd..3c57a0f5 100644 --- a/lib/utils/irqchip/fdt_irqchip_plic.c +++ b/lib/utils/irqchip/fdt_irqchip_plic.c @@ -164,10 +164,7 @@ static int irqchip_plic_cold_init(const void *fdt, int nodeoff, if (rc) goto fail_free_data; - if (match->data) { - void (*plic_plat_init)(struct plic_data *) = match->data; - plic_plat_init(pd); - } + pd->flags = (unsigned long)match->data; rc = plic_cold_irqchip_init(pd); if (rc) @@ -184,19 +181,12 @@ fail_free_data: return rc; } -#define THEAD_PLIC_CTRL_REG 0x1ffffc - -static void thead_plic_plat_init(struct plic_data *pd) -{ - writel_relaxed(BIT(0), (char *)pd->addr + THEAD_PLIC_CTRL_REG); -} - void thead_plic_restore(void) { struct sbi_scratch *scratch = sbi_scratch_thishart_ptr(); struct plic_data *plic = plic_get_hart_data_ptr(scratch); - thead_plic_plat_init(plic); + plic_delegate(plic); } static const struct fdt_match irqchip_plic_match[] = { @@ -204,7 +194,7 @@ static const struct fdt_match irqchip_plic_match[] = { { .compatible = "riscv,plic0" }, { .compatible = "sifive,plic-1.0.0" }, { .compatible = "thead,c900-plic", - .data = thead_plic_plat_init }, + .data = (void *)PLIC_FLAG_THEAD_DELEGATION }, { /* sentinel */ } }; diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c index c66a6886..a432a8c4 100644 --- a/lib/utils/irqchip/plic.c +++ b/lib/utils/irqchip/plic.c @@ -24,6 +24,8 @@ #define PLIC_CONTEXT_BASE 0x200000 #define PLIC_CONTEXT_STRIDE 0x1000 +#define THEAD_PLIC_CTRL_REG 0x1ffffc + static u32 plic_get_priority(const struct plic_data *plic, u32 source) { volatile void *plic_priority = (char *)plic->addr + @@ -93,6 +95,13 @@ static void plic_set_ie(const struct plic_data *plic, u32 cntxid, writel(val, plic_ie); } +void plic_delegate(const struct plic_data *plic) +{ + /* If this is a T-HEAD PLIC, delegate access to S-mode */ + if (plic->flags & PLIC_FLAG_THEAD_DELEGATION) + writel_relaxed(BIT(0), (char *)plic->addr + THEAD_PLIC_CTRL_REG); +} + void plic_context_save(const struct plic_data *plic, int context_id, u32 *enable, u32 *threshold, u32 num) { @@ -178,6 +187,8 @@ int plic_cold_irqchip_init(const struct plic_data *plic) for (i = 1; i <= plic->num_src; i++) plic_set_priority(plic, i, 0); + plic_delegate(plic); + return sbi_domain_root_add_memrange(plic->addr, plic->size, BIT(20), (SBI_DOMAIN_MEMREGION_MMIO | SBI_DOMAIN_MEMREGION_SHARED_SURW_MRW)); From patchwork Tue Nov 5 04:10:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 2006628 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=3TRjM+Dn; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256 header.s=google header.b=PwbXmYEp; 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Mon, 04 Nov 2024 20:10:20 -0800 (PST) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e92fa0ea9bsm10759120a91.10.2024.11.04.20.10.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Nov 2024 20:10:19 -0800 (PST) From: Samuel Holland To: opensbi@lists.infradead.org Subject: [PATCH 3/9] lib: utils/irqchip: plic: Provide a hartindex to context map Date: Mon, 4 Nov 2024 20:10:04 -0800 Message-ID: <20241105041015.2949808-4-samuel.holland@sifive.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20241105041015.2949808-1-samuel.holland@sifive.com> References: <20241105041015.2949808-1-samuel.holland@sifive.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241104_201021_233830_D7E71E0A X-CRM114-Status: GOOD ( 17.72 ) X-Spam-Score: -2.1 (--) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: This removes platform-specific arguments to plic_warm_irqchip_init(), which makes the driver independent from the platform after cold init, and allows for further refactoring. Signed-off-by: Samuel Holland --- Content analysis details: (-2.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:52e listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org This removes platform-specific arguments to plic_warm_irqchip_init(), which makes the driver independent from the platform after cold init, and allows for further refactoring. Signed-off-by: Samuel Holland --- include/sbi_utils/irqchip/plic.h | 14 +++++-- lib/utils/irqchip/fdt_irqchip_plic.c | 62 +++++++--------------------- lib/utils/irqchip/plic.c | 14 +++++-- platform/fpga/ariane/platform.c | 6 ++- platform/fpga/openpiton/platform.c | 8 +++- platform/kendryte/k210/platform.c | 7 +++- platform/nuclei/ux600/platform.c | 7 ++-- platform/template/platform.c | 9 +++- 8 files changed, 62 insertions(+), 65 deletions(-) diff --git a/include/sbi_utils/irqchip/plic.h b/include/sbi_utils/irqchip/plic.h index cbe66761..e6b6f823 100644 --- a/include/sbi_utils/irqchip/plic.h +++ b/include/sbi_utils/irqchip/plic.h @@ -17,6 +17,7 @@ struct plic_data { unsigned long size; unsigned long num_src; unsigned long flags; + s16 context_map[][2]; }; /** Work around a bug on Ariane that requires enabling interrupts at boot */ @@ -24,6 +25,12 @@ struct plic_data { /** PLIC must be delegated to S-mode like T-HEAD C906 and C910 */ #define PLIC_FLAG_THEAD_DELEGATION BIT(1) +#define PLIC_M_CONTEXT 0 +#define PLIC_S_CONTEXT 1 + +#define PLIC_DATA_SIZE(__hart_count) (sizeof(struct plic_data) + \ + (__hart_count) * 2 * sizeof(s16)) + /* So far, priorities on all consumers of these functions fit in 8 bits. */ void plic_priority_save(const struct plic_data *plic, u8 *priority, u32 num); @@ -32,14 +39,13 @@ void plic_priority_restore(const struct plic_data *plic, const u8 *priority, void plic_delegate(const struct plic_data *plic); -void plic_context_save(const struct plic_data *plic, int context_id, +void plic_context_save(const struct plic_data *plic, bool smode, u32 *enable, u32 *threshold, u32 num); -void plic_context_restore(const struct plic_data *plic, int context_id, +void plic_context_restore(const struct plic_data *plic, bool smode, const u32 *enable, u32 threshold, u32 num); -int plic_warm_irqchip_init(const struct plic_data *plic, - int m_cntx_id, int s_cntx_id); +int plic_warm_irqchip_init(const struct plic_data *plic); int plic_cold_irqchip_init(const struct plic_data *plic); diff --git a/lib/utils/irqchip/fdt_irqchip_plic.c b/lib/utils/irqchip/fdt_irqchip_plic.c index 3c57a0f5..2ba56748 100644 --- a/lib/utils/irqchip/fdt_irqchip_plic.c +++ b/lib/utils/irqchip/fdt_irqchip_plic.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -25,22 +26,6 @@ static unsigned long plic_ptr_offset; #define plic_set_hart_data_ptr(__scratch, __plic) \ sbi_scratch_write_type((__scratch), void *, plic_ptr_offset, (__plic)) -static unsigned long plic_mcontext_offset; - -#define plic_get_hart_mcontext(__scratch) \ - (sbi_scratch_read_type((__scratch), long, plic_mcontext_offset) - 1) - -#define plic_set_hart_mcontext(__scratch, __mctx) \ - sbi_scratch_write_type((__scratch), long, plic_mcontext_offset, (__mctx) + 1) - -static unsigned long plic_scontext_offset; - -#define plic_get_hart_scontext(__scratch) \ - (sbi_scratch_read_type((__scratch), long, plic_scontext_offset) - 1) - -#define plic_set_hart_scontext(__scratch, __sctx) \ - sbi_scratch_write_type((__scratch), long, plic_scontext_offset, (__sctx) + 1) - void fdt_plic_priority_save(u8 *priority, u32 num) { struct sbi_scratch *scratch = sbi_scratch_thishart_ptr(); @@ -59,9 +44,7 @@ void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold, u32 num) { struct sbi_scratch *scratch = sbi_scratch_thishart_ptr(); - plic_context_save(plic_get_hart_data_ptr(scratch), - smode ? plic_get_hart_scontext(scratch) : - plic_get_hart_mcontext(scratch), + plic_context_save(plic_get_hart_data_ptr(scratch), smode, enable, threshold, num); } @@ -70,9 +53,7 @@ void fdt_plic_context_restore(bool smode, const u32 *enable, u32 threshold, { struct sbi_scratch *scratch = sbi_scratch_thishart_ptr(); - plic_context_restore(plic_get_hart_data_ptr(scratch), - smode ? plic_get_hart_scontext(scratch) : - plic_get_hart_mcontext(scratch), + plic_context_restore(plic_get_hart_data_ptr(scratch), smode, enable, threshold, num); } @@ -80,16 +61,14 @@ static int irqchip_plic_warm_init(void) { struct sbi_scratch *scratch = sbi_scratch_thishart_ptr(); - return plic_warm_irqchip_init(plic_get_hart_data_ptr(scratch), - plic_get_hart_mcontext(scratch), - plic_get_hart_scontext(scratch)); + return plic_warm_irqchip_init(plic_get_hart_data_ptr(scratch)); } -static int irqchip_plic_update_hartid_table(const void *fdt, int nodeoff, - struct plic_data *pd) +static int irqchip_plic_update_context_map(const void *fdt, int nodeoff, + struct plic_data *pd) { const fdt32_t *val; - u32 phandle, hwirq, hartid; + u32 phandle, hwirq, hartid, hartindex; struct sbi_scratch *scratch; int i, err, count, cpu_offset, cpu_intc_offset; @@ -114,17 +93,18 @@ static int irqchip_plic_update_hartid_table(const void *fdt, int nodeoff, if (err) continue; - scratch = sbi_hartid_to_scratch(hartid); + hartindex = sbi_hartid_to_hartindex(hartid); + scratch = sbi_hartindex_to_scratch(hartindex); if (!scratch) continue; plic_set_hart_data_ptr(scratch, pd); switch (hwirq) { case IRQ_M_EXT: - plic_set_hart_mcontext(scratch, i / 2); + pd->context_map[hartindex][PLIC_M_CONTEXT] = i / 2; break; case IRQ_S_EXT: - plic_set_hart_scontext(scratch, i / 2); + pd->context_map[hartindex][PLIC_S_CONTEXT] = i / 2; break; } } @@ -135,6 +115,8 @@ static int irqchip_plic_update_hartid_table(const void *fdt, int nodeoff, static int irqchip_plic_cold_init(const void *fdt, int nodeoff, const struct fdt_match *match) { + struct sbi_scratch *scratch = sbi_scratch_thishart_ptr(); + const struct sbi_platform *plat = sbi_platform_ptr(scratch); int rc; struct plic_data *pd; @@ -144,19 +126,7 @@ static int irqchip_plic_cold_init(const void *fdt, int nodeoff, return SBI_ENOMEM; } - if (!plic_mcontext_offset) { - plic_mcontext_offset = sbi_scratch_alloc_type_offset(long); - if (!plic_mcontext_offset) - return SBI_ENOMEM; - } - - if (!plic_scontext_offset) { - plic_scontext_offset = sbi_scratch_alloc_type_offset(long); - if (!plic_scontext_offset) - return SBI_ENOMEM; - } - - pd = sbi_zalloc(sizeof(*pd)); + pd = sbi_zalloc(PLIC_DATA_SIZE(plat->hart_count)); if (!pd) return SBI_ENOMEM; @@ -166,11 +136,11 @@ static int irqchip_plic_cold_init(const void *fdt, int nodeoff, pd->flags = (unsigned long)match->data; - rc = plic_cold_irqchip_init(pd); + rc = irqchip_plic_update_context_map(fdt, nodeoff, pd); if (rc) goto fail_free_data; - rc = irqchip_plic_update_hartid_table(fdt, nodeoff, pd); + rc = plic_cold_irqchip_init(pd); if (rc) goto fail_free_data; diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c index a432a8c4..c8ea8840 100644 --- a/lib/utils/irqchip/plic.c +++ b/lib/utils/irqchip/plic.c @@ -102,9 +102,11 @@ void plic_delegate(const struct plic_data *plic) writel_relaxed(BIT(0), (char *)plic->addr + THEAD_PLIC_CTRL_REG); } -void plic_context_save(const struct plic_data *plic, int context_id, +void plic_context_save(const struct plic_data *plic, bool smode, u32 *enable, u32 *threshold, u32 num) { + u32 hartindex = current_hartindex(); + s16 context_id = plic->context_map[hartindex][smode]; u32 ie_words = plic->num_src / 32 + 1; if (num > ie_words) @@ -116,9 +118,11 @@ void plic_context_save(const struct plic_data *plic, int context_id, *threshold = plic_get_thresh(plic, context_id); } -void plic_context_restore(const struct plic_data *plic, int context_id, +void plic_context_restore(const struct plic_data *plic, bool smode, const u32 *enable, u32 threshold, u32 num) { + u32 hartindex = current_hartindex(); + s16 context_id = plic->context_map[hartindex][smode]; u32 ie_words = plic->num_src / 32 + 1; if (num > ie_words) @@ -149,9 +153,11 @@ static int plic_context_init(const struct plic_data *plic, int context_id, return 0; } -int plic_warm_irqchip_init(const struct plic_data *plic, - int m_cntx_id, int s_cntx_id) +int plic_warm_irqchip_init(const struct plic_data *plic) { + u32 hartindex = current_hartindex(); + s16 m_cntx_id = plic->context_map[hartindex][PLIC_M_CONTEXT]; + s16 s_cntx_id = plic->context_map[hartindex][PLIC_S_CONTEXT]; bool enable; int ret; diff --git a/platform/fpga/ariane/platform.c b/platform/fpga/ariane/platform.c index b21d9ba9..79f6441f 100644 --- a/platform/fpga/ariane/platform.c +++ b/platform/fpga/ariane/platform.c @@ -40,6 +40,9 @@ static struct plic_data plic = { .size = ARIANE_PLIC_SIZE, .num_src = ARIANE_PLIC_NUM_SOURCES, .flags = PLIC_FLAG_ARIANE_BUG, + .context_map = { + [0] = { 0, 1 }, + }, }; static struct aclint_mswi_data mswi = { @@ -99,7 +102,6 @@ static int ariane_final_init(bool cold_boot) */ static int ariane_irqchip_init(bool cold_boot) { - u32 hartid = current_hartid(); int ret; if (cold_boot) { @@ -108,7 +110,7 @@ static int ariane_irqchip_init(bool cold_boot) return ret; } - return plic_warm_irqchip_init(&plic, 2 * hartid, 2 * hartid + 1); + return plic_warm_irqchip_init(&plic); } /* diff --git a/platform/fpga/openpiton/platform.c b/platform/fpga/openpiton/platform.c index c1e84b61..ae5b56c2 100644 --- a/platform/fpga/openpiton/platform.c +++ b/platform/fpga/openpiton/platform.c @@ -44,6 +44,11 @@ static struct plic_data plic = { .size = OPENPITON_DEFAULT_PLIC_SIZE, .num_src = OPENPITON_DEFAULT_PLIC_NUM_SOURCES, .flags = PLIC_FLAG_ARIANE_BUG, + .context_map = { + [0] = { 0, 1 }, + [1] = { 2, 3 }, + [2] = { 4, 5 }, + }, }; static struct aclint_mswi_data mswi = { @@ -130,7 +135,6 @@ static int openpiton_final_init(bool cold_boot) */ static int openpiton_irqchip_init(bool cold_boot) { - u32 hartid = current_hartid(); int ret; if (cold_boot) { @@ -139,7 +143,7 @@ static int openpiton_irqchip_init(bool cold_boot) return ret; } - return plic_warm_irqchip_init(&plic, 2 * hartid, 2 * hartid + 1); + return plic_warm_irqchip_init(&plic); } /* diff --git a/platform/kendryte/k210/platform.c b/platform/kendryte/k210/platform.c index 2f3f7079..fa175667 100644 --- a/platform/kendryte/k210/platform.c +++ b/platform/kendryte/k210/platform.c @@ -33,6 +33,10 @@ static struct plic_data plic = { .addr = K210_PLIC_BASE_ADDR, .size = K210_PLIC_BASE_SIZE, .num_src = K210_PLIC_NUM_SOURCES, + .context_map = { + [0] = { 0, 1 }, + [1] = { 2, 3 }, + }, }; static struct aclint_mswi_data mswi = { @@ -135,7 +139,6 @@ static int k210_final_init(bool cold_boot) static int k210_irqchip_init(bool cold_boot) { int rc; - u32 hartid = current_hartid(); if (cold_boot) { rc = plic_cold_irqchip_init(&plic); @@ -143,7 +146,7 @@ static int k210_irqchip_init(bool cold_boot) return rc; } - return plic_warm_irqchip_init(&plic, hartid * 2, hartid * 2 + 1); + return plic_warm_irqchip_init(&plic); } static int k210_ipi_init(bool cold_boot) diff --git a/platform/nuclei/ux600/platform.c b/platform/nuclei/ux600/platform.c index 5610e7c7..cca12ead 100644 --- a/platform/nuclei/ux600/platform.c +++ b/platform/nuclei/ux600/platform.c @@ -66,6 +66,9 @@ static struct plic_data plic = { .addr = UX600_PLIC_ADDR, .size = UX600_PLIC_SIZE, .num_src = UX600_PLIC_NUM_SOURCES, + .context_map = { + [0] = { 0, -1 }, + }, }; static struct aclint_mswi_data mswi = { @@ -190,7 +193,6 @@ static int ux600_final_init(bool cold_boot) static int ux600_irqchip_init(bool cold_boot) { int rc; - u32 hartid = current_hartid(); if (cold_boot) { rc = plic_cold_irqchip_init(&plic); @@ -198,8 +200,7 @@ static int ux600_irqchip_init(bool cold_boot) return rc; } - return plic_warm_irqchip_init(&plic, (hartid) ? (2 * hartid - 1) : 0, - (hartid) ? (2 * hartid) : -1); + return plic_warm_irqchip_init(&plic); } static int ux600_ipi_init(bool cold_boot) diff --git a/platform/template/platform.c b/platform/template/platform.c index b4d30a57..37674304 100644 --- a/platform/template/platform.c +++ b/platform/template/platform.c @@ -37,6 +37,12 @@ static struct plic_data plic = { .addr = PLATFORM_PLIC_ADDR, .size = PLATFORM_PLIC_SIZE, .num_src = PLATFORM_PLIC_NUM_SOURCES, + .context_map = { + [0] = { 0, 1 }, + [1] = { 2, 3 }, + [2] = { 4, 5 }, + [3] = { 6, 7 }, + }, }; static struct aclint_mswi_data mswi = { @@ -85,7 +91,6 @@ static int platform_final_init(bool cold_boot) */ static int platform_irqchip_init(bool cold_boot) { - u32 hartid = current_hartid(); int ret; /* Example if the generic PLIC driver is used */ @@ -95,7 +100,7 @@ static int platform_irqchip_init(bool cold_boot) return ret; } - return plic_warm_irqchip_init(&plic, 2 * hartid, 2 * hartid + 1); + return plic_warm_irqchip_init(&plic); } /* From patchwork Tue Nov 5 04:10:05 2024 Content-Type: text/plain; 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The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Move the PLIC save/restore functions inside the driver, so they can be reused on any platform that needs them. The memory needed to store the PLIC context is also allocated by the driver. The PM data [...] Content analysis details: (-2.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:52f listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Move the PLIC save/restore functions inside the driver, so they can be reused on any platform that needs them. The memory needed to store the PLIC context is also allocated by the driver. The PM data cannot be completely encapsulated, as some platforms (including Allwinner D1) need to program the IRQ enable status to a sideband interrupt controller for wakeup capability. Signed-off-by: Samuel Holland --- include/sbi_utils/irqchip/fdt_irqchip_plic.h | 22 +-- include/sbi_utils/irqchip/plic.h | 19 +-- lib/utils/irqchip/fdt_irqchip_plic.c | 32 +---- lib/utils/irqchip/plic.c | 134 ++++++++++++------- platform/generic/allwinner/sun20i-d1.c | 34 +---- 5 files changed, 112 insertions(+), 129 deletions(-) diff --git a/include/sbi_utils/irqchip/fdt_irqchip_plic.h b/include/sbi_utils/irqchip/fdt_irqchip_plic.h index df645dd0..fe769993 100644 --- a/include/sbi_utils/irqchip/fdt_irqchip_plic.h +++ b/include/sbi_utils/irqchip/fdt_irqchip_plic.h @@ -8,26 +8,12 @@ #define __IRQCHIP_FDT_IRQCHIP_PLIC_H__ #include +#include -/** - * Save the PLIC priority state - * @param priority pointer to the memory region for the saved priority - * @param num size of the memory region including interrupt source 0 - */ -void fdt_plic_priority_save(u8 *priority, u32 num); - -/** - * Restore the PLIC priority state - * @param priority pointer to the memory region for the saved priority - * @param num size of the memory region including interrupt source 0 - */ -void fdt_plic_priority_restore(const u8 *priority, u32 num); - -void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold, u32 num); +struct plic_data *fdt_plic_get(void); -void fdt_plic_context_restore(bool smode, const u32 *enable, u32 threshold, - u32 num); +void fdt_plic_suspend(void); -void thead_plic_restore(void); +void fdt_plic_resume(void); #endif diff --git a/include/sbi_utils/irqchip/plic.h b/include/sbi_utils/irqchip/plic.h index e6b6f823..29fe60c1 100644 --- a/include/sbi_utils/irqchip/plic.h +++ b/include/sbi_utils/irqchip/plic.h @@ -17,6 +17,7 @@ struct plic_data { unsigned long size; unsigned long num_src; unsigned long flags; + void *pm_data; s16 context_map[][2]; }; @@ -24,6 +25,8 @@ struct plic_data { #define PLIC_FLAG_ARIANE_BUG BIT(0) /** PLIC must be delegated to S-mode like T-HEAD C906 and C910 */ #define PLIC_FLAG_THEAD_DELEGATION BIT(1) +/** Allocate space for power management save/restore operations */ +#define PLIC_FLAG_ENABLE_PM BIT(2) #define PLIC_M_CONTEXT 0 #define PLIC_S_CONTEXT 1 @@ -31,22 +34,14 @@ struct plic_data { #define PLIC_DATA_SIZE(__hart_count) (sizeof(struct plic_data) + \ (__hart_count) * 2 * sizeof(s16)) -/* So far, priorities on all consumers of these functions fit in 8 bits. */ -void plic_priority_save(const struct plic_data *plic, u8 *priority, u32 num); +#define PLIC_IE_WORDS(__p) ((__p)->num_src / 32 + 1) -void plic_priority_restore(const struct plic_data *plic, const u8 *priority, - u32 num); +void plic_suspend(const struct plic_data *plic); -void plic_delegate(const struct plic_data *plic); - -void plic_context_save(const struct plic_data *plic, bool smode, - u32 *enable, u32 *threshold, u32 num); - -void plic_context_restore(const struct plic_data *plic, bool smode, - const u32 *enable, u32 threshold, u32 num); +void plic_resume(const struct plic_data *plic); int plic_warm_irqchip_init(const struct plic_data *plic); -int plic_cold_irqchip_init(const struct plic_data *plic); +int plic_cold_irqchip_init(struct plic_data *plic); #endif diff --git a/lib/utils/irqchip/fdt_irqchip_plic.c b/lib/utils/irqchip/fdt_irqchip_plic.c index 2ba56748..3826d2ae 100644 --- a/lib/utils/irqchip/fdt_irqchip_plic.c +++ b/lib/utils/irqchip/fdt_irqchip_plic.c @@ -26,35 +26,25 @@ static unsigned long plic_ptr_offset; #define plic_set_hart_data_ptr(__scratch, __plic) \ sbi_scratch_write_type((__scratch), void *, plic_ptr_offset, (__plic)) -void fdt_plic_priority_save(u8 *priority, u32 num) +struct plic_data *fdt_plic_get(void) { struct sbi_scratch *scratch = sbi_scratch_thishart_ptr(); - plic_priority_save(plic_get_hart_data_ptr(scratch), priority, num); + return plic_get_hart_data_ptr(scratch); } -void fdt_plic_priority_restore(const u8 *priority, u32 num) +void fdt_plic_suspend(void) { struct sbi_scratch *scratch = sbi_scratch_thishart_ptr(); - plic_priority_restore(plic_get_hart_data_ptr(scratch), priority, num); + plic_suspend(plic_get_hart_data_ptr(scratch)); } -void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold, u32 num) +void fdt_plic_resume(void) { struct sbi_scratch *scratch = sbi_scratch_thishart_ptr(); - plic_context_save(plic_get_hart_data_ptr(scratch), smode, - enable, threshold, num); -} - -void fdt_plic_context_restore(bool smode, const u32 *enable, u32 threshold, - u32 num) -{ - struct sbi_scratch *scratch = sbi_scratch_thishart_ptr(); - - plic_context_restore(plic_get_hart_data_ptr(scratch), smode, - enable, threshold, num); + plic_resume(plic_get_hart_data_ptr(scratch)); } static int irqchip_plic_warm_init(void) @@ -151,20 +141,12 @@ fail_free_data: return rc; } -void thead_plic_restore(void) -{ - struct sbi_scratch *scratch = sbi_scratch_thishart_ptr(); - struct plic_data *plic = plic_get_hart_data_ptr(scratch); - - plic_delegate(plic); -} - static const struct fdt_match irqchip_plic_match[] = { { .compatible = "andestech,nceplic100" }, { .compatible = "riscv,plic0" }, { .compatible = "sifive,plic-1.0.0" }, { .compatible = "thead,c900-plic", - .data = (void *)PLIC_FLAG_THEAD_DELEGATION }, + .data = (void *)(PLIC_FLAG_THEAD_DELEGATION | PLIC_FLAG_ENABLE_PM) }, { /* sentinel */ } }; diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c index c8ea8840..ab58e390 100644 --- a/lib/utils/irqchip/plic.c +++ b/lib/utils/irqchip/plic.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -40,19 +41,6 @@ static void plic_set_priority(const struct plic_data *plic, u32 source, u32 val) writel(val, plic_priority); } -void plic_priority_save(const struct plic_data *plic, u8 *priority, u32 num) -{ - for (u32 i = 1; i <= num; i++) - priority[i] = plic_get_priority(plic, i); -} - -void plic_priority_restore(const struct plic_data *plic, const u8 *priority, - u32 num) -{ - for (u32 i = 1; i <= num; i++) - plic_set_priority(plic, i, priority[i]); -} - static u32 plic_get_thresh(const struct plic_data *plic, u32 cntxid) { volatile void *plic_thresh; @@ -95,62 +83,91 @@ static void plic_set_ie(const struct plic_data *plic, u32 cntxid, writel(val, plic_ie); } -void plic_delegate(const struct plic_data *plic) +static void plic_delegate(const struct plic_data *plic) { /* If this is a T-HEAD PLIC, delegate access to S-mode */ if (plic->flags & PLIC_FLAG_THEAD_DELEGATION) writel_relaxed(BIT(0), (char *)plic->addr + THEAD_PLIC_CTRL_REG); } -void plic_context_save(const struct plic_data *plic, bool smode, - u32 *enable, u32 *threshold, u32 num) +static int plic_context_init(const struct plic_data *plic, int context_id, + bool enable, u32 threshold) { - u32 hartindex = current_hartindex(); - s16 context_id = plic->context_map[hartindex][smode]; - u32 ie_words = plic->num_src / 32 + 1; + u32 ie_words, ie_value; - if (num > ie_words) - num = ie_words; + if (!plic || context_id < 0) + return SBI_EINVAL; - for (u32 i = 0; i < num; i++) - enable[i] = plic_get_ie(plic, context_id, i); + ie_words = PLIC_IE_WORDS(plic); + ie_value = enable ? 0xffffffffU : 0U; + + for (u32 i = 0; i < ie_words; i++) + plic_set_ie(plic, context_id, i, ie_value); + + plic_set_thresh(plic, context_id, threshold); - *threshold = plic_get_thresh(plic, context_id); + return 0; } -void plic_context_restore(const struct plic_data *plic, bool smode, - const u32 *enable, u32 threshold, u32 num) +void plic_suspend(const struct plic_data *plic) { - u32 hartindex = current_hartindex(); - s16 context_id = plic->context_map[hartindex][smode]; - u32 ie_words = plic->num_src / 32 + 1; + u32 ie_words = PLIC_IE_WORDS(plic); + u32 *data_word = plic->pm_data; + u8 *data_byte; - if (num > ie_words) - num = ie_words; + if (!data_word) + return; - for (u32 i = 0; i < num; i++) - plic_set_ie(plic, context_id, i, enable[i]); + for (u32 h = 0; h <= sbi_scratch_last_hartindex(); h++) { + u32 context_id = plic->context_map[h][PLIC_S_CONTEXT]; - plic_set_thresh(plic, context_id, threshold); + if (context_id < 0) + continue; + + /* Save the enable bits */ + for (u32 i = 0; i < ie_words; i++) + *data_word++ = plic_get_ie(plic, context_id, i); + + /* Save the context threshold */ + *data_word++ = plic_get_thresh(plic, context_id); + } + + /* Restore the input priorities */ + data_byte = (u8 *)data_word; + for (u32 i = 1; i <= plic->num_src; i++) + *data_byte++ = plic_get_priority(plic, i); } -static int plic_context_init(const struct plic_data *plic, int context_id, - bool enable, u32 threshold) +void plic_resume(const struct plic_data *plic) { - u32 ie_words, ie_value; + u32 ie_words = PLIC_IE_WORDS(plic); + u32 *data_word = plic->pm_data; + u8 *data_byte; - if (!plic || context_id < 0) - return SBI_EINVAL; + if (!data_word) + return; - ie_words = plic->num_src / 32 + 1; - ie_value = enable ? 0xffffffffU : 0U; + for (u32 h = 0; h <= sbi_scratch_last_hartindex(); h++) { + u32 context_id = plic->context_map[h][PLIC_S_CONTEXT]; - for (u32 i = 0; i < ie_words; i++) - plic_set_ie(plic, context_id, i, ie_value); + if (context_id < 0) + continue; - plic_set_thresh(plic, context_id, threshold); + /* Restore the enable bits */ + for (u32 i = 0; i < ie_words; i++) + plic_set_ie(plic, context_id, i, *data_word++); - return 0; + /* Restore the context threshold */ + plic_set_thresh(plic, context_id, *data_word++); + } + + /* Restore the input priorities */ + data_byte = (u8 *)data_word; + for (u32 i = 1; i <= plic->num_src; i++) + plic_set_priority(plic, i, *data_byte++); + + /* Restore the delegation */ + plic_delegate(plic); } int plic_warm_irqchip_init(const struct plic_data *plic) @@ -182,13 +199,38 @@ int plic_warm_irqchip_init(const struct plic_data *plic) return 0; } -int plic_cold_irqchip_init(const struct plic_data *plic) +int plic_cold_irqchip_init(struct plic_data *plic) { int i; if (!plic) return SBI_EINVAL; + if (plic->flags & PLIC_FLAG_ENABLE_PM) { + unsigned long data_size = 0; + + for (u32 i = 0; i <= sbi_scratch_last_hartindex(); i++) { + if (plic->context_map[i][PLIC_S_CONTEXT] < 0) + continue; + + /* Allocate space for enable bits */ + data_size += (plic->num_src / 32 + 1) * sizeof(u32); + + /* Allocate space for the context threshold */ + data_size += sizeof(u32); + } + + /* + * Allocate space for the input priorities. So far, + * priorities on all known implementations fit in 8 bits. + */ + data_size += plic->num_src * sizeof(u8); + + plic->pm_data = sbi_malloc(data_size); + if (!plic->pm_data) + return SBI_ENOMEM; + } + /* Configure default priorities of all IRQs */ for (i = 1; i <= plic->num_src; i++) plic_set_priority(plic, i, 0); diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c index 9b1d5559..c4b06d1a 100644 --- a/platform/generic/allwinner/sun20i-d1.c +++ b/platform/generic/allwinner/sun20i-d1.c @@ -60,31 +60,6 @@ static void sun20i_d1_csr_restore(void) csr_write(THEAD_C9XX_CSR_MHINT, csr_mhint); } -/* - * PLIC - */ - -#define PLIC_SOURCES 175 -#define PLIC_IE_WORDS (PLIC_SOURCES / 32 + 1) - -static u8 plic_priority[1 + PLIC_SOURCES]; -static u32 plic_sie[PLIC_IE_WORDS]; -static u32 plic_threshold; - -static void sun20i_d1_plic_save(void) -{ - fdt_plic_context_save(true, plic_sie, &plic_threshold, PLIC_IE_WORDS); - fdt_plic_priority_save(plic_priority, PLIC_SOURCES); -} - -static void sun20i_d1_plic_restore(void) -{ - thead_plic_restore(); - fdt_plic_priority_restore(plic_priority, PLIC_SOURCES); - fdt_plic_context_restore(true, plic_sie, plic_threshold, - PLIC_IE_WORDS); -} - /* * PPU */ @@ -117,6 +92,9 @@ static void sun20i_d1_ppu_restore(void) static void sun20i_d1_riscv_cfg_save(void) { + struct plic_data *plic = fdt_plic_get(); + u32 *plic_sie = plic->pm_data; + /* Enable MMIO access. Do not assume S-mode leaves the clock enabled. */ writel_relaxed(CCU_BGR_ENABLE, SUN20I_D1_CCU_BASE + RISCV_CFG_BGR_REG); @@ -126,7 +104,7 @@ static void sun20i_d1_riscv_cfg_save(void) * the wakeup mask registers (the offset is for GIC compatibility). So * copying SIE to the wakeup mask needs some bit manipulation. */ - for (int i = 0; i < PLIC_IE_WORDS - 1; i++) + for (int i = 0; i < PLIC_IE_WORDS(plic) - 1; i++) writel_relaxed(plic_sie[i] >> 16 | plic_sie[i + 1] << 16, SUN20I_D1_RISCV_CFG_BASE + WAKEUP_MASK_REG(i)); @@ -158,7 +136,7 @@ static int sun20i_d1_hart_suspend(u32 suspend_type) if (!(suspend_type & SBI_HSM_SUSP_NON_RET_BIT)) return SBI_ENOTSUPP; - sun20i_d1_plic_save(); + fdt_plic_suspend(); sun20i_d1_ppu_save(); sun20i_d1_riscv_cfg_save(); sun20i_d1_csr_save(); @@ -178,7 +156,7 @@ static void sun20i_d1_hart_resume(void) sun20i_d1_csr_restore(); sun20i_d1_riscv_cfg_restore(); sun20i_d1_ppu_restore(); - sun20i_d1_plic_restore(); + fdt_plic_resume(); } static const struct sbi_hsm_device sun20i_d1_ppu = { From patchwork Tue Nov 5 04:10:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 2006631 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Mon, 04 Nov 2024 20:10:21 -0800 (PST) From: Samuel Holland To: opensbi@lists.infradead.org Subject: [PATCH 5/9] lib: utils/irqchip: Move per-hart data from fdt_plic to plic Date: Mon, 4 Nov 2024 20:10:06 -0800 Message-ID: <20241105041015.2949808-6-samuel.holland@sifive.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20241105041015.2949808-1-samuel.holland@sifive.com> References: <20241105041015.2949808-1-samuel.holland@sifive.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241104_201023_547457_06691FDB X-CRM114-Status: GOOD ( 22.36 ) X-Spam-Score: -2.1 (--) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: The per-hart PLIC pointer is not really specific to FDT platforms. Move it into the main driver and drop the extra wrapper functions. Signed-off-by: Samuel Holland --- include/sbi_utils/irqchip/fdt_irqchip_plic.h | 19 -------- include/sbi_utils/irqchip/plic.h | 8 ++-- lib/utils/irqchip/fdt_irqchip_plic.c | 49 + lib/utils/irqchip/plic.c | 49 +++++ [...] Content analysis details: (-2.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:1029 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org The per-hart PLIC pointer is not really specific to FDT platforms. Move it into the main driver and drop the extra wrapper functions. Signed-off-by: Samuel Holland --- include/sbi_utils/irqchip/fdt_irqchip_plic.h | 19 -------- include/sbi_utils/irqchip/plic.h | 8 ++-- lib/utils/irqchip/fdt_irqchip_plic.c | 49 +------------------- lib/utils/irqchip/plic.c | 49 ++++++++++++++++++-- platform/fpga/ariane/platform.c | 2 +- platform/fpga/openpiton/platform.c | 2 +- platform/generic/allwinner/sun20i-d1.c | 8 ++-- platform/kendryte/k210/platform.c | 2 +- platform/nuclei/ux600/platform.c | 2 +- platform/template/platform.c | 2 +- 10 files changed, 60 insertions(+), 83 deletions(-) delete mode 100644 include/sbi_utils/irqchip/fdt_irqchip_plic.h diff --git a/include/sbi_utils/irqchip/fdt_irqchip_plic.h b/include/sbi_utils/irqchip/fdt_irqchip_plic.h deleted file mode 100644 index fe769993..00000000 --- a/include/sbi_utils/irqchip/fdt_irqchip_plic.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * SPDX-License-Identifier: BSD-2-Clause - * - * Copyright (c) 2022 Samuel Holland - */ - -#ifndef __IRQCHIP_FDT_IRQCHIP_PLIC_H__ -#define __IRQCHIP_FDT_IRQCHIP_PLIC_H__ - -#include -#include - -struct plic_data *fdt_plic_get(void); - -void fdt_plic_suspend(void); - -void fdt_plic_resume(void); - -#endif diff --git a/include/sbi_utils/irqchip/plic.h b/include/sbi_utils/irqchip/plic.h index 29fe60c1..5c638e14 100644 --- a/include/sbi_utils/irqchip/plic.h +++ b/include/sbi_utils/irqchip/plic.h @@ -36,11 +36,13 @@ struct plic_data { #define PLIC_IE_WORDS(__p) ((__p)->num_src / 32 + 1) -void plic_suspend(const struct plic_data *plic); +struct plic_data *plic_get(void); -void plic_resume(const struct plic_data *plic); +void plic_suspend(void); -int plic_warm_irqchip_init(const struct plic_data *plic); +void plic_resume(void); + +int plic_warm_irqchip_init(void); int plic_cold_irqchip_init(struct plic_data *plic); diff --git a/lib/utils/irqchip/fdt_irqchip_plic.c b/lib/utils/irqchip/fdt_irqchip_plic.c index 3826d2ae..ebde7eec 100644 --- a/lib/utils/irqchip/fdt_irqchip_plic.c +++ b/lib/utils/irqchip/fdt_irqchip_plic.c @@ -18,48 +18,11 @@ #include #include -static unsigned long plic_ptr_offset; - -#define plic_get_hart_data_ptr(__scratch) \ - sbi_scratch_read_type((__scratch), void *, plic_ptr_offset) - -#define plic_set_hart_data_ptr(__scratch, __plic) \ - sbi_scratch_write_type((__scratch), void *, plic_ptr_offset, (__plic)) - -struct plic_data *fdt_plic_get(void) -{ - struct sbi_scratch *scratch = sbi_scratch_thishart_ptr(); - - return plic_get_hart_data_ptr(scratch); -} - -void fdt_plic_suspend(void) -{ - struct sbi_scratch *scratch = sbi_scratch_thishart_ptr(); - - plic_suspend(plic_get_hart_data_ptr(scratch)); -} - -void fdt_plic_resume(void) -{ - struct sbi_scratch *scratch = sbi_scratch_thishart_ptr(); - - plic_resume(plic_get_hart_data_ptr(scratch)); -} - -static int irqchip_plic_warm_init(void) -{ - struct sbi_scratch *scratch = sbi_scratch_thishart_ptr(); - - return plic_warm_irqchip_init(plic_get_hart_data_ptr(scratch)); -} - static int irqchip_plic_update_context_map(const void *fdt, int nodeoff, struct plic_data *pd) { const fdt32_t *val; u32 phandle, hwirq, hartid, hartindex; - struct sbi_scratch *scratch; int i, err, count, cpu_offset, cpu_intc_offset; val = fdt_getprop(fdt, nodeoff, "interrupts-extended", &count); @@ -84,11 +47,9 @@ static int irqchip_plic_update_context_map(const void *fdt, int nodeoff, continue; hartindex = sbi_hartid_to_hartindex(hartid); - scratch = sbi_hartindex_to_scratch(hartindex); - if (!scratch) + if (hartindex == -1U) continue; - plic_set_hart_data_ptr(scratch, pd); switch (hwirq) { case IRQ_M_EXT: pd->context_map[hartindex][PLIC_M_CONTEXT] = i / 2; @@ -110,12 +71,6 @@ static int irqchip_plic_cold_init(const void *fdt, int nodeoff, int rc; struct plic_data *pd; - if (!plic_ptr_offset) { - plic_ptr_offset = sbi_scratch_alloc_type_offset(void *); - if (!plic_ptr_offset) - return SBI_ENOMEM; - } - pd = sbi_zalloc(PLIC_DATA_SIZE(plat->hart_count)); if (!pd) return SBI_ENOMEM; @@ -153,6 +108,6 @@ static const struct fdt_match irqchip_plic_match[] = { struct fdt_irqchip fdt_irqchip_plic = { .match_table = irqchip_plic_match, .cold_init = irqchip_plic_cold_init, - .warm_init = irqchip_plic_warm_init, + .warm_init = plic_warm_irqchip_init, .exit = NULL, }; diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c index ab58e390..ca506c4c 100644 --- a/lib/utils/irqchip/plic.c +++ b/lib/utils/irqchip/plic.c @@ -27,6 +27,21 @@ #define THEAD_PLIC_CTRL_REG 0x1ffffc +static unsigned long plic_ptr_offset; + +#define plic_get_hart_data_ptr(__scratch) \ + sbi_scratch_read_type((__scratch), void *, plic_ptr_offset) + +#define plic_set_hart_data_ptr(__scratch, __plic) \ + sbi_scratch_write_type((__scratch), void *, plic_ptr_offset, (__plic)) + +struct plic_data *plic_get(void) +{ + struct sbi_scratch *scratch = sbi_scratch_thishart_ptr(); + + return plic_get_hart_data_ptr(scratch); +} + static u32 plic_get_priority(const struct plic_data *plic, u32 source) { volatile void *plic_priority = (char *)plic->addr + @@ -109,8 +124,10 @@ static int plic_context_init(const struct plic_data *plic, int context_id, return 0; } -void plic_suspend(const struct plic_data *plic) +void plic_suspend(void) { + struct sbi_scratch *scratch = sbi_scratch_thishart_ptr(); + const struct plic_data *plic = plic_get_hart_data_ptr(scratch); u32 ie_words = PLIC_IE_WORDS(plic); u32 *data_word = plic->pm_data; u8 *data_byte; @@ -138,8 +155,10 @@ void plic_suspend(const struct plic_data *plic) *data_byte++ = plic_get_priority(plic, i); } -void plic_resume(const struct plic_data *plic) +void plic_resume(void) { + struct sbi_scratch *scratch = sbi_scratch_thishart_ptr(); + const struct plic_data *plic = plic_get_hart_data_ptr(scratch); u32 ie_words = PLIC_IE_WORDS(plic); u32 *data_word = plic->pm_data; u8 *data_byte; @@ -170,8 +189,10 @@ void plic_resume(const struct plic_data *plic) plic_delegate(plic); } -int plic_warm_irqchip_init(const struct plic_data *plic) +int plic_warm_irqchip_init(void) { + struct sbi_scratch *scratch = sbi_scratch_thishart_ptr(); + const struct plic_data *plic = plic_get_hart_data_ptr(scratch); u32 hartindex = current_hartindex(); s16 m_cntx_id = plic->context_map[hartindex][PLIC_M_CONTEXT]; s16 s_cntx_id = plic->context_map[hartindex][PLIC_S_CONTEXT]; @@ -201,11 +222,17 @@ int plic_warm_irqchip_init(const struct plic_data *plic) int plic_cold_irqchip_init(struct plic_data *plic) { - int i; + int i, ret; if (!plic) return SBI_EINVAL; + if (!plic_ptr_offset) { + plic_ptr_offset = sbi_scratch_alloc_type_offset(void *); + if (!plic_ptr_offset) + return SBI_ENOMEM; + } + if (plic->flags & PLIC_FLAG_ENABLE_PM) { unsigned long data_size = 0; @@ -237,7 +264,19 @@ int plic_cold_irqchip_init(struct plic_data *plic) plic_delegate(plic); - return sbi_domain_root_add_memrange(plic->addr, plic->size, BIT(20), + ret = sbi_domain_root_add_memrange(plic->addr, plic->size, BIT(20), (SBI_DOMAIN_MEMREGION_MMIO | SBI_DOMAIN_MEMREGION_SHARED_SURW_MRW)); + if (ret) + return ret; + + for (u32 i = 0; i <= sbi_scratch_last_hartindex(); i++) { + if (plic->context_map[i][PLIC_M_CONTEXT] < 0 && + plic->context_map[i][PLIC_S_CONTEXT] < 0) + continue; + + plic_set_hart_data_ptr(sbi_hartindex_to_scratch(i), plic); + } + + return 0; } diff --git a/platform/fpga/ariane/platform.c b/platform/fpga/ariane/platform.c index 79f6441f..c4ac0ae6 100644 --- a/platform/fpga/ariane/platform.c +++ b/platform/fpga/ariane/platform.c @@ -110,7 +110,7 @@ static int ariane_irqchip_init(bool cold_boot) return ret; } - return plic_warm_irqchip_init(&plic); + return plic_warm_irqchip_init(); } /* diff --git a/platform/fpga/openpiton/platform.c b/platform/fpga/openpiton/platform.c index ae5b56c2..73429f88 100644 --- a/platform/fpga/openpiton/platform.c +++ b/platform/fpga/openpiton/platform.c @@ -143,7 +143,7 @@ static int openpiton_irqchip_init(bool cold_boot) return ret; } - return plic_warm_irqchip_init(&plic); + return plic_warm_irqchip_init(); } /* diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c index c4b06d1a..b65013c2 100644 --- a/platform/generic/allwinner/sun20i-d1.c +++ b/platform/generic/allwinner/sun20i-d1.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #define SUN20I_D1_CCU_BASE ((void *)0x02001000) #define SUN20I_D1_RISCV_CFG_BASE ((void *)0x06010000) @@ -92,7 +92,7 @@ static void sun20i_d1_ppu_restore(void) static void sun20i_d1_riscv_cfg_save(void) { - struct plic_data *plic = fdt_plic_get(); + struct plic_data *plic = plic_get(); u32 *plic_sie = plic->pm_data; /* Enable MMIO access. Do not assume S-mode leaves the clock enabled. */ @@ -136,7 +136,7 @@ static int sun20i_d1_hart_suspend(u32 suspend_type) if (!(suspend_type & SBI_HSM_SUSP_NON_RET_BIT)) return SBI_ENOTSUPP; - fdt_plic_suspend(); + plic_suspend(); sun20i_d1_ppu_save(); sun20i_d1_riscv_cfg_save(); sun20i_d1_csr_save(); @@ -156,7 +156,7 @@ static void sun20i_d1_hart_resume(void) sun20i_d1_csr_restore(); sun20i_d1_riscv_cfg_restore(); sun20i_d1_ppu_restore(); - fdt_plic_resume(); + plic_resume(); } static const struct sbi_hsm_device sun20i_d1_ppu = { diff --git a/platform/kendryte/k210/platform.c b/platform/kendryte/k210/platform.c index fa175667..e1808d17 100644 --- a/platform/kendryte/k210/platform.c +++ b/platform/kendryte/k210/platform.c @@ -146,7 +146,7 @@ static int k210_irqchip_init(bool cold_boot) return rc; } - return plic_warm_irqchip_init(&plic); + return plic_warm_irqchip_init(); } static int k210_ipi_init(bool cold_boot) diff --git a/platform/nuclei/ux600/platform.c b/platform/nuclei/ux600/platform.c index cca12ead..12657bc0 100644 --- a/platform/nuclei/ux600/platform.c +++ b/platform/nuclei/ux600/platform.c @@ -200,7 +200,7 @@ static int ux600_irqchip_init(bool cold_boot) return rc; } - return plic_warm_irqchip_init(&plic); + return plic_warm_irqchip_init(); } static int ux600_ipi_init(bool cold_boot) diff --git a/platform/template/platform.c b/platform/template/platform.c index 37674304..298301a4 100644 --- a/platform/template/platform.c +++ b/platform/template/platform.c @@ -100,7 +100,7 @@ static int platform_irqchip_init(bool cold_boot) return ret; } - return plic_warm_irqchip_init(&plic); + return plic_warm_irqchip_init(); } /* From patchwork Tue Nov 5 04:10:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 2006626 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=vvMCBSd2; dkim=fail reason="signature verification failed" (2048-bit key; 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The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Have the SBI irqchip core keep track of registered irqchip devices. This is useful for any callbacks the irqchip driver may have, such as for warm initialization, the external interrupt handler functi [...] Content analysis details: (-2.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:102b listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Have the SBI irqchip core keep track of registered irqchip devices. This is useful for any callbacks the irqchip driver may have, such as for warm initialization, the external interrupt handler function, and any future support for handling external interrupts (beyond IPIs) in M-mode. This improves on the tracking done in fdt_irqchip.c, as it tracks device instances, not just drivers, so callbacks can target a specific device. Signed-off-by: Samuel Holland --- include/sbi/sbi_irqchip.h | 10 ++++++++++ lib/sbi/sbi_irqchip.c | 8 ++++++++ lib/utils/irqchip/aplic.c | 7 +++++++ lib/utils/irqchip/imsic.c | 6 ++++++ lib/utils/irqchip/plic.c | 7 +++++++ 5 files changed, 38 insertions(+) diff --git a/include/sbi/sbi_irqchip.h b/include/sbi/sbi_irqchip.h index 0ed02eb4..c88b760a 100644 --- a/include/sbi/sbi_irqchip.h +++ b/include/sbi/sbi_irqchip.h @@ -10,10 +10,17 @@ #ifndef __SBI_IRQCHIP_H__ #define __SBI_IRQCHIP_H__ +#include #include struct sbi_scratch; +/** irqchip hardware device */ +struct sbi_irqchip_device { + /** Node in the list of irqchip devices */ + struct sbi_dlist node; +}; + /** * Set external interrupt handling function * @@ -34,6 +41,9 @@ void sbi_irqchip_set_irqfn(int (*fn)(void)); */ int sbi_irqchip_process(void); +/** Register an irqchip device to receive callbacks */ +void sbi_irqchip_add_device(struct sbi_irqchip_device *dev); + /** Initialize interrupt controllers */ int sbi_irqchip_init(struct sbi_scratch *scratch, bool cold_boot); diff --git a/lib/sbi/sbi_irqchip.c b/lib/sbi/sbi_irqchip.c index 0ae604aa..2ab9d1ff 100644 --- a/lib/sbi/sbi_irqchip.c +++ b/lib/sbi/sbi_irqchip.c @@ -8,8 +8,11 @@ */ #include +#include #include +static SBI_LIST_HEAD(irqchip_list); + static int default_irqfn(void) { return SBI_ENODEV; @@ -28,6 +31,11 @@ int sbi_irqchip_process(void) return ext_irqfn(); } +void sbi_irqchip_add_device(struct sbi_irqchip_device *dev) +{ + sbi_list_add_tail(&dev->node, &irqchip_list); +} + int sbi_irqchip_init(struct sbi_scratch *scratch, bool cold_boot) { int rc; diff --git a/lib/utils/irqchip/aplic.c b/lib/utils/irqchip/aplic.c index 28f2f26d..27371849 100644 --- a/lib/utils/irqchip/aplic.c +++ b/lib/utils/irqchip/aplic.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #define APLIC_MAX_IDC (1UL << 14) @@ -165,6 +166,9 @@ static int aplic_check_msicfg(struct aplic_msicfg_data *msicfg) return 0; } +static struct sbi_irqchip_device aplic_device = { +}; + int aplic_cold_irqchip_init(struct aplic_data *aplic) { int rc; @@ -275,5 +279,8 @@ int aplic_cold_irqchip_init(struct aplic_data *aplic) return rc; } + /* Register irqchip device */ + sbi_irqchip_add_device(&aplic_device); + return 0; } diff --git a/lib/utils/irqchip/imsic.c b/lib/utils/irqchip/imsic.c index ae8b31e0..a3b2cf09 100644 --- a/lib/utils/irqchip/imsic.c +++ b/lib/utils/irqchip/imsic.c @@ -345,6 +345,9 @@ int imsic_data_check(struct imsic_data *imsic) return 0; } +static struct sbi_irqchip_device imsic_device = { +}; + int imsic_cold_irqchip_init(struct imsic_data *imsic) { int i, rc; @@ -387,6 +390,9 @@ int imsic_cold_irqchip_init(struct imsic_data *imsic) return rc; } + /* Register irqchip device */ + sbi_irqchip_add_device(&imsic_device); + /* Register IPI device */ sbi_ipi_set_device(&imsic_ipi_device); diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c index ca506c4c..f9eb7411 100644 --- a/lib/utils/irqchip/plic.c +++ b/lib/utils/irqchip/plic.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -220,6 +221,9 @@ int plic_warm_irqchip_init(void) return 0; } +static struct sbi_irqchip_device plic_device = { +}; + int plic_cold_irqchip_init(struct plic_data *plic) { int i, ret; @@ -278,5 +282,8 @@ int plic_cold_irqchip_init(struct plic_data *plic) plic_set_hart_data_ptr(sbi_hartindex_to_scratch(i), plic); } + /* Register irqchip device */ + sbi_irqchip_add_device(&plic_device); + return 0; } From patchwork Tue Nov 5 04:10:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 2006627 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=gxVoSzHT; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256 header.s=google header.b=NI6B8DOV; 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The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Currently, each platform keeps track of which irqchip driver is in use and calls its warm init function. Since the generic platform may use multiple irqchip drivers, it has logic to track an array of [...] Content analysis details: (-2.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:52b listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Currently, each platform keeps track of which irqchip driver is in use and calls its warm init function. Since the generic platform may use multiple irqchip drivers, it has logic to track an array of drivers. The code is simplified and made common across platforms by treating warm init and exit as properties of the driver, not the platform. Then the platform's only role is to select and prepare a driver during cold boot. For now, only add a .warm_init hook, since none of the existing drivers need an .exit hook. It could be added in the future if needed. Signed-off-by: Samuel Holland --- include/sbi/sbi_irqchip.h | 3 +++ include/sbi_utils/irqchip/imsic.h | 2 -- include/sbi_utils/irqchip/plic.h | 2 -- lib/sbi/sbi_irqchip.c | 9 +++++++++ lib/utils/irqchip/fdt_irqchip_aplic.c | 8 +------- lib/utils/irqchip/fdt_irqchip_imsic.c | 2 +- lib/utils/irqchip/fdt_irqchip_plic.c | 2 +- lib/utils/irqchip/imsic.c | 3 ++- lib/utils/irqchip/plic.c | 3 ++- platform/fpga/ariane/platform.c | 2 +- platform/fpga/openpiton/platform.c | 2 +- platform/kendryte/k210/platform.c | 2 +- platform/nuclei/ux600/platform.c | 2 +- platform/template/platform.c | 2 +- 14 files changed, 24 insertions(+), 20 deletions(-) diff --git a/include/sbi/sbi_irqchip.h b/include/sbi/sbi_irqchip.h index c88b760a..9d26067f 100644 --- a/include/sbi/sbi_irqchip.h +++ b/include/sbi/sbi_irqchip.h @@ -19,6 +19,9 @@ struct sbi_scratch; struct sbi_irqchip_device { /** Node in the list of irqchip devices */ struct sbi_dlist node; + + /** Initialize per-hart state for the current hart */ + int (*warm_init)(struct sbi_irqchip_device *dev); }; /** diff --git a/include/sbi_utils/irqchip/imsic.h b/include/sbi_utils/irqchip/imsic.h index bc9292d3..353cefec 100644 --- a/include/sbi_utils/irqchip/imsic.h +++ b/include/sbi_utils/irqchip/imsic.h @@ -43,8 +43,6 @@ int imsic_get_target_file(u32 hartindex); void imsic_local_irqchip_init(void); -int imsic_warm_irqchip_init(void); - int imsic_data_check(struct imsic_data *imsic); int imsic_cold_irqchip_init(struct imsic_data *imsic); diff --git a/include/sbi_utils/irqchip/plic.h b/include/sbi_utils/irqchip/plic.h index 5c638e14..a173871e 100644 --- a/include/sbi_utils/irqchip/plic.h +++ b/include/sbi_utils/irqchip/plic.h @@ -42,8 +42,6 @@ void plic_suspend(void); void plic_resume(void); -int plic_warm_irqchip_init(void); - int plic_cold_irqchip_init(struct plic_data *plic); #endif diff --git a/lib/sbi/sbi_irqchip.c b/lib/sbi/sbi_irqchip.c index 2ab9d1ff..1aa18b8b 100644 --- a/lib/sbi/sbi_irqchip.c +++ b/lib/sbi/sbi_irqchip.c @@ -40,11 +40,20 @@ int sbi_irqchip_init(struct sbi_scratch *scratch, bool cold_boot) { int rc; const struct sbi_platform *plat = sbi_platform_ptr(scratch); + struct sbi_irqchip_device *dev; rc = sbi_platform_irqchip_init(plat, cold_boot); if (rc) return rc; + sbi_list_for_each_entry(dev, &irqchip_list, node) { + if (!dev->warm_init) + continue; + rc = dev->warm_init(dev); + if (rc) + return rc; + } + if (ext_irqfn != default_irqfn) csr_set(CSR_MIE, MIP_MEIP); diff --git a/lib/utils/irqchip/fdt_irqchip_aplic.c b/lib/utils/irqchip/fdt_irqchip_aplic.c index 6eb6e085..ed6ccf12 100644 --- a/lib/utils/irqchip/fdt_irqchip_aplic.c +++ b/lib/utils/irqchip/fdt_irqchip_aplic.c @@ -16,12 +16,6 @@ #include #include -static int irqchip_aplic_warm_init(void) -{ - /* Nothing to do here. */ - return 0; -} - static int irqchip_aplic_cold_init(const void *fdt, int nodeoff, const struct fdt_match *match) { @@ -55,6 +49,6 @@ static const struct fdt_match irqchip_aplic_match[] = { struct fdt_irqchip fdt_irqchip_aplic = { .match_table = irqchip_aplic_match, .cold_init = irqchip_aplic_cold_init, - .warm_init = irqchip_aplic_warm_init, + .warm_init = NULL, .exit = NULL, }; diff --git a/lib/utils/irqchip/fdt_irqchip_imsic.c b/lib/utils/irqchip/fdt_irqchip_imsic.c index ca62b427..63be6007 100644 --- a/lib/utils/irqchip/fdt_irqchip_imsic.c +++ b/lib/utils/irqchip/fdt_irqchip_imsic.c @@ -95,5 +95,5 @@ static const struct fdt_match irqchip_imsic_match[] = { struct fdt_irqchip fdt_irqchip_imsic = { .match_table = irqchip_imsic_match, .cold_init = irqchip_imsic_cold_init, - .warm_init = imsic_warm_irqchip_init, + .warm_init = NULL, }; diff --git a/lib/utils/irqchip/fdt_irqchip_plic.c b/lib/utils/irqchip/fdt_irqchip_plic.c index ebde7eec..9066d745 100644 --- a/lib/utils/irqchip/fdt_irqchip_plic.c +++ b/lib/utils/irqchip/fdt_irqchip_plic.c @@ -108,6 +108,6 @@ static const struct fdt_match irqchip_plic_match[] = { struct fdt_irqchip fdt_irqchip_plic = { .match_table = irqchip_plic_match, .cold_init = irqchip_plic_cold_init, - .warm_init = plic_warm_irqchip_init, + .warm_init = NULL, .exit = NULL, }; diff --git a/lib/utils/irqchip/imsic.c b/lib/utils/irqchip/imsic.c index a3b2cf09..b5198b43 100644 --- a/lib/utils/irqchip/imsic.c +++ b/lib/utils/irqchip/imsic.c @@ -255,7 +255,7 @@ void imsic_local_irqchip_init(void) imsic_local_eix_update(IMSIC_IPI_ID, 1, false, true); } -int imsic_warm_irqchip_init(void) +static int imsic_warm_irqchip_init(struct sbi_irqchip_device *dev) { struct imsic_data *imsic = imsic_get_data(current_hartindex()); @@ -346,6 +346,7 @@ int imsic_data_check(struct imsic_data *imsic) } static struct sbi_irqchip_device imsic_device = { + .warm_init = imsic_warm_irqchip_init, }; int imsic_cold_irqchip_init(struct imsic_data *imsic) diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c index f9eb7411..7761ae98 100644 --- a/lib/utils/irqchip/plic.c +++ b/lib/utils/irqchip/plic.c @@ -190,7 +190,7 @@ void plic_resume(void) plic_delegate(plic); } -int plic_warm_irqchip_init(void) +static int plic_warm_irqchip_init(struct sbi_irqchip_device *dev) { struct sbi_scratch *scratch = sbi_scratch_thishart_ptr(); const struct plic_data *plic = plic_get_hart_data_ptr(scratch); @@ -222,6 +222,7 @@ int plic_warm_irqchip_init(void) } static struct sbi_irqchip_device plic_device = { + .warm_init = plic_warm_irqchip_init, }; int plic_cold_irqchip_init(struct plic_data *plic) diff --git a/platform/fpga/ariane/platform.c b/platform/fpga/ariane/platform.c index c4ac0ae6..ab3206cf 100644 --- a/platform/fpga/ariane/platform.c +++ b/platform/fpga/ariane/platform.c @@ -110,7 +110,7 @@ static int ariane_irqchip_init(bool cold_boot) return ret; } - return plic_warm_irqchip_init(); + return 0; } /* diff --git a/platform/fpga/openpiton/platform.c b/platform/fpga/openpiton/platform.c index 73429f88..13585297 100644 --- a/platform/fpga/openpiton/platform.c +++ b/platform/fpga/openpiton/platform.c @@ -143,7 +143,7 @@ static int openpiton_irqchip_init(bool cold_boot) return ret; } - return plic_warm_irqchip_init(); + return 0; } /* diff --git a/platform/kendryte/k210/platform.c b/platform/kendryte/k210/platform.c index e1808d17..ebfab715 100644 --- a/platform/kendryte/k210/platform.c +++ b/platform/kendryte/k210/platform.c @@ -146,7 +146,7 @@ static int k210_irqchip_init(bool cold_boot) return rc; } - return plic_warm_irqchip_init(); + return 0; } static int k210_ipi_init(bool cold_boot) diff --git a/platform/nuclei/ux600/platform.c b/platform/nuclei/ux600/platform.c index 12657bc0..0a823e0e 100644 --- a/platform/nuclei/ux600/platform.c +++ b/platform/nuclei/ux600/platform.c @@ -200,7 +200,7 @@ static int ux600_irqchip_init(bool cold_boot) return rc; } - return plic_warm_irqchip_init(); + return 0; } static int ux600_ipi_init(bool cold_boot) diff --git a/platform/template/platform.c b/platform/template/platform.c index 298301a4..a13798d9 100644 --- a/platform/template/platform.c +++ b/platform/template/platform.c @@ -100,7 +100,7 @@ static int platform_irqchip_init(bool cold_boot) return ret; } - return plic_warm_irqchip_init(); + return 0; } /* From patchwork Tue Nov 5 04:10:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 2006635 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=zpIu4RXA; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256 header.s=google header.b=A68JbwnO; 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The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Now that driver lifecycle is managed from within the SBI irqchip core, platforms need only to initialize the driver once during cold init. Remove the remaining platform hooks that are no longer used. Content analysis details: (-2.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:1031 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Now that driver lifecycle is managed from within the SBI irqchip core, platforms need only to initialize the driver once during cold init. Remove the remaining platform hooks that are no longer used. Signed-off-by: Samuel Holland --- include/sbi/sbi_platform.h | 25 +++-------- include/sbi_utils/irqchip/fdt_irqchip.h | 10 +---- lib/sbi/sbi_irqchip.c | 12 +++--- lib/utils/irqchip/fdt_irqchip.c | 57 +------------------------ lib/utils/irqchip/fdt_irqchip_aplic.c | 2 - lib/utils/irqchip/fdt_irqchip_imsic.c | 1 - lib/utils/irqchip/fdt_irqchip_plic.c | 2 - platform/fpga/ariane/platform.c | 14 ++---- platform/fpga/openpiton/platform.c | 14 ++---- platform/generic/platform.c | 1 - platform/kendryte/k210/platform.c | 12 +----- platform/nuclei/ux600/platform.c | 12 +----- platform/template/platform.c | 14 ++---- 13 files changed, 26 insertions(+), 150 deletions(-) diff --git a/include/sbi/sbi_platform.h b/include/sbi/sbi_platform.h index 7b3ac4bf..d6420055 100644 --- a/include/sbi/sbi_platform.h +++ b/include/sbi/sbi_platform.h @@ -111,10 +111,8 @@ struct sbi_platform_operations { /** Get platform specific mhpmevent value */ uint64_t (*pmu_xlate_to_mhpmevent)(uint32_t event_idx, uint64_t data); - /** Initialize the platform interrupt controller for current HART */ - int (*irqchip_init)(bool cold_boot); - /** Exit the platform interrupt controller for current HART */ - void (*irqchip_exit)(void); + /** Initialize the platform interrupt controller during cold boot */ + int (*irqchip_init)(void); /** Initialize IPI for current HART */ int (*ipi_init)(bool cold_boot); @@ -547,32 +545,19 @@ static inline uint64_t sbi_platform_pmu_xlate_to_mhpmevent(const struct sbi_plat } /** - * Initialize the platform interrupt controller for current HART + * Initialize the platform interrupt controller during cold boot * * @param plat pointer to struct sbi_platform - * @param cold_boot whether cold boot (true) or warm_boot (false) * * @return 0 on success and negative error code on failure */ -static inline int sbi_platform_irqchip_init(const struct sbi_platform *plat, - bool cold_boot) +static inline int sbi_platform_irqchip_init(const struct sbi_platform *plat) { if (plat && sbi_platform_ops(plat)->irqchip_init) - return sbi_platform_ops(plat)->irqchip_init(cold_boot); + return sbi_platform_ops(plat)->irqchip_init(); return 0; } -/** - * Exit the platform interrupt controller for current HART - * - * @param plat pointer to struct sbi_platform - */ -static inline void sbi_platform_irqchip_exit(const struct sbi_platform *plat) -{ - if (plat && sbi_platform_ops(plat)->irqchip_exit) - sbi_platform_ops(plat)->irqchip_exit(); -} - /** * Initialize the platform IPI support for current HART * diff --git a/include/sbi_utils/irqchip/fdt_irqchip.h b/include/sbi_utils/irqchip/fdt_irqchip.h index bc02c0c8..0ad00489 100644 --- a/include/sbi_utils/irqchip/fdt_irqchip.h +++ b/include/sbi_utils/irqchip/fdt_irqchip.h @@ -17,19 +17,13 @@ struct fdt_irqchip { const struct fdt_match *match_table; int (*cold_init)(const void *fdt, int nodeoff, const struct fdt_match *match); - int (*warm_init)(void); - void (*exit)(void); }; -void fdt_irqchip_exit(void); - -int fdt_irqchip_init(bool cold_boot); +int fdt_irqchip_init(void); #else -static inline void fdt_irqchip_exit(void) { } - -static inline int fdt_irqchip_init(bool cold_boot) { return 0; } +static inline int fdt_irqchip_init(void) { return 0; } #endif diff --git a/lib/sbi/sbi_irqchip.c b/lib/sbi/sbi_irqchip.c index 1aa18b8b..ab487d16 100644 --- a/lib/sbi/sbi_irqchip.c +++ b/lib/sbi/sbi_irqchip.c @@ -42,9 +42,11 @@ int sbi_irqchip_init(struct sbi_scratch *scratch, bool cold_boot) const struct sbi_platform *plat = sbi_platform_ptr(scratch); struct sbi_irqchip_device *dev; - rc = sbi_platform_irqchip_init(plat, cold_boot); - if (rc) - return rc; + if (cold_boot) { + rc = sbi_platform_irqchip_init(plat); + if (rc) + return rc; + } sbi_list_for_each_entry(dev, &irqchip_list, node) { if (!dev->warm_init) @@ -62,10 +64,6 @@ int sbi_irqchip_init(struct sbi_scratch *scratch, bool cold_boot) void sbi_irqchip_exit(struct sbi_scratch *scratch) { - const struct sbi_platform *plat = sbi_platform_ptr(scratch); - if (ext_irqfn != default_irqfn) csr_clear(CSR_MIE, MIP_MEIP); - - sbi_platform_irqchip_exit(plat); } diff --git a/lib/utils/irqchip/fdt_irqchip.c b/lib/utils/irqchip/fdt_irqchip.c index b4f054ae..2819540a 100644 --- a/lib/utils/irqchip/fdt_irqchip.c +++ b/lib/utils/irqchip/fdt_irqchip.c @@ -16,40 +16,8 @@ extern struct fdt_irqchip *fdt_irqchip_drivers[]; extern unsigned long fdt_irqchip_drivers_size; -#define FDT_IRQCHIP_MAX_DRIVERS 8 - -static struct fdt_irqchip *current_drivers[FDT_IRQCHIP_MAX_DRIVERS] = {0}; -static int current_drivers_count; - -void fdt_irqchip_exit(void) -{ - int i; - - for (i = 0; i < current_drivers_count; i++) { - if (!current_drivers[i] || !current_drivers[i]->exit) - continue; - current_drivers[i]->exit(); - } -} - -static int fdt_irqchip_warm_init(void) -{ - int i, rc; - - for (i = 0; i < current_drivers_count; i++) { - if (!current_drivers[i] || !current_drivers[i]->warm_init) - continue; - rc = current_drivers[i]->warm_init(); - if (rc) - return rc; - } - - return 0; -} - -static int fdt_irqchip_cold_init(void) +int fdt_irqchip_init(void) { - bool drv_added; int pos, noff, rc; struct fdt_irqchip *drv; const struct fdt_match *match; @@ -59,7 +27,6 @@ static int fdt_irqchip_cold_init(void) drv = fdt_irqchip_drivers[pos]; noff = -1; - drv_added = false; while ((noff = fdt_find_match(fdt, noff, drv->match_table, &match)) >= 0) { if (!fdt_node_is_enabled(fdt,noff)) @@ -72,30 +39,8 @@ static int fdt_irqchip_cold_init(void) if (rc) return rc; } - - if (drv_added) - continue; - - current_drivers[current_drivers_count++] = drv; - drv_added = true; } - - if (FDT_IRQCHIP_MAX_DRIVERS <= current_drivers_count) - break; } return 0; } - -int fdt_irqchip_init(bool cold_boot) -{ - int rc; - - if (cold_boot) { - rc = fdt_irqchip_cold_init(); - if (rc) - return rc; - } - - return fdt_irqchip_warm_init(); -} diff --git a/lib/utils/irqchip/fdt_irqchip_aplic.c b/lib/utils/irqchip/fdt_irqchip_aplic.c index ed6ccf12..532d8c48 100644 --- a/lib/utils/irqchip/fdt_irqchip_aplic.c +++ b/lib/utils/irqchip/fdt_irqchip_aplic.c @@ -49,6 +49,4 @@ static const struct fdt_match irqchip_aplic_match[] = { struct fdt_irqchip fdt_irqchip_aplic = { .match_table = irqchip_aplic_match, .cold_init = irqchip_aplic_cold_init, - .warm_init = NULL, - .exit = NULL, }; diff --git a/lib/utils/irqchip/fdt_irqchip_imsic.c b/lib/utils/irqchip/fdt_irqchip_imsic.c index 63be6007..40d63eb0 100644 --- a/lib/utils/irqchip/fdt_irqchip_imsic.c +++ b/lib/utils/irqchip/fdt_irqchip_imsic.c @@ -95,5 +95,4 @@ static const struct fdt_match irqchip_imsic_match[] = { struct fdt_irqchip fdt_irqchip_imsic = { .match_table = irqchip_imsic_match, .cold_init = irqchip_imsic_cold_init, - .warm_init = NULL, }; diff --git a/lib/utils/irqchip/fdt_irqchip_plic.c b/lib/utils/irqchip/fdt_irqchip_plic.c index 9066d745..a7388dcc 100644 --- a/lib/utils/irqchip/fdt_irqchip_plic.c +++ b/lib/utils/irqchip/fdt_irqchip_plic.c @@ -108,6 +108,4 @@ static const struct fdt_match irqchip_plic_match[] = { struct fdt_irqchip fdt_irqchip_plic = { .match_table = irqchip_plic_match, .cold_init = irqchip_plic_cold_init, - .warm_init = NULL, - .exit = NULL, }; diff --git a/platform/fpga/ariane/platform.c b/platform/fpga/ariane/platform.c index ab3206cf..b95c5055 100644 --- a/platform/fpga/ariane/platform.c +++ b/platform/fpga/ariane/platform.c @@ -98,19 +98,11 @@ static int ariane_final_init(bool cold_boot) } /* - * Initialize the ariane interrupt controller for current HART. + * Initialize the ariane interrupt controller during cold boot. */ -static int ariane_irqchip_init(bool cold_boot) +static int ariane_irqchip_init(void) { - int ret; - - if (cold_boot) { - ret = plic_cold_irqchip_init(&plic); - if (ret) - return ret; - } - - return 0; + return plic_cold_irqchip_init(&plic); } /* diff --git a/platform/fpga/openpiton/platform.c b/platform/fpga/openpiton/platform.c index 13585297..e4e338bf 100644 --- a/platform/fpga/openpiton/platform.c +++ b/platform/fpga/openpiton/platform.c @@ -131,19 +131,11 @@ static int openpiton_final_init(bool cold_boot) } /* - * Initialize the openpiton interrupt controller for current HART. + * Initialize the openpiton interrupt controller during cold boot. */ -static int openpiton_irqchip_init(bool cold_boot) +static int openpiton_irqchip_init(void) { - int ret; - - if (cold_boot) { - ret = plic_cold_irqchip_init(&plic); - if (ret) - return ret; - } - - return 0; + return plic_cold_irqchip_init(&plic); } /* diff --git a/platform/generic/platform.c b/platform/generic/platform.c index 49d877d0..24ce0ffb 100644 --- a/platform/generic/platform.c +++ b/platform/generic/platform.c @@ -397,7 +397,6 @@ const struct sbi_platform_operations platform_ops = { .extensions_init = generic_extensions_init, .domains_init = generic_domains_init, .irqchip_init = fdt_irqchip_init, - .irqchip_exit = fdt_irqchip_exit, .ipi_init = fdt_ipi_init, .ipi_exit = fdt_ipi_exit, .pmu_init = generic_pmu_init, diff --git a/platform/kendryte/k210/platform.c b/platform/kendryte/k210/platform.c index ebfab715..74bf76a2 100644 --- a/platform/kendryte/k210/platform.c +++ b/platform/kendryte/k210/platform.c @@ -136,17 +136,9 @@ static int k210_final_init(bool cold_boot) return 0; } -static int k210_irqchip_init(bool cold_boot) +static int k210_irqchip_init(void) { - int rc; - - if (cold_boot) { - rc = plic_cold_irqchip_init(&plic); - if (rc) - return rc; - } - - return 0; + return plic_cold_irqchip_init(&plic); } static int k210_ipi_init(bool cold_boot) diff --git a/platform/nuclei/ux600/platform.c b/platform/nuclei/ux600/platform.c index 0a823e0e..79ad2c94 100644 --- a/platform/nuclei/ux600/platform.c +++ b/platform/nuclei/ux600/platform.c @@ -190,17 +190,9 @@ static int ux600_final_init(bool cold_boot) return 0; } -static int ux600_irqchip_init(bool cold_boot) +static int ux600_irqchip_init(void) { - int rc; - - if (cold_boot) { - rc = plic_cold_irqchip_init(&plic); - if (rc) - return rc; - } - - return 0; + return plic_cold_irqchip_init(&plic); } static int ux600_ipi_init(bool cold_boot) diff --git a/platform/template/platform.c b/platform/template/platform.c index a13798d9..037d9c92 100644 --- a/platform/template/platform.c +++ b/platform/template/platform.c @@ -87,20 +87,12 @@ static int platform_final_init(bool cold_boot) } /* - * Initialize the platform interrupt controller for current HART. + * Initialize the platform interrupt controller during cold boot. */ -static int platform_irqchip_init(bool cold_boot) +static int platform_irqchip_init(void) { - int ret; - /* Example if the generic PLIC driver is used */ - if (cold_boot) { - ret = plic_cold_irqchip_init(&plic); - if (ret) - return ret; - } - - return 0; + return plic_cold_irqchip_init(&plic); } /* From patchwork Tue Nov 5 04:10:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 2006634 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=pAAjzYFv; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256 header.s=google header.b=hylh1Gqm; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:3::133; 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Content preview: In addition to saving some code size, this moves the decision about setting the top-level external interrupt handler to the irqchip core, not the specific driver, which would be needed to support chai [...] Content analysis details: (-2.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:1029 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org In addition to saving some code size, this moves the decision about setting the top-level external interrupt handler to the irqchip core, not the specific driver, which would be needed to support chained interrupt handlers. Signed-off-by: Samuel Holland --- include/sbi/sbi_irqchip.h | 13 +++---------- lib/sbi/sbi_irqchip.c | 9 +++------ lib/utils/irqchip/imsic.c | 4 +--- 3 files changed, 7 insertions(+), 19 deletions(-) diff --git a/include/sbi/sbi_irqchip.h b/include/sbi/sbi_irqchip.h index 9d26067f..e0ae12f5 100644 --- a/include/sbi/sbi_irqchip.h +++ b/include/sbi/sbi_irqchip.h @@ -22,17 +22,10 @@ struct sbi_irqchip_device { /** Initialize per-hart state for the current hart */ int (*warm_init)(struct sbi_irqchip_device *dev); -}; -/** - * Set external interrupt handling function - * - * This function is called by OpenSBI platform code to set a handler for - * external interrupts - * - * @param fn function pointer for handling external irqs - */ -void sbi_irqchip_set_irqfn(int (*fn)(void)); + /** Handle an IRQ from this irqchip */ + int (*irq_handle)(void); +}; /** * Process external interrupts diff --git a/lib/sbi/sbi_irqchip.c b/lib/sbi/sbi_irqchip.c index ab487d16..0594e05a 100644 --- a/lib/sbi/sbi_irqchip.c +++ b/lib/sbi/sbi_irqchip.c @@ -20,12 +20,6 @@ static int default_irqfn(void) static int (*ext_irqfn)(void) = default_irqfn; -void sbi_irqchip_set_irqfn(int (*fn)(void)) -{ - if (fn) - ext_irqfn = fn; -} - int sbi_irqchip_process(void) { return ext_irqfn(); @@ -34,6 +28,9 @@ int sbi_irqchip_process(void) void sbi_irqchip_add_device(struct sbi_irqchip_device *dev) { sbi_list_add_tail(&dev->node, &irqchip_list); + + if (dev->irq_handle) + ext_irqfn = dev->irq_handle; } int sbi_irqchip_init(struct sbi_scratch *scratch, bool cold_boot) diff --git a/lib/utils/irqchip/imsic.c b/lib/utils/irqchip/imsic.c index b5198b43..057b9fa7 100644 --- a/lib/utils/irqchip/imsic.c +++ b/lib/utils/irqchip/imsic.c @@ -347,6 +347,7 @@ int imsic_data_check(struct imsic_data *imsic) static struct sbi_irqchip_device imsic_device = { .warm_init = imsic_warm_irqchip_init, + .irq_handle = imsic_external_irqfn, }; int imsic_cold_irqchip_init(struct imsic_data *imsic) @@ -376,9 +377,6 @@ int imsic_cold_irqchip_init(struct imsic_data *imsic) return SBI_ENOMEM; } - /* Setup external interrupt function for IMSIC */ - sbi_irqchip_set_irqfn(imsic_external_irqfn); - /* Add IMSIC regions to the root domain */ for (i = 0; i < IMSIC_MAX_REGS && imsic->regs[i].size; i++) { rc = sbi_domain_root_add_memrange(imsic->regs[i].addr,