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Mon, 28 Oct 2024 04:24:40 -0500 Received: from xhdvabbarap40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39 via Frontend Transport; Mon, 28 Oct 2024 04:24:37 -0500 From: Venkatesh Yadav Abbarapu To: CC: , , , , , , , , , , Subject: [PATCH] cadence_qspi: Refactor the flash reset functionality Date: Mon, 28 Oct 2024 14:54:30 +0530 Message-ID: <20241028092430.19841-1-venkatesh.abbarapu@amd.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A346:EE_|PH0PR12MB7469:EE_ X-MS-Office365-Filtering-Correlation-Id: 95d4c435-2c4b-4265-3e4f-08dcf7325aa2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|7416014|376014|1800799024|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: ltk6gg/7wOUPglKJROPeiQDOAT/ziOmYwxIMvlsZZsWDn+AgOrVghObRtOieghYyh8ny09yvIsaLoC5k3aLytMPML99w+JUSwANySi4uAOMVEKiy0sozFvERfkj8Byxtg3OdKkFA7l4P3wl8Ex9X0BBYtRRfFkaE6ovN0avkVUQh5aehpWTZ73yx3zIB/X0bPK90WB2ZDCo+Bkd+SNn66v6JDluR+Lm3B5jzuXQBujJs77QNjO+9D4gUSXBRU+YOZg6Kzs1PIeTgXZvQ2YZJ8OBmA4wzyJ86jM7rXOxTOoFXU1kD6KrjjTsJm1fIuJJhYOzgVZIzOysK6eeQKw4s1nQbL40RpEKGiipv0Hz+t54o+Pq6CbY9egv0dNQSwIGyYr7yanf2JqwvYYFqHpW1OEE4+wU8JjUdCEgyrSwuf0cQo7Huv1XWDUmsWk3fVCak2llW20PrCSafAnBePQq9n2kzD3BdBBa5WgmFLgKtifDy/BzS3zVwq+qC3gm6u7ox023cOdP3rtiVPFEk8ZULbHXLzNsCalVIfYGtudBaJvV9IWJ9poOPyOZMPZ9BECKioRg13F0QCN+R8q7zuqI8rHaxT/KGPncUnI3CpyHcoa2FS1/w0aUOJwcEwd3b+lyNLjOfSL8xsXbS0JzJy/UnV9OKdes/g1IOHIPdqLKTPAUCiO9r4bdFk4TDkYvQZYMmqWl1XY8+1c81hI4qdEbuEHJb1f0nHPvnTES/U6/uPXaiGxEZY1Qsufd5SVldRSAVM4F3Rn4nFf3GRm9SouBnBJImlmM2bRvVBPd1/GCUvC87PlB8ISA087Dz1bA/RE2Am07pFFOPxtYrsJz9Znp5ftB8ie5bz/yxzupiX2MEpUBBkof4uxGDBMfDQTZi7jfGVe5NkfBIlfkkYSILzEpCQaxJ96l8m9DJprBRdeFo5yAvmV6p019i3LGVK/2BILxHNrkAsGvNHyM83lHY4HkOh6uwqSZ+BdrYIs212wn1JuSpVrq43KPdivcnE0nWH+DEez2Trf8CKwqrNJDXC0+GELjiWkxnHakTfMia2CBPr+ogXX33KPyh1agaoE3fPdjngZPDXaIq9zisaWlrObnELntHe9ywpX7+OIc7o7xZ/CNOx1+zkrErYbAqRIJWEyPX3Z85xku3O8L75chSJUgYbQEf7ZtA0wIlPLk3dOXdFxSbQstH5d7LqzqCNLr760B+/KSxRQWuGG9bnR85gZ+sm7yIbSHUvn7gOPlG9/dYDXf45kl7ZKmj5DNE5GW260fXydMHUzRaXwzGENwj+AcgH7pG4Mi7xeeqVXd32gjNh1qkYbTzKESryG5R5gGCG2vtFHwc/lRuAWxq1Ny09pJB7N0Qeho6QKao93vfhSzbq8LTFzC82VQ5LDYKib8RJ4S+xZ4hHFwCbP5YhoyzUpZ1iw== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(7416014)(376014)(1800799024)(82310400026)(36860700013); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2024 09:24:41.9994 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 95d4c435-2c4b-4265-3e4f-08dcf7325aa2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A346.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7469 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean As the flash reset is handled in spi nor core, removing the flash reset functionality. As the configuration like tristate and hysterisis need to be enabled by the cdo. Handle the flash reset only for mini u-boot case. Signed-off-by: Venkatesh Yadav Abbarapu --- drivers/spi/cadence_ospi_versal.c | 43 ------------------------------- drivers/spi/cadence_qspi.c | 7 +++-- 2 files changed, 5 insertions(+), 45 deletions(-) diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c index 222f828f54..de51e4c37f 100644 --- a/drivers/spi/cadence_ospi_versal.c +++ b/drivers/spi/cadence_ospi_versal.c @@ -125,48 +125,6 @@ int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_priv *priv) return 0; } -#if defined(CONFIG_DM_GPIO) -int cadence_qspi_versal_flash_reset(struct udevice *dev) -{ - struct gpio_desc gpio; - u32 reset_gpio; - int ret; - - /* request gpio and set direction as output set to 1 */ - ret = gpio_request_by_name(dev, "reset-gpios", 0, &gpio, - GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); - if (ret) { - printf("%s: unable to reset ospi flash device", __func__); - return ret; - } - - reset_gpio = PMIO_NODE_ID_BASE + gpio.offset; - - /* Request for pin */ - xilinx_pm_request(PM_PINCTRL_REQUEST, reset_gpio, 0, 0, 0, NULL); - - /* Enable hysteresis in cmos receiver */ - xilinx_pm_request(PM_PINCTRL_CONFIG_PARAM_SET, reset_gpio, - PM_PINCTRL_CONFIG_SCHMITT_CMOS, - PM_PINCTRL_INPUT_TYPE_SCHMITT, 0, NULL); - - /* Disable Tri-state */ - xilinx_pm_request(PM_PINCTRL_CONFIG_PARAM_SET, reset_gpio, - PM_PINCTRL_CONFIG_TRI_STATE, - PM_PINCTRL_TRI_STATE_DISABLE, 0, NULL); - udelay(1); - - /* Set value 0 to pin */ - dm_gpio_set_value(&gpio, 0); - udelay(1); - - /* Set value 1 to pin */ - dm_gpio_set_value(&gpio, 1); - udelay(1); - - return 0; -} -#else int cadence_qspi_versal_flash_reset(struct udevice *dev) { /* CRP WPROT */ @@ -209,7 +167,6 @@ int cadence_qspi_versal_flash_reset(struct udevice *dev) return 0; } -#endif void cadence_qspi_apb_enable_linear_mode(bool enable) { diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 9c466f8695..f8c3fe8428 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -258,8 +258,11 @@ static int cadence_spi_probe(struct udevice *bus) if (priv->read_delay >= 0) priv->read_delay = -1; - /* Reset ospi flash device */ - return cadence_qspi_versal_flash_reset(bus); + if (!CONFIG_IS_ENABLED(DM_GPIO)) + /* Reset ospi flash device */ + return cadence_qspi_versal_flash_reset(bus); + + return 0; } static int cadence_spi_remove(struct udevice *dev)