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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4318b57b051sm50104535e9.42.2024.10.25.07.12.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 07:12:56 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Song Gao , Eduardo Habkost , "Edgar E. Iglesias" , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Daniel Henrique Barboza , Yoshinori Sato , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 01/21] softfloat: Allow 2-operand NaN propagation rule to be set at runtime Date: Fri, 25 Oct 2024 15:12:34 +0100 Message-Id: <20241025141254.2141506-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025141254.2141506-1-peter.maydell@linaro.org> References: <20241025141254.2141506-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::132; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x132.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org IEEE 758 does not define a fixed rule for which NaN to pick as the result if both operands of a 2-operand operation are NaNs. As a result different architectures have ended up with different rules for propagating NaNs. QEMU currently hardcodes the NaN propagation logic into the binary because pickNaN() has an ifdef ladder for different targets. We want to make the propagation rule instead be selectable at runtime, because: * this will let us have multiple targets in one QEMU binary * the Arm FEAT_AFP architectural feature includes letting the guest select a NaN propagation rule at runtime * x86 specifies different propagation rules for x87 FPU ops and for SSE ops, and specifying the rule in the float_status would let us emulate this, instead of wrongly using the x87 rules everywhere In this commit we add an enum for the propagation rule, the field in float_status, and the corresponding getters and setters. We change pickNaN to honour this, but because all targets still leave this field at its default 0 value, the fallback logic will pick the rule type with the old ifdef ladder. It's valid not to set a propagation rule if default_nan_mode is enabled, because in that case there's no need to pick a NaN; all the callers of pickNaN() catch this case and skip calling it. So we can already assert that we don't get into the "no rule defined" codepath for our four targets which always set default_nan_mode: Hexagon, RiscV, SH4 and Tricore, and for the one target which does not have FP at all: avr. These targets will not need to be updated to call set_float_2nan_prop_rule(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- Reindent means a couple of slightly long lines in comments, but those will move again in a later patch, so seemed clearer to not re-wrap the comment and then re-rewrap it later. --- include/fpu/softfloat-helpers.h | 11 ++ include/fpu/softfloat-types.h | 42 ++++++ fpu/softfloat-specialize.c.inc | 229 ++++++++++++++++++-------------- 3 files changed, 185 insertions(+), 97 deletions(-) diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h index 94cbe073ec5..453188de70b 100644 --- a/include/fpu/softfloat-helpers.h +++ b/include/fpu/softfloat-helpers.h @@ -75,6 +75,12 @@ static inline void set_floatx80_rounding_precision(FloatX80RoundPrec val, status->floatx80_rounding_precision = val; } +static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule, + float_status *status) +{ + status->float_2nan_prop_rule = rule; +} + static inline void set_flush_to_zero(bool val, float_status *status) { status->flush_to_zero = val; @@ -126,6 +132,11 @@ get_floatx80_rounding_precision(float_status *status) return status->floatx80_rounding_precision; } +static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status) +{ + return status->float_2nan_prop_rule; +} + static inline bool get_flush_to_zero(float_status *status) { return status->flush_to_zero; diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 0884ec4ef7a..5cd5a0d0ae1 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -170,6 +170,47 @@ typedef enum __attribute__((__packed__)) { floatx80_precision_s, } FloatX80RoundPrec; +/* + * 2-input NaN propagation rule. Individual architectures have + * different rules for which input NaN is propagated to the output + * when there is more than one NaN on the input. + * + * If default_nan_mode is enabled then it is valid not to set a + * NaN propagation rule, because the softfloat code guarantees + * not to try to pick a NaN to propagate in default NaN mode. + * + * For transition, currently the 'none' rule will cause us to + * fall back to picking the propagation rule based on the existing + * ifdef ladder. When all targets are converted it will be an error + * not to set the rule in float_status unless in default_nan_mode, + * and we will assert if we need to handle an input NaN and no + * rule was selected. + */ +typedef enum __attribute__((__packed__)) { + /* No propagation rule specified */ + float_2nan_prop_none = 0, + /* Prefer SNaN over QNaN, then operand A over B */ + float_2nan_prop_s_ab, + /* Prefer SNaN over QNaN, then operand B over A */ + float_2nan_prop_s_ba, + /* Prefer A over B regardless of SNaN vs QNaN */ + float_2nan_prop_ab, + /* Prefer B over A regardless of SNaN vs QNaN */ + float_2nan_prop_ba, + /* + * This implements x87 NaN propagation rules: + * SNaN + QNaN => return the QNaN + * two SNaNs => return the one with the larger significand, silenced + * two QNaNs => return the one with the larger significand + * SNaN and a non-NaN => return the SNaN, silenced + * QNaN and a non-NaN => return the QNaN + * + * If we get down to comparing significands and they are the same, + * return the NaN with the positive sign bit (if any). + */ + float_2nan_prop_x87, +} Float2NaNPropRule; + /* * Floating Point Status. Individual architectures may maintain * several versions of float_status for different functions. The @@ -181,6 +222,7 @@ typedef struct float_status { uint16_t float_exception_flags; FloatRoundMode float_rounding_mode; FloatX80RoundPrec floatx80_rounding_precision; + Float2NaNPropRule float_2nan_prop_rule; bool tininess_before_rounding; /* should denormalised results go to zero and set the inexact flag? */ bool flush_to_zero; diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 4e279b9bc40..fae6794a152 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -390,118 +390,153 @@ bool float32_is_signaling_nan(float32 a_, float_status *status) static int pickNaN(FloatClass a_cls, FloatClass b_cls, bool aIsLargerSignificand, float_status *status) { -#if defined(TARGET_ARM) || defined(TARGET_MIPS) || defined(TARGET_HPPA) || \ - defined(TARGET_LOONGARCH64) || defined(TARGET_S390X) - /* ARM mandated NaN propagation rules (see FPProcessNaNs()), take - * the first of: - * 1. A if it is signaling - * 2. B if it is signaling - * 3. A (quiet) - * 4. B (quiet) - * A signaling NaN is always quietened before returning it. - */ - /* According to MIPS specifications, if one of the two operands is - * a sNaN, a new qNaN has to be generated. This is done in - * floatXX_silence_nan(). For qNaN inputs the specifications - * says: "When possible, this QNaN result is one of the operand QNaN - * values." In practice it seems that most implementations choose - * the first operand if both operands are qNaN. In short this gives - * the following rules: - * 1. A if it is signaling - * 2. B if it is signaling - * 3. A (quiet) - * 4. B (quiet) - * A signaling NaN is always silenced before returning it. - */ - if (is_snan(a_cls)) { - return 0; - } else if (is_snan(b_cls)) { - return 1; - } else if (is_qnan(a_cls)) { - return 0; - } else { - return 1; - } -#elif defined(TARGET_PPC) || defined(TARGET_M68K) - /* PowerPC propagation rules: - * 1. A if it sNaN or qNaN - * 2. B if it sNaN or qNaN - * A signaling NaN is always silenced before returning it. - */ - /* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL - * 3.4 FLOATING-POINT INSTRUCTION DETAILS - * If either operand, but not both operands, of an operation is a - * nonsignaling NaN, then that NaN is returned as the result. If both - * operands are nonsignaling NaNs, then the destination operand - * nonsignaling NaN is returned as the result. - * If either operand to an operation is a signaling NaN (SNaN), then the - * SNaN bit is set in the FPSR EXC byte. If the SNaN exception enable bit - * is set in the FPCR ENABLE byte, then the exception is taken and the - * destination is not modified. If the SNaN exception enable bit is not - * set, setting the SNaN bit in the operand to a one converts the SNaN to - * a nonsignaling NaN. The operation then continues as described in the - * preceding paragraph for nonsignaling NaNs. - */ - if (is_nan(a_cls)) { - return 0; - } else { - return 1; - } -#elif defined(TARGET_SPARC) - /* Prefer SNaN over QNaN, order B then A. */ - if (is_snan(b_cls)) { - return 1; - } else if (is_snan(a_cls)) { - return 0; - } else if (is_qnan(b_cls)) { - return 1; - } else { - return 0; - } -#elif defined(TARGET_XTENSA) + Float2NaNPropRule rule = status->float_2nan_prop_rule; + /* - * Xtensa has two NaN propagation modes. - * Which one is active is controlled by float_status::use_first_nan. + * We guarantee not to require the target to tell us how to + * pick a NaN if we're always returning the default NaN. */ - if (status->use_first_nan) { + assert(!status->default_nan_mode); + + if (rule == float_2nan_prop_none) { + /* target didn't set the rule: fall back to old ifdef choices */ +#if defined(TARGET_AVR) || defined(TARGET_HEXAGON) \ + || defined(TARGET_RISCV) || defined(TARGET_SH4) \ + || defined(TARGET_TRICORE) + g_assert_not_reached(); +#elif defined(TARGET_ARM) || defined(TARGET_MIPS) || defined(TARGET_HPPA) || \ + defined(TARGET_LOONGARCH64) || defined(TARGET_S390X) + /* + * ARM mandated NaN propagation rules (see FPProcessNaNs()), take + * the first of: + * 1. A if it is signaling + * 2. B if it is signaling + * 3. A (quiet) + * 4. B (quiet) + * A signaling NaN is always quietened before returning it. + */ + /* + * According to MIPS specifications, if one of the two operands is + * a sNaN, a new qNaN has to be generated. This is done in + * floatXX_silence_nan(). For qNaN inputs the specifications + * says: "When possible, this QNaN result is one of the operand QNaN + * values." In practice it seems that most implementations choose + * the first operand if both operands are qNaN. In short this gives + * the following rules: + * 1. A if it is signaling + * 2. B if it is signaling + * 3. A (quiet) + * 4. B (quiet) + * A signaling NaN is always silenced before returning it. + */ + rule = float_2nan_prop_s_ab; +#elif defined(TARGET_PPC) || defined(TARGET_M68K) + /* + * PowerPC propagation rules: + * 1. A if it sNaN or qNaN + * 2. B if it sNaN or qNaN + * A signaling NaN is always silenced before returning it. + */ + /* + * M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL + * 3.4 FLOATING-POINT INSTRUCTION DETAILS + * If either operand, but not both operands, of an operation is a + * nonsignaling NaN, then that NaN is returned as the result. If both + * operands are nonsignaling NaNs, then the destination operand + * nonsignaling NaN is returned as the result. + * If either operand to an operation is a signaling NaN (SNaN), then the + * SNaN bit is set in the FPSR EXC byte. If the SNaN exception enable bit + * is set in the FPCR ENABLE byte, then the exception is taken and the + * destination is not modified. If the SNaN exception enable bit is not + * set, setting the SNaN bit in the operand to a one converts the SNaN to + * a nonsignaling NaN. The operation then continues as described in the + * preceding paragraph for nonsignaling NaNs. + */ + rule = float_2nan_prop_ab; +#elif defined(TARGET_SPARC) + /* Prefer SNaN over QNaN, order B then A. */ + rule = float_2nan_prop_s_ba; +#elif defined(TARGET_XTENSA) + /* + * Xtensa has two NaN propagation modes. + * Which one is active is controlled by float_status::use_first_nan. + */ + if (status->use_first_nan) { + rule = float_2nan_prop_ab; + } else { + rule = float_2nan_prop_ba; + } +#else + rule = float_2nan_prop_x87; +#endif + } + + switch (rule) { + case float_2nan_prop_s_ab: + if (is_snan(a_cls)) { + return 0; + } else if (is_snan(b_cls)) { + return 1; + } else if (is_qnan(a_cls)) { + return 0; + } else { + return 1; + } + break; + case float_2nan_prop_s_ba: + if (is_snan(b_cls)) { + return 1; + } else if (is_snan(a_cls)) { + return 0; + } else if (is_qnan(b_cls)) { + return 1; + } else { + return 0; + } + break; + case float_2nan_prop_ab: if (is_nan(a_cls)) { return 0; } else { return 1; } - } else { + break; + case float_2nan_prop_ba: if (is_nan(b_cls)) { return 1; } else { return 0; } - } -#else - /* This implements x87 NaN propagation rules: - * SNaN + QNaN => return the QNaN - * two SNaNs => return the one with the larger significand, silenced - * two QNaNs => return the one with the larger significand - * SNaN and a non-NaN => return the SNaN, silenced - * QNaN and a non-NaN => return the QNaN - * - * If we get down to comparing significands and they are the same, - * return the NaN with the positive sign bit (if any). - */ - if (is_snan(a_cls)) { - if (is_snan(b_cls)) { - return aIsLargerSignificand ? 0 : 1; - } - return is_qnan(b_cls) ? 1 : 0; - } else if (is_qnan(a_cls)) { - if (is_snan(b_cls) || !is_qnan(b_cls)) { - return 0; + break; + case float_2nan_prop_x87: + /* + * This implements x87 NaN propagation rules: + * SNaN + QNaN => return the QNaN + * two SNaNs => return the one with the larger significand, silenced + * two QNaNs => return the one with the larger significand + * SNaN and a non-NaN => return the SNaN, silenced + * QNaN and a non-NaN => return the QNaN + * + * If we get down to comparing significands and they are the same, + * return the NaN with the positive sign bit (if any). + */ + if (is_snan(a_cls)) { + if (is_snan(b_cls)) { + return aIsLargerSignificand ? 0 : 1; + } + return is_qnan(b_cls) ? 1 : 0; + } else if (is_qnan(a_cls)) { + if (is_snan(b_cls) || !is_qnan(b_cls)) { + return 0; + } else { + return aIsLargerSignificand ? 0 : 1; + } } else { - return aIsLargerSignificand ? 0 : 1; + return 1; } - } else { - return 1; + default: + g_assert_not_reached(); } -#endif } /*---------------------------------------------------------------------------- From patchwork Fri Oct 25 14:12:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 2002288 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=wFazQQ+Z; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4XZlD14pYzz1xwy for ; Sat, 26 Oct 2024 01:14:57 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t4L3q-00041x-Fx; Fri, 25 Oct 2024 10:13:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t4L3o-0003yh-0c for qemu-ppc@nongnu.org; Fri, 25 Oct 2024 10:13:04 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t4L3j-0007lm-Kn for qemu-ppc@nongnu.org; Fri, 25 Oct 2024 10:13:03 -0400 Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-37d4fd00574so1305944f8f.0 for ; Fri, 25 Oct 2024 07:12:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729865578; x=1730470378; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZnxIUdeIDPfopOqS6esccSkst6Aak8TUkDQf9Y6bLJw=; b=wFazQQ+Zttx2Q0IVTm/i/o55910/+kh86QQ2FD5IxroezhhQ78OgmGj6nZ2ISRd5n7 CgPlOYiplTK2RCFHyvXRIQc32n5vWv1WVjy26UVbXIdZsQG1VTt2+ilpOZir3uPx0xGM G0I3PF9BrzJCu8yfw1dyUIctk7Idzc8By6IUJVC8Rak5gBUzkFMIYtkr9WKLGaNZJXxq AaDHmZkPniFDFlDbC+Mqa/PWzLD+owCzWhrw1+AYasDj8GbwTs03mWY268bkCMf2cBIN XlkfQ666HG4VVwhU45kdwL3z842dpdfLzCpjJcBg07whhs/acODElyUhJQrRDUKye1UV TJ2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729865578; x=1730470378; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZnxIUdeIDPfopOqS6esccSkst6Aak8TUkDQf9Y6bLJw=; b=wTUIoXNUWfT/cIyNlfQmDoxeAt3OgakVJJeaB8nktLMLfMGDqXS70Xgv2Qonc9Piuk 3dg+FsihOstxqRgIxiUtlUrgcqBhOv1uBuCRe7sTWN0vbweK/f2bLB/JaUhL8tC99fS4 xDFRfWKN+6Suje3vc7WK/C6IjfXKtIa8qQIaVm/iIRPb014Kt7XgrwZqLvXw6SekpHGG 78v3XnSXT12QcnzL0VS+xgUdfgTwAkmTl27bPUheMbsmJBT8r/COoplFnIKN0hyvKw70 KpPtrOR2FxbFXy4mxu4QOfXUfRDfptkjA9M48Kq5yFWYUh/vzD6AnOAznJjGB0mGwMYI le3g== X-Forwarded-Encrypted: i=1; AJvYcCXHdU/4G1amUgECICSpg+Sq0qwy583yRX9qk8AZrv/lusAaDKBLShtpAJkROr5VnlQGK3pfMUl1JQ==@nongnu.org X-Gm-Message-State: AOJu0YypL+zkIuEH7uFvdW4eC6YYOMVpPPwXISlvlwdNrCDsQ6RQHLvN abYqxGJCmK2QUrJt3ehKpxt6ntN8fHrfz5Kw9MnIhS0yQneiKqPqRMi6GTY8ipM= X-Google-Smtp-Source: AGHT+IGbytfqhK7flKWpsy7Fx6Uu02lBkJU5a5y/tCFHWWrB5gwAn7GzxDwiORlerliSD/mfpFRIBw== X-Received: by 2002:a5d:4fcb:0:b0:374:c33d:377d with SMTP id ffacd0b85a97d-380458812bbmr4321188f8f.28.1729865578101; Fri, 25 Oct 2024 07:12:58 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4318b57b051sm50104535e9.42.2024.10.25.07.12.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 07:12:57 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Song Gao , Eduardo Habkost , "Edgar E. Iglesias" , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Daniel Henrique Barboza , Yoshinori Sato , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 02/21] tests/fp: Explicitly set 2-NaN propagation rule Date: Fri, 25 Oct 2024 15:12:35 +0100 Message-Id: <20241025141254.2141506-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025141254.2141506-1-peter.maydell@linaro.org> References: <20241025141254.2141506-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Explicitly set a 2-NaN propagation rule in the softfloat tests. In meson.build we put -DTARGET_ARM in fpcflags, and so we should select here the Arm propagation rule of float_2nan_prop_s_ab. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- tests/fp/fp-bench.c | 2 ++ tests/fp/fp-test-log2.c | 1 + tests/fp/fp-test.c | 2 ++ 3 files changed, 5 insertions(+) diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c index 8ce0ca1545d..75c07d5d1f1 100644 --- a/tests/fp/fp-bench.c +++ b/tests/fp/fp-bench.c @@ -488,6 +488,8 @@ static void run_bench(void) { bench_func_t f; + set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status); + f = bench_funcs[operation][precision]; g_assert(f); f(); diff --git a/tests/fp/fp-test-log2.c b/tests/fp/fp-test-log2.c index 4eae93eb7cc..de702c4c80d 100644 --- a/tests/fp/fp-test-log2.c +++ b/tests/fp/fp-test-log2.c @@ -70,6 +70,7 @@ int main(int ac, char **av) float_status qsf = {0}; int i; + set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); set_float_rounding_mode(float_round_nearest_even, &qsf); test.d = 0.0; diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c index 36b5712cda0..5f6f25c8821 100644 --- a/tests/fp/fp-test.c +++ b/tests/fp/fp-test.c @@ -935,6 +935,8 @@ void run_test(void) { unsigned int i; + set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); + genCases_setLevel(test_level); verCases_maxErrorCount = n_max_errors; From patchwork Fri Oct 25 14:12:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 2002314 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=csU1314F; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4XZlHy1qVQz1xtp for ; Sat, 26 Oct 2024 01:18:22 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t4L3v-00046c-7Q; Fri, 25 Oct 2024 10:13:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t4L3s-00042y-5W for qemu-ppc@nongnu.org; Fri, 25 Oct 2024 10:13:08 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t4L3k-0007mE-Pe for qemu-ppc@nongnu.org; Fri, 25 Oct 2024 10:13:07 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-4316cce103dso27015845e9.3 for ; Fri, 25 Oct 2024 07:13:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729865579; x=1730470379; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eGwvRk7TZZeC43moIVYb7p9RL4z/VBbvk9hnG7xUO3c=; b=csU1314FYbm4YozNi99R86y+c/GF1E2b4jGCRATbeBgb8HKVNk/fBvz2dnq02NeeyJ x5lT6UADsEWBGk4QGftmz4W+JLAm+07Giahp1Uv2GkaBgIeMmTmBONPRZaL4kT3Gz1ft nMmDAx3DCRTyDVPRP4ehLMLzFrH9GIerqqM6QLoRRXLzRdPktSQvNQRglwt9pe89LEvV zVl6uHiGJeNtQZTI7yGfOqA5+X6IbNRpd5BnoGilMDl70XxgL1kz1IYt+YRFopy+zWH2 Sx84BiLdoVSbl2kDPKECJcxZmDG47bll/3iP3JR8g5j4WdzbrLmgyT9OMadz4woJCBhX 3Ixw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729865579; x=1730470379; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eGwvRk7TZZeC43moIVYb7p9RL4z/VBbvk9hnG7xUO3c=; b=JnQycaPDjmukBUALm9pMZqipC4+RpV+ff2gz0X2VYXfWDMshWrsqWGgjK/1DgW8x8b ifH3JoUFVIMq3s+SDKOfS9VBM8BtKC0Zbyj9mTBIWJlo5ynM6sMgUH+gx58HJfRpqnXx mXC+4mQbzUKkvYBhYPjY9zj7Hcmc5/tBB6Mm6Gyu9x6TR1CdUeHUEgc7CUb2GKbu6cxl l8JxzQU5wAhtSx6PhBPWXbpJEfZdYynzFOd5FnCi/HaNwhhgsidT0OE8s4ee+0oBAkBz x/cfy7a1ZFcXPkXfjfPzRAP+ztNli3RmA7Od8MmEQOU0MacTGUIxjQpnxSndFbmqF00b ZHqQ== X-Forwarded-Encrypted: i=1; AJvYcCVtah3h6kkyrUh9Xdm9hEDgIMXQEx2MjqsfeHRSu+sA878zBenr/ga4ncXgYmFI6pc+cfOI7JLHZA==@nongnu.org X-Gm-Message-State: AOJu0YxqHlXygP8K6kGDoHM7UcnEMuABDYOGMCCQ4JZyzCCqYi86fxcQ jO24MjJ9XlTzUMYZS0UFb4Cp3m/yEbWF9cEg6KojEywNm5sOTDes7bdcGXT2rc0= X-Google-Smtp-Source: AGHT+IEYimKNM/5+v3TTeeUBvxWOef5wpaX97b0yuiLjdVPgKthFZTkVWfIVxbwFrprYwlrLlBD4eA== X-Received: by 2002:a05:600c:1f09:b0:426:59fe:ac27 with SMTP id 5b1f17b1804b1-43184241cc5mr111818875e9.26.1729865579076; Fri, 25 Oct 2024 07:12:59 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4318b57b051sm50104535e9.42.2024.10.25.07.12.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 07:12:58 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Song Gao , Eduardo Habkost , "Edgar E. Iglesias" , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Daniel Henrique Barboza , Yoshinori Sato , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 03/21] target/arm: Explicitly set 2-NaN propagation rule Date: Fri, 25 Oct 2024 15:12:36 +0100 Message-Id: <20241025141254.2141506-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025141254.2141506-1-peter.maydell@linaro.org> References: <20241025141254.2141506-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Set the 2-NaN propagation rule explicitly in the float_status words we use. We wrap this plus the pre-existing setting of the tininess-before-rounding flag in a new function arm_set_default_fp_behaviours() to avoid repetition, since we have a lot of float_status words at this point. The situation with FPA11 emulation in linux-user is a little odd, and arguably "correct" behaviour there would be to exactly match a real Linux kernel's FPA11 emulation. However FPA11 emulation is essentially dead at this point and so it seems better to continue with QEMU's current behaviour and leave a comment describing the situation. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- linux-user/arm/nwfpe/fpa11.c | 18 ++++++++++++++++++ target/arm/cpu.c | 25 +++++++++++++++++-------- fpu/softfloat-specialize.c.inc | 13 ++----------- 3 files changed, 37 insertions(+), 19 deletions(-) diff --git a/linux-user/arm/nwfpe/fpa11.c b/linux-user/arm/nwfpe/fpa11.c index 9a93610d245..8356beb52c6 100644 --- a/linux-user/arm/nwfpe/fpa11.c +++ b/linux-user/arm/nwfpe/fpa11.c @@ -51,6 +51,24 @@ void resetFPA11(void) #ifdef MAINTAIN_FPCR fpa11->fpcr = MASK_RESET; #endif + + /* + * Real FPA11 hardware does not handle NaNs, but always takes an + * exception for them to be software-emulated (ARM7500FE datasheet + * section 10.4). There is no documented architectural requirement + * for NaN propagation rules and it will depend on how the OS + * level software emulation opted to do it. We here use prop_s_ab + * which matches the later VFP hardware choice and how QEMU's + * fpa11 emulation has worked in the past. The real Linux kernel + * does something slightly different: arch/arm/nwfpe/softfloat-specialize + * propagateFloat64NaN() has the curious behaviour that it prefers + * the QNaN over the SNaN, but if both are QNaN it picks A and + * if both are SNaN it picks B. In theory we could add this as + * a NaN propagation rule, but in practice FPA11 emulation is so + * close to totally dead that it's not worth trying to match it at + * this late date. + */ + set_float_2nan_prop_rule(float_2nan_prop_s_ab, &fpa11->fp_status); } void SetRoundingMode(const unsigned int opcode) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1320fd8c8fe..2fd286972a9 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -168,6 +168,18 @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); } +/* + * Set the float_status behaviour to match the Arm defaults: + * * tininess-before-rounding + * * 2-input NaN propagation prefers SNaN over QNaN, and then + * operand A over operand B (see FPProcessNaNs() pseudocode) + */ +static void arm_set_default_fp_behaviours(float_status *s) +{ + set_float_detect_tininess(float_tininess_before_rounding, s); + set_float_2nan_prop_rule(float_2nan_prop_s_ab, s); +} + static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) { /* Reset a single ARMCPRegInfo register */ @@ -549,14 +561,11 @@ static void arm_cpu_reset_hold(Object *obj, ResetType type) set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); set_default_nan_mode(1, &env->vfp.standard_fp_status); set_default_nan_mode(1, &env->vfp.standard_fp_status_f16); - set_float_detect_tininess(float_tininess_before_rounding, - &env->vfp.fp_status); - set_float_detect_tininess(float_tininess_before_rounding, - &env->vfp.standard_fp_status); - set_float_detect_tininess(float_tininess_before_rounding, - &env->vfp.fp_status_f16); - set_float_detect_tininess(float_tininess_before_rounding, - &env->vfp.standard_fp_status_f16); + arm_set_default_fp_behaviours(&env->vfp.fp_status); + arm_set_default_fp_behaviours(&env->vfp.standard_fp_status); + arm_set_default_fp_behaviours(&env->vfp.fp_status_f16); + arm_set_default_fp_behaviours(&env->vfp.standard_fp_status_f16); + #ifndef CONFIG_USER_ONLY if (kvm_enabled()) { kvm_arm_reset_vcpu(cpu); diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index fae6794a152..70cd3628b54 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -402,19 +402,10 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, /* target didn't set the rule: fall back to old ifdef choices */ #if defined(TARGET_AVR) || defined(TARGET_HEXAGON) \ || defined(TARGET_RISCV) || defined(TARGET_SH4) \ - || defined(TARGET_TRICORE) + || defined(TARGET_TRICORE) || defined(TARGET_ARM) g_assert_not_reached(); -#elif defined(TARGET_ARM) || defined(TARGET_MIPS) || defined(TARGET_HPPA) || \ +#elif defined(TARGET_MIPS) || defined(TARGET_HPPA) || \ defined(TARGET_LOONGARCH64) || defined(TARGET_S390X) - /* - * ARM mandated NaN propagation rules (see FPProcessNaNs()), take - * the first of: - * 1. A if it is signaling - * 2. B if it is signaling - * 3. A (quiet) - * 4. B (quiet) - * A signaling NaN is always quietened before returning it. - */ /* * According to MIPS specifications, if one of the two operands is * a sNaN, a new qNaN has to be generated. This is done in From patchwork Fri Oct 25 14:12:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 2002291 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=CGBuWOgn; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4XZlDd1wztz1xtp for ; Sat, 26 Oct 2024 01:15:29 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t4L3u-00045J-0v; Fri, 25 Oct 2024 10:13:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t4L3r-00042m-2o for qemu-ppc@nongnu.org; Fri, 25 Oct 2024 10:13:07 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t4L3l-0007mo-JH for qemu-ppc@nongnu.org; Fri, 25 Oct 2024 10:13:06 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-4315abed18aso20414725e9.2 for ; Fri, 25 Oct 2024 07:13:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729865580; x=1730470380; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oxpTyYZBHeinKYjs0KLdQZTFPyy0lkXjTFzf5hZbbFo=; b=CGBuWOgnxSzMdPYu0Rqs/8R6Pw7jLtC2XSAHErJjZbnCk75QLKtNPWZlryveWc0Ile 8V0uW9QhvS1i9bzN67Xkl3k8KZAzaZVGiLeC9Uy+KEp1uJ+O88fJM9nmTi7rgAXLnYl1 TuSuikrcAK7V12/E9k6/cpFuxzbC4gHCCKr3tYZAhjvywF6djZoX+qQg7UcVzoSA0LIT DqYKreg8VrONjmnCnNcS2Prx9ZsCD6nVzgLLMxNP+S46puGCq1w4Rvmzg8648k9Ze1sR I94Z22WNprp5IfK2t0L4oZvUnmdGlM2Ok2c/JpRBN0GPWncUOSMY0zA+dCPvAiAvVkFP R7cQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729865580; x=1730470380; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oxpTyYZBHeinKYjs0KLdQZTFPyy0lkXjTFzf5hZbbFo=; b=KSbPyzaEcnLRxa+MefBlxeqF8AspfDIKJVJPOerwJyYJyqbq1VttH3FDRy6Q/5GIGC rN2uMFNqFif4VkPwF/Y/f38o4d5G0uAa8dkH3PA3FjU9l5dKFzZQNv2MFSVqByyHjyIB iH65o2ZwvFswZnfuxnq2XLlE66qnwB6IJxeRVGU/7acIvr4T+V0BrOsi7DkAI9lXtFXS D4+iM+Va4qDHYosgM8aIeqenfN1yr55+539he1N78U90yeXptCcWXx5BZOtUhIYtx296 flUGtwb4IiyIMDJ6Lwjkpa4AXX/p3hl8UyDsJRVjsOTS1WvswusfM4NFsFW6KMHziVv8 7Zag== X-Forwarded-Encrypted: i=1; AJvYcCWQK4zruUzY6PO5bWPxmFebzcZXgH+NBnlQPHJvL4kR5N5eBszWErgZ0gX9MlPcqF74KVUTPPg42Q==@nongnu.org X-Gm-Message-State: AOJu0YyBdS9uuvZIYPmgqghSvPdIEVH0SBOJqyAqs3IQ1nFn5jHnaPHJ EJhDbp2TorR7AtzMyLmdAVX++evpdEc6oAN4YL8hobA4xVzbwrGq+FpZAZ4fq68= X-Google-Smtp-Source: AGHT+IFmo0A/cK7mxek7qVmenyHyXSHRnCM6HvcgZruK2l+y0NWBmuNTPj3PU5VnMspDYKzexoWsSw== X-Received: by 2002:a05:600c:511c:b0:42f:823d:dddd with SMTP id 5b1f17b1804b1-4318423b856mr71363435e9.27.1729865580016; Fri, 25 Oct 2024 07:13:00 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4318b57b051sm50104535e9.42.2024.10.25.07.12.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 07:12:59 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Song Gao , Eduardo Habkost , "Edgar E. Iglesias" , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Daniel Henrique Barboza , Yoshinori Sato , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 04/21] target/mips: Explicitly set 2-NaN propagation rule Date: Fri, 25 Oct 2024 15:12:37 +0100 Message-Id: <20241025141254.2141506-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025141254.2141506-1-peter.maydell@linaro.org> References: <20241025141254.2141506-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Set the 2-NaN propagation rule explicitly in the float_status words we use. For active_fpu.fp_status, we do this in a new fp_reset() function which mirrors the existing msa_reset() function in doing "first call restore to set the fp status parts that depend on CPU state, then set the fp status parts that are constant". Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- target/mips/fpu_helper.h | 22 ++++++++++++++++++++++ target/mips/cpu.c | 2 +- target/mips/msa.c | 17 +++++++++++++++++ fpu/softfloat-specialize.c.inc | 18 ++---------------- 4 files changed, 42 insertions(+), 17 deletions(-) diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h index ad1116e8c10..7c3c7897b45 100644 --- a/target/mips/fpu_helper.h +++ b/target/mips/fpu_helper.h @@ -44,6 +44,28 @@ static inline void restore_fp_status(CPUMIPSState *env) restore_snan_bit_mode(env); } +static inline void fp_reset(CPUMIPSState *env) +{ + restore_fp_status(env); + + /* + * According to MIPS specifications, if one of the two operands is + * a sNaN, a new qNaN has to be generated. This is done in + * floatXX_silence_nan(). For qNaN inputs the specifications + * says: "When possible, this QNaN result is one of the operand QNaN + * values." In practice it seems that most implementations choose + * the first operand if both operands are qNaN. In short this gives + * the following rules: + * 1. A if it is signaling + * 2. B if it is signaling + * 3. A (quiet) + * 4. B (quiet) + * A signaling NaN is always silenced before returning it. + */ + set_float_2nan_prop_rule(float_2nan_prop_s_ab, + &env->active_fpu.fp_status); +} + /* MSA */ enum CPUMIPSMSADataFormat { diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 9724e71a5e0..d0a43b6d5c7 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -407,9 +407,9 @@ static void mips_cpu_reset_hold(Object *obj, ResetType type) } msa_reset(env); + fp_reset(env); compute_hflags(env); - restore_fp_status(env); restore_pamask(env); cs->exception_index = EXCP_NONE; diff --git a/target/mips/msa.c b/target/mips/msa.c index 61f1a9a5936..9dffc428f5c 100644 --- a/target/mips/msa.c +++ b/target/mips/msa.c @@ -49,6 +49,23 @@ void msa_reset(CPUMIPSState *env) set_float_detect_tininess(float_tininess_after_rounding, &env->active_tc.msa_fp_status); + /* + * According to MIPS specifications, if one of the two operands is + * a sNaN, a new qNaN has to be generated. This is done in + * floatXX_silence_nan(). For qNaN inputs the specifications + * says: "When possible, this QNaN result is one of the operand QNaN + * values." In practice it seems that most implementations choose + * the first operand if both operands are qNaN. In short this gives + * the following rules: + * 1. A if it is signaling + * 2. B if it is signaling + * 3. A (quiet) + * 4. B (quiet) + * A signaling NaN is always silenced before returning it. + */ + set_float_2nan_prop_rule(float_2nan_prop_s_ab, + &env->active_tc.msa_fp_status); + /* clear float_status exception flags */ set_float_exception_flags(0, &env->active_tc.msa_fp_status); diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 70cd3628b54..c60b999aa3d 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -402,24 +402,10 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, /* target didn't set the rule: fall back to old ifdef choices */ #if defined(TARGET_AVR) || defined(TARGET_HEXAGON) \ || defined(TARGET_RISCV) || defined(TARGET_SH4) \ - || defined(TARGET_TRICORE) || defined(TARGET_ARM) + || defined(TARGET_TRICORE) || defined(TARGET_ARM) || defined(TARGET_MIPS) g_assert_not_reached(); -#elif defined(TARGET_MIPS) || defined(TARGET_HPPA) || \ +#elif defined(TARGET_HPPA) || \ defined(TARGET_LOONGARCH64) || defined(TARGET_S390X) - /* - * According to MIPS specifications, if one of the two operands is - * a sNaN, a new qNaN has to be generated. This is done in - * floatXX_silence_nan(). For qNaN inputs the specifications - * says: "When possible, this QNaN result is one of the operand QNaN - * values." In practice it seems that most implementations choose - * the first operand if both operands are qNaN. In short this gives - * the following rules: - * 1. A if it is signaling - * 2. B if it is signaling - * 3. A (quiet) - * 4. B (quiet) - * A signaling NaN is always silenced before returning it. - */ rule = float_2nan_prop_s_ab; #elif defined(TARGET_PPC) || defined(TARGET_M68K) /* From patchwork Fri Oct 25 14:12:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 2002308 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=O2s93LMA; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4XZlHJ4KRLz1xtp for ; Sat, 26 Oct 2024 01:17:48 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t4L3v-00047c-Uc; Fri, 25 Oct 2024 10:13:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t4L3t-00043l-FC for qemu-ppc@nongnu.org; Fri, 25 Oct 2024 10:13:09 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t4L3m-0007nE-En for qemu-ppc@nongnu.org; Fri, 25 Oct 2024 10:13:08 -0400 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-4315c1c7392so21121795e9.1 for ; Fri, 25 Oct 2024 07:13:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729865581; x=1730470381; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YDlbbvylJyMrU/YJShcxhMfUmai1iRbva+PhQ15qan4=; b=O2s93LMAgXPvuN0338XpNBLW0UNo2M5/Kgk+ROvEM52yyeaN5uzbmk2gYnF9lHu2Lc JDouInfGo/lSWGLNW0EqQiXo/1ZnwSUYL2+3D48lEkb0qKDNZytlqyByju9SP5TAXYWn wHsfh7G2sBpR7j6xBihiAFL13b4ug89XNOW5jTMBgVu2UovagfCoq+npfffyeEjcdGnW 1QKBwiCn0Dlctx6oLTOYZOxqZEttcN91LdKz+jblhqItmYpQzk0P47Hy6UdHx17qy4LZ N0y3MAI/1G+kHb069gIRHXrzJ1SB0rGR99wpG7SZdF4vGf8BNOHl5x+pZIloTamiL0WQ /VGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729865581; x=1730470381; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YDlbbvylJyMrU/YJShcxhMfUmai1iRbva+PhQ15qan4=; b=HIgl95AHuRLIFEC/u6b+G90/8ZCbw1giCA137W+oW/PvWks8ZeJD1JxTB224lzSlVC k1hQkVdFHelBDyb3ZcL/E5iSmudQoAy816w5+PLU+iRekFS/p5DxbnJ3nWpfqtNYHm+x 3SFtYndn8B1xxf5SMtuC4mI1ENrcFRLf19Qr7zPbHovwtOD8gL8bv66tbl1l7zk6HhR8 qeqEFxlZmyrqrGZVHna0yac/8rvLIR9aSkpSFGrnMQwQt4JSjdinop2ugf2dYaTke5xM opRjyZiATmmh1JIPY+lVFFr0qd+PLY+w2pIrlW3bvLSnMeOB9UlL7i5OyC/Sjb7JLA/3 8eGg== X-Forwarded-Encrypted: i=1; AJvYcCUHXYyAhnSUXuz/rltJ4E0AlFPW5VH/C28E3VtWnOt+z5w3sXRn9KqhcWybwY6DG7eYBbYWbcdAuw==@nongnu.org X-Gm-Message-State: AOJu0YxAZ90lxXKQDt9GC86FgDVlelPxl/U82GkMjT300wkULGEKkoqS Zk+rLYPZH+pgF72jhF1Zcw2Kt+JFlSyXiCCnK6HAPQM0l7AzrbkEqAXK5NjWQE4= X-Google-Smtp-Source: AGHT+IGhrCfW0xMsmU6S61HVoy3sW36vUuPi9HltT0dQ13BCpWIevBn1kVk6idl0Da/qYmgJw0nA8w== X-Received: by 2002:a05:600c:1c03:b0:42b:af5a:109 with SMTP id 5b1f17b1804b1-4318424eb98mr90790405e9.24.1729865580849; Fri, 25 Oct 2024 07:13:00 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4318b57b051sm50104535e9.42.2024.10.25.07.13.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 07:13:00 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Song Gao , Eduardo Habkost , "Edgar E. Iglesias" , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Daniel Henrique Barboza , Yoshinori Sato , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 05/21] target/loongarch: Explicitly set 2-NaN propagation rule Date: Fri, 25 Oct 2024 15:12:38 +0100 Message-Id: <20241025141254.2141506-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025141254.2141506-1-peter.maydell@linaro.org> References: <20241025141254.2141506-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Set the 2-NaN propagation rule explicitly in the float_status word we use. (There are a couple of places in fpu_helper.c where we create a dummy float_status word with "float_status *s = { };", but these are only used for calling float*_is_quiet_nan() so it doesn't matter that we don't set a 2-NaN propagation rule there.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/loongarch/tcg/fpu_helper.c | 1 + fpu/softfloat-specialize.c.inc | 6 +++--- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c index f6753c5875b..21bc3b04a96 100644 --- a/target/loongarch/tcg/fpu_helper.c +++ b/target/loongarch/tcg/fpu_helper.c @@ -31,6 +31,7 @@ void restore_fp_status(CPULoongArchState *env) set_float_rounding_mode(ieee_rm[(env->fcsr0 >> FCSR0_RM) & 0x3], &env->fp_status); set_flush_to_zero(0, &env->fp_status); + set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status); } int ieee_ex_to_loongarch(int xcpt) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index c60b999aa3d..bbc3b70fa9d 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -402,10 +402,10 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, /* target didn't set the rule: fall back to old ifdef choices */ #if defined(TARGET_AVR) || defined(TARGET_HEXAGON) \ || defined(TARGET_RISCV) || defined(TARGET_SH4) \ - || defined(TARGET_TRICORE) || defined(TARGET_ARM) || defined(TARGET_MIPS) + || defined(TARGET_TRICORE) || defined(TARGET_ARM) || defined(TARGET_MIPS) \ + || defined(TARGET_LOONGARCH64) g_assert_not_reached(); -#elif defined(TARGET_HPPA) || \ - defined(TARGET_LOONGARCH64) || defined(TARGET_S390X) +#elif defined(TARGET_HPPA) || defined(TARGET_S390X) rule = float_2nan_prop_s_ab; #elif defined(TARGET_PPC) || defined(TARGET_M68K) /* From patchwork Fri Oct 25 14:12:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 2002312 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=LmZoURKW; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4XZlHY4rZhz1xtp for ; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4318b57b051sm50104535e9.42.2024.10.25.07.13.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 07:13:01 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Song Gao , Eduardo Habkost , "Edgar E. Iglesias" , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Daniel Henrique Barboza , Yoshinori Sato , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 06/21] target/hppa: Explicitly set 2-NaN propagation rule Date: Fri, 25 Oct 2024 15:12:39 +0100 Message-Id: <20241025141254.2141506-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025141254.2141506-1-peter.maydell@linaro.org> References: <20241025141254.2141506-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12d; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x12d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Set the 2-NaN propagation rule explicitly in env->fp_status. Really we only need to do this at CPU reset (after reset has zeroed out most of the CPU state struct, which typically includes fp_status fields). However target/hppa does not currently implement CPU reset at all, so leave a TODO comment to note that this could be moved if we ever do implement reset. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/hppa/fpu_helper.c | 6 ++++++ fpu/softfloat-specialize.c.inc | 4 ++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c index deaed2b65d1..0e44074ba82 100644 --- a/target/hppa/fpu_helper.c +++ b/target/hppa/fpu_helper.c @@ -49,6 +49,12 @@ void HELPER(loaded_fr0)(CPUHPPAState *env) d = FIELD_EX32(shadow, FPSR, D); set_flush_to_zero(d, &env->fp_status); set_flush_inputs_to_zero(d, &env->fp_status); + + /* + * TODO: we only need to do this at CPU reset, but currently + * HPPA does note implement a CPU reset method at all... + */ + set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status); } void cpu_hppa_loaded_fr0(CPUHPPAState *env) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index bbc3b70fa9d..4e51cf8d083 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -403,9 +403,9 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, #if defined(TARGET_AVR) || defined(TARGET_HEXAGON) \ || defined(TARGET_RISCV) || defined(TARGET_SH4) \ || defined(TARGET_TRICORE) || defined(TARGET_ARM) || defined(TARGET_MIPS) \ - || defined(TARGET_LOONGARCH64) + || defined(TARGET_LOONGARCH64) || defined(TARGET_HPPA) g_assert_not_reached(); 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4318b57b051sm50104535e9.42.2024.10.25.07.13.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 07:13:02 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Song Gao , Eduardo Habkost , "Edgar E. Iglesias" , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Daniel Henrique Barboza , Yoshinori Sato , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 07/21] target/s390x: Explicitly set 2-NaN propagation rule Date: Fri, 25 Oct 2024 15:12:40 +0100 Message-Id: <20241025141254.2141506-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025141254.2141506-1-peter.maydell@linaro.org> References: <20241025141254.2141506-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Set the 2-NaN propagation rule explicitly in env->fpu_status. Signed-off-by: Peter Maydell Reviewed-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/s390x/cpu.c | 1 + fpu/softfloat-specialize.c.inc | 5 ++--- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 4e41a3dff59..514c70f3010 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -205,6 +205,7 @@ static void s390_cpu_reset_hold(Object *obj, ResetType type) /* tininess for underflow is detected before rounding */ set_float_detect_tininess(float_tininess_before_rounding, &env->fpu_status); + set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status); /* fall through */ case RESET_TYPE_S390_CPU_NORMAL: env->psw.mask &= ~PSW_MASK_RI; diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 4e51cf8d083..a0c740e544d 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -403,10 +403,9 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, #if defined(TARGET_AVR) || defined(TARGET_HEXAGON) \ || defined(TARGET_RISCV) || defined(TARGET_SH4) \ || defined(TARGET_TRICORE) || defined(TARGET_ARM) || defined(TARGET_MIPS) \ - || defined(TARGET_LOONGARCH64) || defined(TARGET_HPPA) + || defined(TARGET_LOONGARCH64) || defined(TARGET_HPPA) \ + || defined(TARGET_S390X) g_assert_not_reached(); -#elif defined(TARGET_S390X) - rule = float_2nan_prop_s_ab; #elif defined(TARGET_PPC) || defined(TARGET_M68K) /* * PowerPC propagation rules: From patchwork Fri Oct 25 14:12:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 2002277 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=Ac1bPSnc; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4XZlC31nNPz1xwy for ; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4318b57b051sm50104535e9.42.2024.10.25.07.13.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 07:13:03 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Song Gao , Eduardo Habkost , "Edgar E. Iglesias" , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Daniel Henrique Barboza , Yoshinori Sato , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 08/21] target/ppc: Explicitly set 2-NaN propagation rule Date: Fri, 25 Oct 2024 15:12:41 +0100 Message-Id: <20241025141254.2141506-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025141254.2141506-1-peter.maydell@linaro.org> References: <20241025141254.2141506-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Set the 2-NaN propagation rule explicitly in env->fp_status and env->vec_status. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- As an aside, it looks a bit suspicious that we set tininess_before_rounding on fp_status but not vec_status... --- target/ppc/cpu_init.c | 8 ++++++++ fpu/softfloat-specialize.c.inc | 10 ++-------- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 23881d09e9f..5c9dcd1f857 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7326,6 +7326,14 @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type) /* tininess for underflow is detected before rounding */ set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status); + /* + * PowerPC propagation rules: + * 1. A if it sNaN or qNaN + * 2. B if it sNaN or qNaN + * A signaling NaN is always silenced before returning it. + */ + set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); + set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status); for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { ppc_spr_t *spr = &env->spr_cb[i]; diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index a0c740e544d..8e3124c11a6 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -404,15 +404,9 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, || defined(TARGET_RISCV) || defined(TARGET_SH4) \ || defined(TARGET_TRICORE) || defined(TARGET_ARM) || defined(TARGET_MIPS) \ || defined(TARGET_LOONGARCH64) || defined(TARGET_HPPA) \ - || defined(TARGET_S390X) + || defined(TARGET_S390X) || defined(TARGET_PPC) g_assert_not_reached(); -#elif defined(TARGET_PPC) || defined(TARGET_M68K) - /* - * PowerPC propagation rules: - * 1. A if it sNaN or qNaN - * 2. B if it sNaN or qNaN - * A signaling NaN is always silenced before returning it. - */ +#elif defined(TARGET_M68K) /* * M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL * 3.4 FLOATING-POINT INSTRUCTION DETAILS From patchwork Fri Oct 25 14:12:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 2002274 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=Bj8wxhAm; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4XZlBr0MZ0z1xwy for ; Sat, 26 Oct 2024 01:13:56 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t4L3y-0004Ai-K5; Fri, 25 Oct 2024 10:13:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t4L3x-00048P-Ba for qemu-ppc@nongnu.org; Fri, 25 Oct 2024 10:13:13 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t4L3p-0007pU-LN for qemu-ppc@nongnu.org; Fri, 25 Oct 2024 10:13:12 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-431695fa98bso20341425e9.3 for ; Fri, 25 Oct 2024 07:13:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729865584; x=1730470384; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XlVlvBeEo5iy1psg/A6qK9cIHAMeC9pxkWdSURdFSQg=; b=Bj8wxhAm9lpUJ1fIxmemV7A4Fhlzh6VxATJrSopcjMESDHrrWek+eh+R60432Qui77 I7+BvAPgiD/BJqkOMReTZ77j1yhCCpcsSU0/iAzE3AI10kYAje5qerfdZh7WhIBC6CZD wX7S6y86FwJ4w6gq7pl6e4jfaWTAHuh831DhRn+GEun/mesvE74+F66eyvv37bcOnd6C qEtNxBk380xAreFiLfRkU/QwRZpTR7sJgsAjlRaF2GbTIm8PMZasS5+BzHgZVvuoqLl3 FLVIuNPmmzXERchBoxiJRJFsg477wo6s5LBuCcnfgT8USyaEj5sCrgELo9Cvl28sCTDU uOOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729865584; x=1730470384; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XlVlvBeEo5iy1psg/A6qK9cIHAMeC9pxkWdSURdFSQg=; b=FU+mz77W5QaTCdqYLvdEjquLMXwndJsR7034ETKfg2FueKNbn+oDdsuDc7cL6rCwsE badJcI8eydNfuaLcRoxpbL5jpAGE1NS7aUrXLt8PdBICtxJ7j2QIuhhpnq/4Pj42p2yd 2xPc4ojaxJTMWmHeREyebxofChBDtMIpYmefmTalD7knmJs69bDtbazWJx7G3nXwPF1I ugQVI2SSHyYda1d8wQJyYnekWyiOSzQ7UcIFsdVNgC4tyM4f/6TJo+0+VN4Pdd2mWWiP cKtn9zQcvJP8nschT4Lk4ZePMdmClSQmzXKMtE16Bf1JQsFO3jxbtaASBL1gl3/yuKwh 24WA== X-Forwarded-Encrypted: i=1; AJvYcCVaPR4uRIsGquN3TNaqetsGy9rpWpBjFo8qFdKYjjm1RoC1ZAo9aGKnhIL870xloQzlwCbGdVTDqw==@nongnu.org X-Gm-Message-State: AOJu0YyEuUSLsyLh1u506tm7zKzxNYidpq/gNPVxuky0bidXkBi45hfx DUZHZFhmkkJ1f3blU5sHruqmxSuX+V4UX1t7pWq/kWzUdXFjhU90bDDU5Ij80aU= X-Google-Smtp-Source: AGHT+IHuVmVPpD0uEEE99zbT59LiMowu3UFFLJFExcm831LgVTVmwcTaFFic7V7R5EgyO383KTowLQ== X-Received: by 2002:a05:600c:34cb:b0:430:5760:2fe with SMTP id 5b1f17b1804b1-4318c73947emr54557345e9.22.1729865584260; Fri, 25 Oct 2024 07:13:04 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4318b57b051sm50104535e9.42.2024.10.25.07.13.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 07:13:03 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Song Gao , Eduardo Habkost , "Edgar E. Iglesias" , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Daniel Henrique Barboza , Yoshinori Sato , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 09/21] target/m68k: Explicitly set 2-NaN propagation rule Date: Fri, 25 Oct 2024 15:12:42 +0100 Message-Id: <20241025141254.2141506-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025141254.2141506-1-peter.maydell@linaro.org> References: <20241025141254.2141506-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Explicitly set the 2-NaN propagation rule on env->fp_status and on the temporary fp_status that we use in frem (since we pass that to a division operation function). Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- target/m68k/cpu.c | 16 ++++++++++++++++ target/m68k/fpu_helper.c | 1 + fpu/softfloat-specialize.c.inc | 19 +------------------ 3 files changed, 18 insertions(+), 18 deletions(-) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 1d49f4cb238..5fe335558aa 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -93,6 +93,22 @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) env->fregs[i].d = nan; } cpu_m68k_set_fpcr(env, 0); + /* + * M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL + * 3.4 FLOATING-POINT INSTRUCTION DETAILS + * If either operand, but not both operands, of an operation is a + * nonsignaling NaN, then that NaN is returned as the result. If both + * operands are nonsignaling NaNs, then the destination operand + * nonsignaling NaN is returned as the result. + * If either operand to an operation is a signaling NaN (SNaN), then the + * SNaN bit is set in the FPSR EXC byte. If the SNaN exception enable bit + * is set in the FPCR ENABLE byte, then the exception is taken and the + * destination is not modified. If the SNaN exception enable bit is not + * set, setting the SNaN bit in the operand to a one converts the SNaN to + * a nonsignaling NaN. The operation then continues as described in the + * preceding paragraph for nonsignaling NaNs. + */ + set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); env->fpsr = 0; /* TODO: We should set PC from the interrupt vector. */ diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c index 8314791f504..a605162b71f 100644 --- a/target/m68k/fpu_helper.c +++ b/target/m68k/fpu_helper.c @@ -620,6 +620,7 @@ void HELPER(frem)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) int sign; /* Calculate quotient directly using round to nearest mode */ + set_float_2nan_prop_rule(float_2nan_prop_ab, &fp_status); set_float_rounding_mode(float_round_nearest_even, &fp_status); set_floatx80_rounding_precision( get_floatx80_rounding_precision(&env->fp_status), &fp_status); diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 8e3124c11a6..226632a4d10 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -404,25 +404,8 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, || defined(TARGET_RISCV) || defined(TARGET_SH4) \ || defined(TARGET_TRICORE) || defined(TARGET_ARM) || defined(TARGET_MIPS) \ || defined(TARGET_LOONGARCH64) || defined(TARGET_HPPA) \ - || defined(TARGET_S390X) || defined(TARGET_PPC) + || defined(TARGET_S390X) || defined(TARGET_PPC) || defined(TARGET_M68K) g_assert_not_reached(); -#elif defined(TARGET_M68K) - /* - * M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL - * 3.4 FLOATING-POINT INSTRUCTION DETAILS - * If either operand, but not both operands, of an operation is a - * nonsignaling NaN, then that NaN is returned as the result. If both - * operands are nonsignaling NaNs, then the destination operand - * nonsignaling NaN is returned as the result. - * If either operand to an operation is a signaling NaN (SNaN), then the - * SNaN bit is set in the FPSR EXC byte. If the SNaN exception enable bit - * is set in the FPCR ENABLE byte, then the exception is taken and the - * destination is not modified. If the SNaN exception enable bit is not - * set, setting the SNaN bit in the operand to a one converts the SNaN to - * a nonsignaling NaN. The operation then continues as described in the - * preceding paragraph for nonsignaling NaNs. - */ - rule = float_2nan_prop_ab; #elif defined(TARGET_SPARC) /* Prefer SNaN over QNaN, order B then A. */ rule = float_2nan_prop_s_ba; From patchwork Fri Oct 25 14:12:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 2002313 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=lkAQl2ea; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4XZlHd401jz1xtp for ; Sat, 26 Oct 2024 01:18:05 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t4L46-0004Jt-K7; Fri, 25 Oct 2024 10:13:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t4L3y-0004AO-KA for qemu-ppc@nongnu.org; Fri, 25 Oct 2024 10:13:14 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t4L3q-0007py-FR for qemu-ppc@nongnu.org; Fri, 25 Oct 2024 10:13:14 -0400 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-431688d5127so20545415e9.0 for ; Fri, 25 Oct 2024 07:13:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729865585; x=1730470385; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LWQTkVIYoMx387TeXW3tDVaYyEBBg7QXyfQFYBePRB4=; b=lkAQl2earbkay8EYGVF02u13RWSiTiD0htE/yj8EOZ8ReUAM4/U91P8KDfFobko5la CPrcz2i3MdCG0iZCkI5mmv9xZZaeRB1FHD/Rsn72T4WFWyOwZkCkGVj/HNXYXEvC+RZd AtGE9Elskx0r4978Zhm2KD1y4NvCbuJ7sTd4hRgOsPH/OL++YSb8k2DlAfsu6TIlC+FT tURhSW9NsqeNVeu9JezMvxUCl5+iPTPUPdV25YCUBgqAQyWaZUr6FF9ZIZCOHwPv9rjd EJkMTY3EXCxgE6lV9x0oVPwSzFtBe2a9SbmrFhKpkN8zubZB+IbvU8uxzCcd3IxilvhE cLoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729865585; x=1730470385; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LWQTkVIYoMx387TeXW3tDVaYyEBBg7QXyfQFYBePRB4=; b=Laa4yZGKv1/SYmD/p+hoCGLtBoi2WF4Ojf9rQG5JgVyH0XIeJAIk+UrT7AL/mepMgQ KtQCBYk0XheOD+0oX3NebZzKpyxmuDBxpMzn5JM4VdWRC1S2Qq3JFgFJ2ZRDl/o86Unn tWrXHrDZdE+/2BczL9MYQ5CfaCgpx5ek5Sa2cTWQp/1gCLqfw+Z0H1SAqGsSMQvx7cHN AgSEWWJQDVKkFYydm1n3u6Thd0kYulnvk+suoClvJu5tNewmzxSJwdTm+9wJcTFBQ+B+ NP2zxkFjgbphSpJin+jcE9fylsO6HPfRnj/IrP8b1DfUsvEzx7nGmiqG0jMuLldWQMv1 fvQA== X-Forwarded-Encrypted: i=1; AJvYcCXVcZaJe8vQ3QNwiSlPMiE8qgGTuRq0wzfG7Yn+YteTSbxpg18/hlNGQYq26ChXpImZhE4Xj6Da6A==@nongnu.org X-Gm-Message-State: AOJu0YwS7YavF6ZdCPlQkwbsK5LZAGm4atLCVN6uWkqy6ke+DNwpckvI HCgfyybuXjjLjUrL5IlutBphKzSmpMaTaNKofxWkw9kMLhAHgd6Tuvt6L5fVKPg= X-Google-Smtp-Source: AGHT+IHSPtYopQuk24YCPV4j/3lLijdSJYW/1g+JfHiVm9QFLT6tmDk6VCMAGDw3f+ncfW6XOWoYQw== X-Received: by 2002:a05:600c:6d19:b0:425:7bbf:fd07 with SMTP id 5b1f17b1804b1-4318c8cd0bamr52618515e9.5.1729865585055; Fri, 25 Oct 2024 07:13:05 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4318b57b051sm50104535e9.42.2024.10.25.07.13.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 07:13:04 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Song Gao , Eduardo Habkost , "Edgar E. Iglesias" , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Daniel Henrique Barboza , Yoshinori Sato , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 10/21] target/m68k: Initialize float_status fields in gdb set/get functions Date: Fri, 25 Oct 2024 15:12:43 +0100 Message-Id: <20241025141254.2141506-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025141254.2141506-1-peter.maydell@linaro.org> References: <20241025141254.2141506-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org In cf_fpu_gdb_get_reg() and cf_fpu_gdb_set_reg() we use a temporary float_status variable to pass to floatx80_to_float64() and float64_to_floatx80(), but we don't initialize it, meaning that those functions could access uninitialized data. Zero-init the structs. (We don't need to set a NaN-propagation rule here because we don't use these with a 2-argument fpu operation.) Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- Spotted by code-inspection while I was doing the 2-NaN propagation patches. --- target/m68k/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 9d3db8419de..9bfc6ae97c0 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -36,7 +36,7 @@ static int cf_fpu_gdb_get_reg(CPUState *cs, GByteArray *mem_buf, int n) CPUM68KState *env = &cpu->env; if (n < 8) { - float_status s; + float_status s = {}; return gdb_get_reg64(mem_buf, floatx80_to_float64(env->fregs[n].d, &s)); } switch (n) { @@ -56,7 +56,7 @@ static int cf_fpu_gdb_set_reg(CPUState *cs, uint8_t *mem_buf, int n) CPUM68KState *env = &cpu->env; if (n < 8) { - float_status s; + float_status s = {}; env->fregs[n].d = float64_to_floatx80(ldq_be_p(mem_buf), &s); return 8; } From patchwork Fri Oct 25 14:12:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 2002284 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=CLdBiU/1; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4XZlCy4LPzz1xwy for ; Sat, 26 Oct 2024 01:14:54 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t4L4B-0004Pp-GG; Fri, 25 Oct 2024 10:13:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t4L3z-0004CA-Ua for qemu-ppc@nongnu.org; Fri, 25 Oct 2024 10:13:15 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t4L3r-0007qb-WB for qemu-ppc@nongnu.org; Fri, 25 Oct 2024 10:13:15 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-431548bd1b4so20391465e9.3 for ; Fri, 25 Oct 2024 07:13:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729865586; x=1730470386; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jjOM3QYK37qULOvoMpKikOAGRTQIulU/PhbW7+12E+A=; b=CLdBiU/1Fe8HGeL5xo32mAHXZwY5KCAkRLjHEkm3BRA+m/gnZH6OHrvtNw7cziYpaV b0cp29vrbJL8opXePKe9Fsqy20IZpfaGVEh8Sosq/1fBUW+Mrrds6xLlARLRBlDFht8k LW/2kU35JWF4kHP6tpf4cFzCUlFuGZMCMJfINohy8W18Ry5NBbhJuzpipdgcQW3BPdoP uzFxmaPHwuiHNEQjVyUhdQ7OPjS14voWjtPZOMMkX6ZPM4Y/fYMw+2IyaRy2TCiVCUSb +EHo2chM0Paf9j1pJbx63PPimIkkwzi6l7Wu2mRGoIpvFonGSbSRnaKb5H2uU/BkXj4z fpDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729865586; x=1730470386; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jjOM3QYK37qULOvoMpKikOAGRTQIulU/PhbW7+12E+A=; b=YtFuCIsyDzMksNoz1anRlH4jSxHEI5xJTSQjwU3NyJpn8jdmiOnHYAthivwUvuLXUw mayNjyrhfqk4zBZL3JpA7t6zLU4iSffrM2gBkaJA/Alz3+/NfFpuo+hzoCbdRUQeMBjR jPab0p/Ge2/cBPjRpxsny8Nm8MVrJgFueIZlOrKppt7YO6U/cuv6VcLVmF8exvsIeuBo 63MIRHWN4CH3OR+80238mnJVsZtC9Q+TuIBIMJevhuvDV+zAyD+LRRJDAze+5Ulm//As 8B4V5jdBUANildpgS2Wn2+LzMxRKQSQl0Edufne9gKlA1HuU4k5IXusCa6DFCLdko5RZ hW4A== X-Forwarded-Encrypted: i=1; AJvYcCXw5pomaOG8bggdTT7A1hOhDAeZgSqb91riQWcDn3Bvp487JHxaxtMy8PJWbXCGF4gNWY2N/YFfaw==@nongnu.org X-Gm-Message-State: AOJu0YyY2CjDmEsB8Yf6kIswAcWizmrFSqVzdIFL581gVzB49c/fqXNJ GAcBYYY15EFf+n+ZglwFTwmqfjS39D9+R1pezi03E3rr6Lp08DQ3KsJbFT5eP6M= X-Google-Smtp-Source: AGHT+IElcpmJ1LU46tPdnbNHuTc3BFBmHYJc+kaPi4JdihFLfSRZx1lONZoPeZB6hUVJoUrQ/Pjf/w== X-Received: by 2002:a05:600c:5118:b0:431:3a6d:b84a with SMTP id 5b1f17b1804b1-431841e12cdmr75651695e9.4.1729865585974; Fri, 25 Oct 2024 07:13:05 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4318b57b051sm50104535e9.42.2024.10.25.07.13.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 07:13:05 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Song Gao , Eduardo Habkost , "Edgar E. Iglesias" , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Daniel Henrique Barboza , Yoshinori Sato , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 11/21] target/sparc: Move cpu_put_fsr(env, 0) call to reset Date: Fri, 25 Oct 2024 15:12:44 +0100 Message-Id: <20241025141254.2141506-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025141254.2141506-1-peter.maydell@linaro.org> References: <20241025141254.2141506-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Currently we call cpu_put_fsr(0) in sparc_cpu_realizefn(), which initializes various fields in the CPU struct: * fsr_cexc_ftt * fcc[] * fsr_qne * fsr It also sets the rounding mode in env->fp_status. This is largely pointless, because when we later reset the CPU this will zero out all the fields up until the "end_reset_fields" label, which includes all of these (but not fp_status!) Move the cpu_put_fsr(env, 0) call to reset, because that expresses the logical requirement: we want to reset FSR to 0 on every reset. This isn't a behaviour change because the fields are all zero anyway. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- target/sparc/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 54cb269e0af..e7f4068a162 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -76,6 +76,7 @@ static void sparc_cpu_reset_hold(Object *obj, ResetType type) env->npc = env->pc + 4; #endif env->cache_control = 0; + cpu_put_fsr(env, 0); } #ifndef CONFIG_USER_ONLY @@ -805,7 +806,6 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) env->version |= env->def.maxtl << 8; env->version |= env->def.nwindows - 1; #endif - cpu_put_fsr(env, 0); cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { From patchwork Fri Oct 25 14:12:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 2002299 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=VkHiDTtk; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4XZlF11Bchz1xxG for ; Sat, 26 Oct 2024 01:15:49 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t4L45-0004IM-Pr; Fri, 25 Oct 2024 10:13:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t4L41-0004D0-5F for qemu-ppc@nongnu.org; Fri, 25 Oct 2024 10:13:17 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t4L3s-0007qy-Ka for qemu-ppc@nongnu.org; Fri, 25 Oct 2024 10:13:16 -0400 Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-37d8901cb98so2119021f8f.0 for ; Fri, 25 Oct 2024 07:13:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729865587; x=1730470387; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+3N7Gh5ykD6QxUXP4fouNsk3DmkKRJ2QzcoWCfXISHI=; b=VkHiDTtkl6/xjD7vf7wRv6vPMshw+ZerzlexMzsF9ivpAYZdnYNEmlD5fYaA1UivxW 2EppflRwN20n291OyRg4MJcQTdRfD47bHJECxXK4LRCht5gCnfrWXE+qEcp+qW6pyfd1 k+NJB5/hfscgXIxmGdRVVaYA/HDNHWWmwTztGUpC+5jgT9xPgv4B0hYPNCf1dC8pW4Pb xKpAKpzvanmJJ++seOIv2/o7VS3uirtsMw+yJWmV1VRD8GKYJO2PoTLvcDNiuMIL8wEo OosJYc0baW5VNq64Unsux3tE6P9ya706IOffWX23HlAcfpuz03NFFMBkNFPmPkN+s15k +5HQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729865587; x=1730470387; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+3N7Gh5ykD6QxUXP4fouNsk3DmkKRJ2QzcoWCfXISHI=; b=Z89psNwGoXUCe4s+cnhiO8PDrBT0H/myw0q6aE7cpe3kM3vEiBiOvK/WKJCbO6DJME z5VIGCXZ/hTh2yizM8q+8syFSV08oVRswfvRrMELvHU8xD0kkIHWLXN8POzTSH0EYsrF hGMAVUY+9vyY2AfKQTbDhcc7mR/4076OiWXjKnkkc4y/2k39kIPEoxiuNlsCIVH10sFZ /wGHvcQ8+/f88dWDNj+5NwIJ5rTSAV2MYxytXcxZraKCxQsBjnDT0KXFi2WDyZ1erJOj y2X6MJsbvlHNPt9zDj+sM9/x0wj5OSh5wAR7YfihSM3a406SCLO+PMn2T1sI81hjDNqp B0IQ== X-Forwarded-Encrypted: i=1; AJvYcCUog2NlxgO7YiT+Jui7+iiv12h5ZfmzhRtdvpQrOoR+e2j5jcDGLQphPnKIl5oHeIhCZlZ8bZSfgA==@nongnu.org X-Gm-Message-State: AOJu0YznDKqZWWwBcunm1h1yWsOoshUfOlj9QqsVAsAW5m0BFtTKR6e2 +J/0xNjGpi4XgyMePKnWTnf4x4766wHEh9qix91mFBPzMc6B2GyfPh2TcLBWO1c= X-Google-Smtp-Source: AGHT+IFELKEdswjTGifEl1YHesJLSbvwyrbGh5IhwQ+SHELG0FMMmzYmcW2PCs8GDLSYanzPnyZ5mg== X-Received: by 2002:a05:6000:d0b:b0:374:bd00:d1e with SMTP id ffacd0b85a97d-3803abc2879mr4856955f8f.3.1729865586918; Fri, 25 Oct 2024 07:13:06 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4318b57b051sm50104535e9.42.2024.10.25.07.13.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 07:13:06 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Song Gao , Eduardo Habkost , "Edgar E. Iglesias" , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Daniel Henrique Barboza , Yoshinori Sato , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 12/21] target/sparc: Explicitly set 2-NaN propagation rule Date: Fri, 25 Oct 2024 15:12:45 +0100 Message-Id: <20241025141254.2141506-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025141254.2141506-1-peter.maydell@linaro.org> References: <20241025141254.2141506-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Set the NaN propagation rule explicitly in the float_status words we use. Signed-off-by: Peter Maydell Acked-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- target/sparc/cpu.c | 8 ++++++++ target/sparc/fop_helper.c | 10 ++++++++-- fpu/softfloat-specialize.c.inc | 6 ++---- 3 files changed, 18 insertions(+), 6 deletions(-) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index e7f4068a162..dd7af86de73 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -26,6 +26,7 @@ #include "hw/qdev-properties.h" #include "qapi/visitor.h" #include "tcg/tcg.h" +#include "fpu/softfloat.h" //#define DEBUG_FEATURES @@ -807,6 +808,13 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) env->version |= env->def.nwindows - 1; #endif + /* + * Prefer SNaN over QNaN, order B then A. It's OK to do this in realize + * rather than reset, because fp_status is after 'end_reset_fields' in + * the CPU state struct so it won't get zeroed on reset. + */ + set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status); + cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index b6692382b3b..6f9ccc008a0 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -497,7 +497,10 @@ uint32_t helper_flcmps(float32 src1, float32 src2) * Perform the comparison with a dummy fp environment. */ float_status discard = { }; - FloatRelation r = float32_compare_quiet(src1, src2, &discard); + FloatRelation r; + + set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard); + r = float32_compare_quiet(src1, src2, &discard); switch (r) { case float_relation_equal: @@ -518,7 +521,10 @@ uint32_t helper_flcmps(float32 src1, float32 src2) uint32_t helper_flcmpd(float64 src1, float64 src2) { float_status discard = { }; - FloatRelation r = float64_compare_quiet(src1, src2, &discard); + FloatRelation r; + + set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard); + r = float64_compare_quiet(src1, src2, &discard); switch (r) { case float_relation_equal: diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 226632a4d10..8bc95187178 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -404,11 +404,9 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, || defined(TARGET_RISCV) || defined(TARGET_SH4) \ || defined(TARGET_TRICORE) || defined(TARGET_ARM) || defined(TARGET_MIPS) \ || defined(TARGET_LOONGARCH64) || defined(TARGET_HPPA) \ - || defined(TARGET_S390X) || defined(TARGET_PPC) || defined(TARGET_M68K) + || defined(TARGET_S390X) || defined(TARGET_PPC) || defined(TARGET_M68K) \ + || defined(TARGET_SPARC) g_assert_not_reached(); -#elif defined(TARGET_SPARC) - /* Prefer SNaN over QNaN, order B then A. */ - rule = float_2nan_prop_s_ba; #elif defined(TARGET_XTENSA) /* * Xtensa has two NaN propagation modes. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4318b57b051sm50104535e9.42.2024.10.25.07.13.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 07:13:07 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Song Gao , Eduardo Habkost , "Edgar E. Iglesias" , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Daniel Henrique Barboza , Yoshinori Sato , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 13/21] target/xtensa: Factor out calls to set_use_first_nan() Date: Fri, 25 Oct 2024 15:12:46 +0100 Message-Id: <20241025141254.2141506-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025141254.2141506-1-peter.maydell@linaro.org> References: <20241025141254.2141506-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org In xtensa we currently call set_use_first_nan() in a lot of places where we want to switch the NaN-propagation handling. We're about to change the softfloat API we use to do that, so start by factoring all the calls out into a single xtensa_use_first_nan() function. The bulk of this change was done with sed -i -e 's/set_use_first_nan(\([^,]*\),[^)]*)/xtensa_use_first_nan(env, \1)/' target/xtensa/fpu_helper.c Signed-off-by: Peter Maydell Reviewed-by: Max Filippov Reviewed-by: Richard Henderson --- target/xtensa/cpu.h | 6 ++++++ target/xtensa/cpu.c | 2 +- target/xtensa/fpu_helper.c | 33 +++++++++++++++++++-------------- 3 files changed, 26 insertions(+), 15 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 9f2341d8563..77e48eef19c 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -802,4 +802,10 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc, XtensaCPU *xtensa_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk); +/* + * Set the NaN propagation rule for future FPU operations: + * use_first is true to pick the first NaN as the result if both + * inputs are NaNs, false to pick the second. + */ +void xtensa_use_first_nan(CPUXtensaState *env, bool use_first); #endif diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index a08c7a0b1f2..6f9039abaee 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -134,7 +134,7 @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type) cs->halted = env->runstall; #endif set_no_signaling_nans(!dfpu, &env->fp_status); - set_use_first_nan(!dfpu, &env->fp_status); + xtensa_use_first_nan(env, !dfpu); } static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model) diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c index 381e83ded83..50a5efa65e2 100644 --- a/target/xtensa/fpu_helper.c +++ b/target/xtensa/fpu_helper.c @@ -57,6 +57,11 @@ static const struct { { XTENSA_FP_V, float_flag_invalid, }, }; +void xtensa_use_first_nan(CPUXtensaState *env, bool use_first) +{ + set_use_first_nan(use_first, &env->fp_status); +} + void HELPER(wur_fpu2k_fcr)(CPUXtensaState *env, uint32_t v) { static const int rounding_mode[] = { @@ -171,87 +176,87 @@ float32 HELPER(fpu2k_msub_s)(CPUXtensaState *env, float64 HELPER(add_d)(CPUXtensaState *env, float64 a, float64 b) { - set_use_first_nan(true, &env->fp_status); + xtensa_use_first_nan(env, true); return float64_add(a, b, &env->fp_status); } float32 HELPER(add_s)(CPUXtensaState *env, float32 a, float32 b) { - set_use_first_nan(env->config->use_first_nan, &env->fp_status); + xtensa_use_first_nan(env, env->config->use_first_nan); return float32_add(a, b, &env->fp_status); } float64 HELPER(sub_d)(CPUXtensaState *env, float64 a, float64 b) { - set_use_first_nan(true, &env->fp_status); + xtensa_use_first_nan(env, true); return float64_sub(a, b, &env->fp_status); } float32 HELPER(sub_s)(CPUXtensaState *env, float32 a, float32 b) { - set_use_first_nan(env->config->use_first_nan, &env->fp_status); + xtensa_use_first_nan(env, env->config->use_first_nan); return float32_sub(a, b, &env->fp_status); } float64 HELPER(mul_d)(CPUXtensaState *env, float64 a, float64 b) { - set_use_first_nan(true, &env->fp_status); + xtensa_use_first_nan(env, true); return float64_mul(a, b, &env->fp_status); } float32 HELPER(mul_s)(CPUXtensaState *env, float32 a, float32 b) { - set_use_first_nan(env->config->use_first_nan, &env->fp_status); + xtensa_use_first_nan(env, env->config->use_first_nan); return float32_mul(a, b, &env->fp_status); } float64 HELPER(madd_d)(CPUXtensaState *env, float64 a, float64 b, float64 c) { - set_use_first_nan(env->config->use_first_nan, &env->fp_status); + xtensa_use_first_nan(env, env->config->use_first_nan); return float64_muladd(b, c, a, 0, &env->fp_status); } float32 HELPER(madd_s)(CPUXtensaState *env, float32 a, float32 b, float32 c) { - set_use_first_nan(env->config->use_first_nan, &env->fp_status); + xtensa_use_first_nan(env, env->config->use_first_nan); return float32_muladd(b, c, a, 0, &env->fp_status); } float64 HELPER(msub_d)(CPUXtensaState *env, float64 a, float64 b, float64 c) { - set_use_first_nan(env->config->use_first_nan, &env->fp_status); + xtensa_use_first_nan(env, env->config->use_first_nan); return float64_muladd(b, c, a, float_muladd_negate_product, &env->fp_status); } float32 HELPER(msub_s)(CPUXtensaState *env, float32 a, float32 b, float32 c) { - set_use_first_nan(env->config->use_first_nan, &env->fp_status); + xtensa_use_first_nan(env, env->config->use_first_nan); return float32_muladd(b, c, a, float_muladd_negate_product, &env->fp_status); } float64 HELPER(mkdadj_d)(CPUXtensaState *env, float64 a, float64 b) { - set_use_first_nan(true, &env->fp_status); + xtensa_use_first_nan(env, true); return float64_div(b, a, &env->fp_status); } float32 HELPER(mkdadj_s)(CPUXtensaState *env, float32 a, float32 b) { - set_use_first_nan(env->config->use_first_nan, &env->fp_status); + xtensa_use_first_nan(env, env->config->use_first_nan); return float32_div(b, a, &env->fp_status); } float64 HELPER(mksadj_d)(CPUXtensaState *env, float64 v) { - set_use_first_nan(true, &env->fp_status); + xtensa_use_first_nan(env, true); return float64_sqrt(v, &env->fp_status); } float32 HELPER(mksadj_s)(CPUXtensaState *env, float32 v) { - set_use_first_nan(env->config->use_first_nan, &env->fp_status); + xtensa_use_first_nan(env, env->config->use_first_nan); return float32_sqrt(v, &env->fp_status); } From patchwork Fri Oct 25 14:12:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 2002293 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4318b57b051sm50104535e9.42.2024.10.25.07.13.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 07:13:08 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Song Gao , Eduardo Habkost , "Edgar E. Iglesias" , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Daniel Henrique Barboza , Yoshinori Sato , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 14/21] target/xtensa: Explicitly set 2-NaN propagation rule Date: Fri, 25 Oct 2024 15:12:47 +0100 Message-Id: <20241025141254.2141506-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025141254.2141506-1-peter.maydell@linaro.org> References: <20241025141254.2141506-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Set the NaN propagation rule explicitly in xtensa_use_first_nan(). (When we convert the softfloat pickNaNMulAdd routine to also select a NaN propagation rule at runtime, we will be able to remove the use_first_nan flag because the propagation rules will handle everything.) Signed-off-by: Peter Maydell Reviewed-by: Max Filippov Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/xtensa/fpu_helper.c | 2 ++ fpu/softfloat-specialize.c.inc | 12 +----------- 2 files changed, 3 insertions(+), 11 deletions(-) diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c index 50a5efa65e2..f2d212d05df 100644 --- a/target/xtensa/fpu_helper.c +++ b/target/xtensa/fpu_helper.c @@ -60,6 +60,8 @@ static const struct { void xtensa_use_first_nan(CPUXtensaState *env, bool use_first) { set_use_first_nan(use_first, &env->fp_status); + set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba, + &env->fp_status); } void HELPER(wur_fpu2k_fcr)(CPUXtensaState *env, uint32_t v) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 8bc95187178..b050c5eb04a 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -405,18 +405,8 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, || defined(TARGET_TRICORE) || defined(TARGET_ARM) || defined(TARGET_MIPS) \ || defined(TARGET_LOONGARCH64) || defined(TARGET_HPPA) \ || defined(TARGET_S390X) || defined(TARGET_PPC) || defined(TARGET_M68K) \ - || defined(TARGET_SPARC) + || defined(TARGET_SPARC) || defined(TARGET_XTENSA) g_assert_not_reached(); -#elif defined(TARGET_XTENSA) - /* - * Xtensa has two NaN propagation modes. - * Which one is active is controlled by float_status::use_first_nan. - */ - if (status->use_first_nan) { - rule = float_2nan_prop_ab; - } else { - rule = float_2nan_prop_ba; - } #else rule = float_2nan_prop_x87; #endif From patchwork Fri Oct 25 14:12:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 2002290 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=SS6Q9Fp/; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4318b57b051sm50104535e9.42.2024.10.25.07.13.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 07:13:09 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Song Gao , Eduardo Habkost , "Edgar E. Iglesias" , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Daniel Henrique Barboza , Yoshinori Sato , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 15/21] target/i386: Set 2-NaN propagation rule explicitly Date: Fri, 25 Oct 2024 15:12:48 +0100 Message-Id: <20241025141254.2141506-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025141254.2141506-1-peter.maydell@linaro.org> References: <20241025141254.2141506-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Set the NaN propagation rule explicitly for the float_status words used in the x86 target. This is a no-behaviour-change commit, so we retain the existing behaviour of using the x87-style "prefer QNaN over SNaN, then prefer the NaN with the larger significand" for MMX and SSE. This is however not the documented hardware behaviour, so we leave a TODO note about what we should be doing instead. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/i386/cpu.h | 3 +++ target/i386/cpu.c | 4 ++++ target/i386/tcg/fpu_helper.c | 40 ++++++++++++++++++++++++++++++++++ fpu/softfloat-specialize.c.inc | 3 ++- 4 files changed, 49 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 74886d1580f..43ba62e92d3 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2562,6 +2562,9 @@ static inline bool cpu_vmx_maybe_enabled(CPUX86State *env) int get_pg_mode(CPUX86State *env); /* fpu_helper.c */ + +/* Set all non-runtime-variable float_status fields to x86 handling */ +void cpu_init_fp_statuses(CPUX86State *env); void update_fp_status(CPUX86State *env); void update_mxcsr_status(CPUX86State *env); void update_mxcsr_from_sse_status(CPUX86State *env); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1ff1af032ea..e9260fbc654 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7083,6 +7083,10 @@ static void x86_cpu_reset_hold(Object *obj, ResetType type) memset(env, 0, offsetof(CPUX86State, end_reset_fields)); + if (tcg_enabled()) { + cpu_init_fp_statuses(env); + } + env->old_exception = -1; /* init to reset state */ diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index e1b850f3fc2..53b49bb2977 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -135,6 +135,46 @@ static void fpu_set_exception(CPUX86State *env, int mask) } } +void cpu_init_fp_statuses(CPUX86State *env) +{ + /* + * Initialise the non-runtime-varying fields of the various + * float_status words to x86 behaviour. This must be called at + * CPU reset because the float_status words are in the + * "zeroed on reset" portion of the CPU state struct. + * Fields in float_status that vary under guest control are set + * via the codepath for setting that register, eg cpu_set_fpuc(). + */ + /* + * Use x87 NaN propagation rules: + * SNaN + QNaN => return the QNaN + * two SNaNs => return the one with the larger significand, silenced + * two QNaNs => return the one with the larger significand + * SNaN and a non-NaN => return the SNaN, silenced + * QNaN and a non-NaN => return the QNaN + * + * If we get down to comparing significands and they are the same, + * return the NaN with the positive sign bit (if any). + */ + set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status); + /* + * TODO: These are incorrect: the x86 Software Developer's Manual vol 1 + * section 4.8.3.5 "Operating on SNaNs and QNaNs" says that the + * "larger significand" behaviour is only used for x87 FPU operations. + * For SSE the required behaviour is to always return the first NaN, + * which is float_2nan_prop_ab. + * + * mmx_status is used only for the AMD 3DNow! instructions, which + * are documented in the "3DNow! Technology Manual" as not supporting + * NaNs or infinities as inputs. The result of passing two NaNs is + * documented as "undefined", so we can do what we choose. + * (Strictly there is some behaviour we don't implement correctly + * for these "unsupported" NaN and Inf values, like "NaN * 0 == 0".) + */ + set_float_2nan_prop_rule(float_2nan_prop_x87, &env->mmx_status); + set_float_2nan_prop_rule(float_2nan_prop_x87, &env->sse_status); +} + static inline uint8_t save_exception_flags(CPUX86State *env) { uint8_t old_flags = get_float_exception_flags(&env->fp_status); diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index b050c5eb04a..77ebc8216f6 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -405,7 +405,8 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, || defined(TARGET_TRICORE) || defined(TARGET_ARM) || defined(TARGET_MIPS) \ || defined(TARGET_LOONGARCH64) || defined(TARGET_HPPA) \ || defined(TARGET_S390X) || defined(TARGET_PPC) || defined(TARGET_M68K) \ - || defined(TARGET_SPARC) || defined(TARGET_XTENSA) + || defined(TARGET_SPARC) || defined(TARGET_XTENSA) \ + || defined(TARGET_I386) g_assert_not_reached(); #else rule = float_2nan_prop_x87; From patchwork Fri Oct 25 14:12:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 2002280 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=F7nS6GVr; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4XZlCV1qfDz1xwy for ; Sat, 26 Oct 2024 01:14:23 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t4L4F-0004Tn-7W; Fri, 25 Oct 2024 10:13:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t4L44-0004I4-VZ for qemu-ppc@nongnu.org; Fri, 25 Oct 2024 10:13:21 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t4L3v-0007tO-Qq for qemu-ppc@nongnu.org; Fri, 25 Oct 2024 10:13:20 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-4316f3d3c21so20263975e9.3 for ; Fri, 25 Oct 2024 07:13:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729865590; x=1730470390; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=R0KwrJ+RLRqyfxTos/cR3Np44ABB8RBfSuYyJrILdGI=; b=F7nS6GVrZ6Ud5EY3wzWxnRC3v0jBOi+8Gh0/KNexEOm8jNQ6jjTPC0oLlfO+QDfiUl Ayke1GDj7kHX9yRk7QdjRSocLxQDWolEDWQnWy3jvo2kvZ2jVwThVF1cyyvb9Z+aZ6VW cXpI3vbr84tnrbXSMKiXwlG90xUg/E0Kaoe7cQFlk6mwfAYzGywW71enQCT7Nc0naleU XfgyC5dHqI5k0JHMhNvobWEg1gW3NFx2/Ixh4ZJJKmkZS98zWCHq0tlx7vigM25tx2cK b4VzTR0LaG3AyTwOUBDarPxH/keGoVFYN0tmzK/GDHpAVBeRl4x/7Rf6ZDEK8Zk1Nsjz BeDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729865590; x=1730470390; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=R0KwrJ+RLRqyfxTos/cR3Np44ABB8RBfSuYyJrILdGI=; b=ZMW7hQyA4Vuc8sHPUSnL9pkjnDpdmpZgXJqFsDGJzAFNWmh26CSybupjpS6LcGtUIt 2x/BYzFQ7R/OL/sQj30/ujsNid4ACCebQ82REGJs6tys3unp/Se9VY5ucTiOVy6siAB9 0iyFX/6ZpSSp6A8kpef9cC+hPIam/zezoSSFckmPmWWom02m985TuwJIA/8/1HZVfq74 Tty9gwNh7M6DpXrtM+6bVqIRvyE556yFbqGdeXKI+nIUdqgTBmSuozxvE+pHuqcIVgwI mhLm9Kua5qMp++QzE+eutkCiOFvhD4jvozaHtZD8+bGBDp4llOEQGvDXXCCS4qIB/utA MvbQ== X-Forwarded-Encrypted: i=1; AJvYcCUCAvnAvRUp3+PkkinOhB3z0+Vc8NZDY2lQYZeeTRTDYBv56SKnZoixVdMqBkHuUk5XSuvAwzgGRg==@nongnu.org X-Gm-Message-State: AOJu0Yx4u2AQImQbHnAXSA/VhDO0LXDVn7J5SIz0liwgRKbm24roEKwd CUwCe5O06jHAzjOCLZMilfUeFXrvfC4W9mu6IdhluQIlc2QR7A2GvMf6WJb+9/A= X-Google-Smtp-Source: AGHT+IElscYFzJMkYmD7qnmfjnyWZqUI37VMxIDiiFWHpHvVdX7AL5ahkCq804b4/QejsLD1QmJqwg== X-Received: by 2002:a05:600c:1e08:b0:431:2b66:44f7 with SMTP id 5b1f17b1804b1-431841a5fe1mr81921395e9.31.1729865590281; Fri, 25 Oct 2024 07:13:10 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4318b57b051sm50104535e9.42.2024.10.25.07.13.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 07:13:10 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Song Gao , Eduardo Habkost , "Edgar E. Iglesias" , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Daniel Henrique Barboza , Yoshinori Sato , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 16/21] target/alpha: Explicitly set 2-NaN propagation rule Date: Fri, 25 Oct 2024 15:12:49 +0100 Message-Id: <20241025141254.2141506-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025141254.2141506-1-peter.maydell@linaro.org> References: <20241025141254.2141506-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Set the NaN propagation rule explicitly for the float_status word used in this target. This is a no-behaviour-change commit, so we retain the existing behaviour of x87-style pick-largest-significand NaN propagation. This is however not the architecturally correct handling, so we leave a TODO note to that effect. We also leave a TODO note pointing out that all this code in the cpu initfn (including the existing setting up of env->flags and the FPCR) should be in a currently non-existent CPU reset function. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/alpha/cpu.c | 11 +++++++++++ fpu/softfloat-specialize.c.inc | 2 +- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 9db1dffc03e..5d75c941f7a 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -24,6 +24,7 @@ #include "qemu/qemu-print.h" #include "cpu.h" #include "exec/exec-all.h" +#include "fpu/softfloat.h" static void alpha_cpu_set_pc(CPUState *cs, vaddr value) @@ -187,7 +188,17 @@ static void alpha_cpu_initfn(Object *obj) { CPUAlphaState *env = cpu_env(CPU(obj)); + /* TODO all this should be done in reset, not init */ + env->lock_addr = -1; + + /* + * TODO: this is incorrect. The Alpha Architecture Handbook version 4 + * describes NaN propagation in section 4.7.10.4. We should prefer + * the operand in Fb (whether it is a QNaN or an SNaN), then the + * operand in Fa. That is float_2nan_prop_ba. + */ + set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status); #if defined(CONFIG_USER_ONLY) env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN; cpu_alpha_store_fpcr(env, (uint64_t)(FPCR_INVD | FPCR_DZED | FPCR_OVFD diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 77ebc8216f6..a5c3e2b8de5 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -406,7 +406,7 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, || defined(TARGET_LOONGARCH64) || defined(TARGET_HPPA) \ || defined(TARGET_S390X) || defined(TARGET_PPC) || defined(TARGET_M68K) \ || defined(TARGET_SPARC) || defined(TARGET_XTENSA) \ - || defined(TARGET_I386) + || defined(TARGET_I386) || defined(TARGET_ALPHA) g_assert_not_reached(); #else rule = float_2nan_prop_x87; From patchwork Fri Oct 25 14:12:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 2002285 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=pca3dyA0; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4XZlD05H8zz1xwy for ; Sat, 26 Oct 2024 01:14:56 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t4L4B-0004Pw-JR; Fri, 25 Oct 2024 10:13:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t4L47-0004L5-Od for qemu-ppc@nongnu.org; Fri, 25 Oct 2024 10:13:24 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t4L3x-0007to-3j for qemu-ppc@nongnu.org; Fri, 25 Oct 2024 10:13:23 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-43169902057so20482155e9.0 for ; Fri, 25 Oct 2024 07:13:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729865591; x=1730470391; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mCkNXmPfCnwutAypvXIltADsiovUrFYgTsHQnSnupeI=; b=pca3dyA0DUBtE/UZ+t+nbehNTEGr0PcZJrjxxZux1SDTYiAoHoVAxirQb0lEFRSTff M+8TK5ftfu2AmIzHGAhANFHIrybvu/rbdrR9iOX0YWZlIF2AVN8q1LbpyF1ChOaqTmB9 +kqJZ+sv6Tkhb8s1q3WrbKB63JN2xYe5z05Lb1fRA5NHFRZhWw2b3UPwBcaYt7h8zmVg Bv1Ql4ZXRhiQg7QJfpU6WQNk2nfhw39o9Et1J2KKsSL0CCXnzb0G+A++hOshHsN9w/wI /ya39ESiS9Z6+iGx5iL55AYEG+E4NOlZAnMyy7pnDlNXSFGLHH7llbuXHi9V36j8GEYc 3IJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729865591; x=1730470391; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mCkNXmPfCnwutAypvXIltADsiovUrFYgTsHQnSnupeI=; b=aCethh7r9WJHhKSv1j16UGfS6iV62Cqkj5Emb+6KV+jZtkkMQkehCnNpW0PCYlbrZz K9tHG5MGdBsLHRUTsEJ69z7wfzPuf/u9e1Jkcx3FYxyfUo0n6EP3dngodZ8Y/nVmSDFQ kFaEkqmJv4scnGjPAp4cM3JFPdKzChPOZFKs6S3pyebn7A/vFbuX1NWNto3ucBOzGxMM QYvWVvIkYIZFY7kmbVJavOUOZieDUs3/67xR28e5CFtZyhjCJhtuECeHXi/7cST3VVh2 /qDIMQavB1X/P1M8f20dCuGe6wKmZJtMF29lcIDhWpBDj8nuX+f5GltIJ+7bP+clfoaM 6ksg== X-Forwarded-Encrypted: i=1; AJvYcCXhAgx0x0m2Jw2aZEEluWez26Lf2qa9tSaZxyqqMvApdME6iBRgqrdM7mnBZ2X+5whixz7qabcssQ==@nongnu.org X-Gm-Message-State: AOJu0Yy/aesPt+k7YIVajqT/ySv86nxl3XmkACp96vrpbNoOkps9htrk v8SSDSkt5KIzvZRQpNGTVIEQSqbG3IIU3xESeNd/bazH4KksVzjQMtSjjX3mOek= X-Google-Smtp-Source: AGHT+IGCfuJvgEuS7mdaniKHTJpPLHMzAXjXMIj8NGfV9QhRf3aVvXHwK13uI5ILUl55ENf6cj2t+A== X-Received: by 2002:a05:600c:4687:b0:431:2460:5574 with SMTP id 5b1f17b1804b1-4318418ac7amr71250255e9.27.1729865591153; Fri, 25 Oct 2024 07:13:11 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4318b57b051sm50104535e9.42.2024.10.25.07.13.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 07:13:10 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Song Gao , Eduardo Habkost , "Edgar E. Iglesias" , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Daniel Henrique Barboza , Yoshinori Sato , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 17/21] target/microblaze: Move setting of float rounding mode to reset Date: Fri, 25 Oct 2024 15:12:50 +0100 Message-Id: <20241025141254.2141506-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025141254.2141506-1-peter.maydell@linaro.org> References: <20241025141254.2141506-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Although the floating point rounding mode for Microblaze is always nearest-even, we cannot set it just once in the CPU initfn. This is because env->fp_status is in the part of the CPU state struct that is zeroed on reset. Move the call to set_float_rounding_mode() into the reset fn. (This had no guest-visible effects because it happens that the float_round_nearest_even enum value is 0, so when the struct was zeroed it didn't corrupt the setting.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/microblaze/cpu.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 135947ee800..6329a774331 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -201,6 +201,8 @@ static void mb_cpu_reset_hold(Object *obj, ResetType type) env->pc = cpu->cfg.base_vectors; + set_float_rounding_mode(float_round_nearest_even, &env->fp_status); + #if defined(CONFIG_USER_ONLY) /* start in user mode with interrupts enabled. */ mb_cpu_write_msr(env, MSR_EE | MSR_IE | MSR_VM | MSR_UM); @@ -311,15 +313,12 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) static void mb_cpu_initfn(Object *obj) { MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj); - CPUMBState *env = &cpu->env; gdb_register_coprocessor(CPU(cpu), mb_cpu_gdb_read_stack_protect, mb_cpu_gdb_write_stack_protect, gdb_find_static_feature("microblaze-stack-protect.xml"), 0); - set_float_rounding_mode(float_round_nearest_even, &env->fp_status); - #ifndef CONFIG_USER_ONLY /* Inbound IRQ and FIR lines */ qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2); From patchwork Fri Oct 25 14:12:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 2002298 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=ODYsXzs2; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4XZlF055Shz1xtp for ; Sat, 26 Oct 2024 01:15:48 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t4L4D-0004SE-PO; Fri, 25 Oct 2024 10:13:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t4L49-0004OQ-Ak for qemu-ppc@nongnu.org; Fri, 25 Oct 2024 10:13:25 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t4L3x-0007uJ-OS for qemu-ppc@nongnu.org; Fri, 25 Oct 2024 10:13:25 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-4315df7b43fso21476895e9.0 for ; Fri, 25 Oct 2024 07:13:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729865592; x=1730470392; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tMvryF9qkcHmjr/I6qQdi1be4a3BwpUnonGBJuEa1aE=; b=ODYsXzs2oGzg1KOhMmCailOU5vkt1bPS2TGEQXiA+TdVtyXlO5EegJGbAnpW+KMxuh Rili1Yv+mQm5aWsp72XSTnuAioIh3+zcqwP0aXwjDFRbtvOzOH0zjpvB9L7bvDs7WpXN AUfj8e7oM2JUZSA7vdrvmG5T9c0V8tPOVXv0Xey67A6eATfqM/tsw0Y3zxv7cTlFxalF mii0bzftcopxGirixt2HnIWYTTjFyCc11TtBi6m8p97oZvYgCjDPLGmXPswaoqHG5Ddj 91h2C9BsEhg7/x89ABiIfwUXd+V8I/nvpIGWeNYfFyVETbNRNcN45yCkfF3pmNAU08JH G53w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729865592; x=1730470392; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tMvryF9qkcHmjr/I6qQdi1be4a3BwpUnonGBJuEa1aE=; b=KTwz0ZemdePvbhe/AhHaXQb3awFIwRYJ2OqUrom8R2UUNisWh1aS6ST1qQhpbOTqmG 6qvxX2p4N7ji8L1AXaKAhhzm6GDjHd9Sv2Z2vOfRha5nwp4zPQSRzChzfpYaiFS+usx9 AfS226O+Vi4ZwRCQ/dP8COmrupa1W/WpVO4MpCoUcVATTA/aJYM6wsUvIeRTKO27k5F4 YBb0pOiAgEx7YtwHeVO3WXivYBOgA7+IqxeJV0ZoCzAZUQ280LpSfqAtAi3YXw608DZ8 yxF6pZa/t6I/bXSxHNvXIwSDC5/PmgjQVDBcXifZ/n6l4fidoOGAbznbuOqP6qgIzUN0 ErwQ== X-Forwarded-Encrypted: i=1; AJvYcCW65VG4//cKt+Oly6zVHIIZRlGLYD2wlbfPWodH4fYFrfbIyBsD1AiOsnlaIr/UusCGCt9bw+lIZQ==@nongnu.org X-Gm-Message-State: AOJu0YzjrEpxvYxrh6/aEUynaYp7IOmI1kidOvgcD5cPOF5JPhy/plvF NRudwCgPcZzRGZyCdQ2x/vktBAKM1LQqTBS0JU1jrkrd79UTdGdYD8tEUfsqO/c= X-Google-Smtp-Source: AGHT+IHxNq6/vkQ2TaPaeuuAkFK4+FFHuybPNerZNA0H29NUQ0TotXUp+CFWvnyAmdoq+Iu4Dr5CZg== X-Received: by 2002:a05:600c:19c6:b0:431:4fa0:2e0b with SMTP id 5b1f17b1804b1-4318c754b24mr47132065e9.28.1729865591969; Fri, 25 Oct 2024 07:13:11 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4318b57b051sm50104535e9.42.2024.10.25.07.13.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 07:13:11 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Song Gao , Eduardo Habkost , "Edgar E. Iglesias" , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Daniel Henrique Barboza , Yoshinori Sato , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 18/21] target/microblaze: Explicitly set 2-NaN propagation rule Date: Fri, 25 Oct 2024 15:12:51 +0100 Message-Id: <20241025141254.2141506-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025141254.2141506-1-peter.maydell@linaro.org> References: <20241025141254.2141506-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Set the NaN propagation rule explicitly for the float_status word used in the microblaze target. This is probably not the architecturally correct behaviour, but since this is a no-behaviour-change patch, we leave a TODO note to that effect. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/microblaze/cpu.c | 5 +++++ fpu/softfloat-specialize.c.inc | 3 ++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 6329a774331..14286deead9 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -202,6 +202,11 @@ static void mb_cpu_reset_hold(Object *obj, ResetType type) env->pc = cpu->cfg.base_vectors; set_float_rounding_mode(float_round_nearest_even, &env->fp_status); + /* + * TODO: this is probably not the correct NaN propagation rule for + * this architecture. + */ + set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status); #if defined(CONFIG_USER_ONLY) /* start in user mode with interrupts enabled. */ diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index a5c3e2b8de5..40cbb1ab73b 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -406,7 +406,8 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, || defined(TARGET_LOONGARCH64) || defined(TARGET_HPPA) \ || defined(TARGET_S390X) || defined(TARGET_PPC) || defined(TARGET_M68K) \ || defined(TARGET_SPARC) || defined(TARGET_XTENSA) \ - || defined(TARGET_I386) || defined(TARGET_ALPHA) + || defined(TARGET_I386) || defined(TARGET_ALPHA) \ + || defined(TARGET_MICROBLAZE) g_assert_not_reached(); #else rule = float_2nan_prop_x87; From patchwork Fri Oct 25 14:12:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 2002283 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=frUVCa6z; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4XZlCn3Gwbz1xwy for ; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4318b57b051sm50104535e9.42.2024.10.25.07.13.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 07:13:12 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Song Gao , Eduardo Habkost , "Edgar E. Iglesias" , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Daniel Henrique Barboza , Yoshinori Sato , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 19/21] target/openrisc: Explicitly set 2-NaN propagation rule Date: Fri, 25 Oct 2024 15:12:52 +0100 Message-Id: <20241025141254.2141506-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025141254.2141506-1-peter.maydell@linaro.org> References: <20241025141254.2141506-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Set the NaN propagation rule explicitly for the float_status word used in the openrisc target. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/openrisc/cpu.c | 6 ++++++ fpu/softfloat-specialize.c.inc | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 6ec54ad7a6c..b96561d1f26 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -105,6 +105,12 @@ static void openrisc_cpu_reset_hold(Object *obj, ResetType type) set_float_detect_tininess(float_tininess_before_rounding, &cpu->env.fp_status); + /* + * TODO: this is probably not the correct NaN propagation rule for + * this architecture. + */ + set_float_2nan_prop_rule(float_2nan_prop_x87, &cpu->env.fp_status); + #ifndef CONFIG_USER_ONLY cpu->env.picmr = 0x00000000; diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 40cbb1ab73b..ee5c73cad46 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -407,7 +407,7 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, || defined(TARGET_S390X) || defined(TARGET_PPC) || defined(TARGET_M68K) \ || defined(TARGET_SPARC) || defined(TARGET_XTENSA) \ || defined(TARGET_I386) || defined(TARGET_ALPHA) \ - || defined(TARGET_MICROBLAZE) + || defined(TARGET_MICROBLAZE) || defined(TARGET_OPENRISC) g_assert_not_reached(); #else rule = float_2nan_prop_x87; From patchwork Fri Oct 25 14:12:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 2002309 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=cAK75Km+; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4XZlHN6rQpz1xtp for ; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4318b57b051sm50104535e9.42.2024.10.25.07.13.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 07:13:13 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Song Gao , Eduardo Habkost , "Edgar E. Iglesias" , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Daniel Henrique Barboza , Yoshinori Sato , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 20/21] target/rx: Explicitly set 2-NaN propagation rule Date: Fri, 25 Oct 2024 15:12:53 +0100 Message-Id: <20241025141254.2141506-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025141254.2141506-1-peter.maydell@linaro.org> References: <20241025141254.2141506-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Set the NaN propagation rule explicitly for the float_status word used in the rx target. This not the architecturally correct behaviour, but since this is a no-behaviour-change patch, we leave a TODO note to that effect. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/rx/cpu.c | 7 +++++++ fpu/softfloat-specialize.c.inc | 3 ++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 36d2a6f1890..65a74ce720f 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -93,6 +93,13 @@ static void rx_cpu_reset_hold(Object *obj, ResetType type) env->fpsw = 0; set_flush_to_zero(1, &env->fp_status); set_flush_inputs_to_zero(1, &env->fp_status); + /* + * TODO: this is not the correct NaN propagation rule for this + * architecture. The "RX Family User's Manual: Software" table 1.6 + * defines the propagation rules as "prefer SNaN over QNaN; + * then prefer dest over source", which is float_2nan_prop_s_ab. + */ + set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status); } static ObjectClass *rx_cpu_class_by_name(const char *cpu_model) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index ee5c73cad46..254bbd67168 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -407,7 +407,8 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, || defined(TARGET_S390X) || defined(TARGET_PPC) || defined(TARGET_M68K) \ || defined(TARGET_SPARC) || defined(TARGET_XTENSA) \ || defined(TARGET_I386) || defined(TARGET_ALPHA) \ - || defined(TARGET_MICROBLAZE) || defined(TARGET_OPENRISC) + || defined(TARGET_MICROBLAZE) || defined(TARGET_OPENRISC) \ + || defined(TARGET_RX) g_assert_not_reached(); #else rule = float_2nan_prop_x87; From patchwork Fri Oct 25 14:12:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 2002276 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=swGkzWKB; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4XZlC10R8Yz1xwy for ; Sat, 26 Oct 2024 01:14:05 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t4L4T-0004sz-LA; Fri, 25 Oct 2024 10:13:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t4L4C-0004Qz-GU for qemu-ppc@nongnu.org; Fri, 25 Oct 2024 10:13:28 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t4L40-0007vv-3V for qemu-ppc@nongnu.org; Fri, 25 Oct 2024 10:13:28 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-4314f38d274so27178815e9.1 for ; Fri, 25 Oct 2024 07:13:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729865594; x=1730470394; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3a+J6mOz6+tgsx1AS0v8GOVI5VoZBPQJco52huASzlo=; b=swGkzWKB74q/r6UrCjCpsnhkDVw6Jws4JQpv2NNPOqK2jbJxltko7H1+s8u/qRECcz EFrs4zJ52KlVn4HQ7M8a5bAgpanB0ujovC6GcYbm0RG/PaxnV3d2eSc8QmTym7D/Bqgq MjyH2wAhQpFCQuKjtwXgv0Bz4ijnmxfYngxfItHVH5kQKIhRIbO2Wr63fThNWYnzrswq 9O9h4ba8jTOW/5EMdqZIFdnZgL12fjKgOZRzXfDz0ByziOT9Z38yMkm8wUdgUoGEjVQ1 aV5kjVtvnf5sApbcb8kgcSp4PiKiNtge8Ur6Yk66Grv2f8ZtceGDJp5uzY0QOYL1JYOl 7uEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729865594; x=1730470394; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3a+J6mOz6+tgsx1AS0v8GOVI5VoZBPQJco52huASzlo=; b=eCAeaAwwKM2t947FEJ0LDhhF6MT0XpaNf4MsLzcQ08AF5fnltgZYyMDkgcoPw8EEc1 D3JeWKkCbpI6JPlYac1z3zdvR5JV1BR6vK/KtUv0RlLorKhL3olSOGCWOWdy6S7JOY+X OgAhwjyfr75D2tIje8SeayD7nENCFHXFwYomz40cUyoNY54Jr6Aqk+xtdqcRS1IyJjOE QVQME7jPHoWTY6OAYJVvcbqjFoh6B7gQgF2eBkiaeKnPVdRUS1CMaSRFVtJFii/c7ob5 XkvjVN965t23SUC/hlq+yYcpBgLTOg9igX7Z8rg0yb/+UAlNJpGtihPcJXY3/yLYvk+E 3bvg== X-Forwarded-Encrypted: i=1; AJvYcCVm+4b5cbiSnFCReUtAySmyNLs0M6zkNLeRogSXu8jTTnjdGqhn/oGKzCg51pKbkCY7LrjQMqZNew==@nongnu.org X-Gm-Message-State: AOJu0YzREe0b3VcpfOl0LGjILBYd1IIf8NQOUXaU57dTrMRupBoIvAVo ZYdzFMNH+txiRAPjz+8BWWqmyPCOEUGRkQfOKYvupDR3u2LYV6GngjshoyEIfXI= X-Google-Smtp-Source: AGHT+IEYMdsaWi/TEfmIcbi85fBTUZ7J91UQRDnMyPxYqnX5zLsKoYqJjNy9q5lZ3k4JbpehHV50wA== X-Received: by 2002:a05:600c:1d82:b0:431:5ba1:a520 with SMTP id 5b1f17b1804b1-431841eb454mr112345445e9.3.1729865594517; Fri, 25 Oct 2024 07:13:14 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4318b57b051sm50104535e9.42.2024.10.25.07.13.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 07:13:14 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Song Gao , Eduardo Habkost , "Edgar E. Iglesias" , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Daniel Henrique Barboza , Yoshinori Sato , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 21/21] softfloat: Remove fallback rule from pickNaN() Date: Fri, 25 Oct 2024 15:12:54 +0100 Message-Id: <20241025141254.2141506-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025141254.2141506-1-peter.maydell@linaro.org> References: <20241025141254.2141506-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Now that all targets have been converted to explicitly set a NaN propagation rule, we can remove the set of target ifdefs (which now list every target) and clean up the references to fallback behaviour for float_2nan_prop_none. The "default" case in the switch will catch any remaining places where status->float_2nan_prop_rule was not set by the target. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/fpu/softfloat-types.h | 10 +++------- fpu/softfloat-specialize.c.inc | 23 +++-------------------- 2 files changed, 6 insertions(+), 27 deletions(-) diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 5cd5a0d0ae1..8f39691dfd0 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -178,13 +178,9 @@ typedef enum __attribute__((__packed__)) { * If default_nan_mode is enabled then it is valid not to set a * NaN propagation rule, because the softfloat code guarantees * not to try to pick a NaN to propagate in default NaN mode. - * - * For transition, currently the 'none' rule will cause us to - * fall back to picking the propagation rule based on the existing - * ifdef ladder. When all targets are converted it will be an error - * not to set the rule in float_status unless in default_nan_mode, - * and we will assert if we need to handle an input NaN and no - * rule was selected. + * When not in default-NaN mode, it is an error for the target + * not to set the rule in float_status, and we will assert if + * we need to handle an input NaN and no rule was selected. */ typedef enum __attribute__((__packed__)) { /* No propagation rule specified */ diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 254bbd67168..b5a32080505 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -390,32 +390,15 @@ bool float32_is_signaling_nan(float32 a_, float_status *status) static int pickNaN(FloatClass a_cls, FloatClass b_cls, bool aIsLargerSignificand, float_status *status) { - Float2NaNPropRule rule = status->float_2nan_prop_rule; - /* * We guarantee not to require the target to tell us how to * pick a NaN if we're always returning the default NaN. + * But if we're not in default-NaN mode then the target must + * specify via set_float_2nan_prop_rule(). */ assert(!status->default_nan_mode); - if (rule == float_2nan_prop_none) { - /* target didn't set the rule: fall back to old ifdef choices */ -#if defined(TARGET_AVR) || defined(TARGET_HEXAGON) \ - || defined(TARGET_RISCV) || defined(TARGET_SH4) \ - || defined(TARGET_TRICORE) || defined(TARGET_ARM) || defined(TARGET_MIPS) \ - || defined(TARGET_LOONGARCH64) || defined(TARGET_HPPA) \ - || defined(TARGET_S390X) || defined(TARGET_PPC) || defined(TARGET_M68K) \ - || defined(TARGET_SPARC) || defined(TARGET_XTENSA) \ - || defined(TARGET_I386) || defined(TARGET_ALPHA) \ - || defined(TARGET_MICROBLAZE) || defined(TARGET_OPENRISC) \ - || defined(TARGET_RX) - g_assert_not_reached(); -#else - rule = float_2nan_prop_x87; -#endif - } - - switch (rule) { + switch (status->float_2nan_prop_rule) { case float_2nan_prop_s_ab: if (is_snan(a_cls)) { return 0;