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Mon, 21 Oct 2024 14:24:43 +0000 (UTC) X-CSE-ConnectionGUID: GtwlCHIrTTulFjHROebvpw== X-CSE-MsgGUID: dE0UT/UfTg64lIEZ5cxd2w== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="28781488" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="28781488" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2024 07:24:43 -0700 X-CSE-ConnectionGUID: GSfk1+MeQAai4XGcozJrSg== X-CSE-MsgGUID: gmDL5iN/TyStqyJJLBmfZQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,221,1725346800"; d="scan'208";a="102857325" Received: from amlin-018-114.igk.intel.com ([10.102.18.114]) by fmviesa002.fm.intel.com with ESMTP; 21 Oct 2024 07:24:40 -0700 From: Arkadiusz Kubalewski To: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, intel-wired-lan@lists.osuosl.org Cc: anthony.l.nguyen@intel.com, przemyslaw.kitszel@intel.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, richardcochran@gmail.com, Arkadiusz Kubalewski , Aleksandr Loktionov Date: Mon, 21 Oct 2024 16:19:54 +0200 Message-Id: <20241021141955.1466979-2-arkadiusz.kubalewski@intel.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20241021141955.1466979-1-arkadiusz.kubalewski@intel.com> References: <20241021141955.1466979-1-arkadiusz.kubalewski@intel.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729520683; x=1761056683; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BWH78xnQQ0mBNPfZL+4Dfj88mfDX/d6wVTXi2veRfQc=; b=BllTxixUdYw3BpXJd3iRlDgNuKCn3lEd7XKeUsaa5rRvROwPE6pTFzQS RaSrsisXjq6ndzcLZ6OuilDexgSVDQExgiM0p/ApsnKjG27nXbtW8Jufv kvGSf6701NRRgA1YznEKEaLXOjjqrnPD6J5+S40PDkbCxlux+V7ODvHZg gWXH55TcuZTobBgJSTkGVGyGj2EL7sb+s0EyZQnPCj8FrmWeCsCtgqECQ saQIRPhYsf6Ap6G0hwgtrV9X11/dYP8bUL/CiDhacwLanizRBS7x56Vch lceoV//SRyPXkx6ruPbU9G/GQet2kDl63LgTeiqj/ek3fJvWWVqNQMZUu Q==; X-Mailman-Original-Authentication-Results: smtp4.osuosl.org; dmarc=pass (p=none dis=none) header.from=intel.com X-Mailman-Original-Authentication-Results: smtp4.osuosl.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=BllTxixU Subject: [Intel-wired-lan] [PATCH net-next 1/2] ptp: add control over HW timestamp latch point X-BeenThere: intel-wired-lan@osuosl.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Intel Wired Ethernet Linux Kernel Driver Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-wired-lan-bounces@osuosl.org Sender: "Intel-wired-lan" Currently HW support of PTP/timesync solutions in network PHY chips can be implemented with two different approaches, the timestamp maybe latched either at the beginning or after the Start of Frame Delimiter (SFD) [1]. Allow ptp device drivers to provide user with control over the HW timestamp latch point with ptp sysfs ABI. [1] https://www.ieee802.org/3/cx/public/april20/tse_3cx_01_0420.pdf Reviewed-by: Aleksandr Loktionov Signed-off-by: Arkadiusz Kubalewski --- Documentation/ABI/testing/sysfs-ptp | 12 ++++++++ drivers/ptp/ptp_sysfs.c | 44 +++++++++++++++++++++++++++++ include/linux/ptp_clock_kernel.h | 29 +++++++++++++++++++ 3 files changed, 85 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-ptp b/Documentation/ABI/testing/sysfs-ptp index 9c317ac7c47a..a0d89e0fd72e 100644 --- a/Documentation/ABI/testing/sysfs-ptp +++ b/Documentation/ABI/testing/sysfs-ptp @@ -140,3 +140,15 @@ Description: PPS events to the Linux PPS subsystem. To enable PPS events, write a "1" into the file. To disable events, write a "0" into the file. + +What: /sys/class/ptp/ptp/ts_point +Date: October 2024 +Contact: Arkadiusz Kubalewski +Description: + This file provides control over the point in time in + which the HW timestamp is latched. As specified in IEEE + 802.3cx, the latch point can be either at the beginning + or after the end of Start of Frame Delimiter (SFD). + Value "0" means the timestamp is latched at the + beginning of the SFD. Value "1" means that timestamp is + latched after the end of SFD. diff --git a/drivers/ptp/ptp_sysfs.c b/drivers/ptp/ptp_sysfs.c index 6b1b8f57cd95..7e9f6ef368b6 100644 --- a/drivers/ptp/ptp_sysfs.c +++ b/drivers/ptp/ptp_sysfs.c @@ -28,6 +28,46 @@ static ssize_t max_phase_adjustment_show(struct device *dev, } static DEVICE_ATTR_RO(max_phase_adjustment); +static ssize_t ts_point_show(struct device *dev, struct device_attribute *attr, + char *page) +{ + struct ptp_clock *ptp = dev_get_drvdata(dev); + enum ptp_ts_point point; + int err; + + if (!ptp->info->get_ts_point) + return -EOPNOTSUPP; + err = ptp->info->get_ts_point(ptp->info, &point); + if (err) + return err; + + return sysfs_emit(page, "%d\n", point); +} + +static ssize_t ts_point_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct ptp_clock *ptp = dev_get_drvdata(dev); + enum ptp_ts_point point; + int err; + u8 val; + + if (!ptp->info->set_ts_point) + return -EOPNOTSUPP; + if (kstrtou8(buf, 0, &val)) + return -EINVAL; + if (val > PTP_TS_POINT_MAX) + return -EINVAL; + point = val; + + err = ptp->info->set_ts_point(ptp->info, point); + if (err) + return err; + + return count; +} +static DEVICE_ATTR_RW(ts_point); + #define PTP_SHOW_INT(name, var) \ static ssize_t var##_show(struct device *dev, \ struct device_attribute *attr, char *page) \ @@ -335,6 +375,7 @@ static struct attribute *ptp_attrs[] = { &dev_attr_pps_enable.attr, &dev_attr_n_vclocks.attr, &dev_attr_max_vclocks.attr, + &dev_attr_ts_point.attr, NULL }; @@ -363,6 +404,9 @@ static umode_t ptp_is_attribute_visible(struct kobject *kobj, } else if (attr == &dev_attr_max_phase_adjustment.attr) { if (!info->adjphase || !info->getmaxphase) mode = 0; + } else if (attr == &dev_attr_ts_point.attr) { + if (!info->get_ts_point && !info->set_ts_point) + mode = 0; } return mode; diff --git a/include/linux/ptp_clock_kernel.h b/include/linux/ptp_clock_kernel.h index c892d22ce0a7..921d6615bd39 100644 --- a/include/linux/ptp_clock_kernel.h +++ b/include/linux/ptp_clock_kernel.h @@ -55,6 +55,23 @@ struct ptp_system_timestamp { clockid_t clockid; }; +/** + * enum ptp_ts_point - possible timestamp latch points (IEEE 802.3cx) + * @PTP_TS_POINT_SFD: timestamp latched at the beginning of sending Start + * of Frame Delimiter (SFD) + * @PTP_TS_POINT_POST_SFD: timestamp latched after the end of sending Start + * of Frame Delimiter (SFD) + */ +enum ptp_ts_point { + PTP_TS_POINT_SFD, + PTP_TS_POINT_POST_SFD, + + /* private: */ + __PTP_TS_POINT_MAX +}; + +#define PTP_TS_POINT_MAX (__PTP_TS_POINT_MAX - 1) + /** * struct ptp_clock_info - describes a PTP hardware clock * @@ -159,6 +176,14 @@ struct ptp_system_timestamp { * scheduling time (>=0) or negative value in case further * scheduling is not required. * + * @set_ts_point: Request change of timestamp latch point, as the timestamp + * could be latched at the beginning or after the end of start + * frame delimiter (SFD), as described in IEEE 802.3cx + * specification. + * + * @get_ts_point: Obtain the timestamp measurement latch point, counterpart of + * .set_ts_point() for getting currently configured value. + * * Drivers should embed their ptp_clock_info within a private * structure, obtaining a reference to it using container_of(). * @@ -195,6 +220,10 @@ struct ptp_clock_info { int (*verify)(struct ptp_clock_info *ptp, unsigned int pin, enum ptp_pin_function func, unsigned int chan); long (*do_aux_work)(struct ptp_clock_info *ptp); + int (*set_ts_point)(struct ptp_clock_info *ptp, + enum ptp_ts_point point); + int (*get_ts_point)(struct ptp_clock_info *ptp, + enum ptp_ts_point *point); }; struct ptp_clock; From patchwork Mon Oct 21 14:19:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kubalewski, Arkadiusz" X-Patchwork-Id: 1999978 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256 header.s=default header.b=BjasO0+Q; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org (client-ip=140.211.166.138; helo=smtp1.osuosl.org; envelope-from=intel-wired-lan-bounces@osuosl.org; receiver=patchwork.ozlabs.org) Received: from smtp1.osuosl.org (smtp1.osuosl.org [140.211.166.138]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4XXHdK65K4z1xwK for ; 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Mon, 21 Oct 2024 14:24:46 +0000 (UTC) X-CSE-ConnectionGUID: UAfST7XCQf+uIJTj0BU7dg== X-CSE-MsgGUID: /aWLR2BWRfytbRADmgyggQ== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="28781500" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="28781500" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2024 07:24:46 -0700 X-CSE-ConnectionGUID: yt24rj3ZQumqjdvCb+ZENQ== X-CSE-MsgGUID: UufQ8RWnQGKIEJ3mQrHtpQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,221,1725346800"; d="scan'208";a="102857345" Received: from amlin-018-114.igk.intel.com ([10.102.18.114]) by fmviesa002.fm.intel.com with ESMTP; 21 Oct 2024 07:24:43 -0700 From: Arkadiusz Kubalewski To: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, intel-wired-lan@lists.osuosl.org Cc: anthony.l.nguyen@intel.com, przemyslaw.kitszel@intel.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, richardcochran@gmail.com, Arkadiusz Kubalewski , Aleksandr Loktionov Date: Mon, 21 Oct 2024 16:19:55 +0200 Message-Id: <20241021141955.1466979-3-arkadiusz.kubalewski@intel.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20241021141955.1466979-1-arkadiusz.kubalewski@intel.com> References: <20241021141955.1466979-1-arkadiusz.kubalewski@intel.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729520686; x=1761056686; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=J909dl2X+WM6p84dhJEZhnAALeM6t0I3u1+vHBG9F9k=; b=CNljoHx8c3ROJLbRp9UpXpoF69GEoOfpZ9/H4dZeWoC3LUEB4wwGOf0f 3ZXhYYpsoO8qccTNVUG76nzHonx9B5qUtyVaj+uwK/QHWIIHVVDNEuW3a Du8hQI79yGIlGx53mauYbtjY4Z/t958VkBmmBwiWC6Jz7SoOKWNtggdZL CGSvQuxacBN4okwnrgP4sLBygHp3JFhJaGb5eR434qKYK40JXzXKMZc5L DGCZGFWjRnsoeQbI/PHFeoxq34SuCOuArZNxPsRpFvyOwIAzoaXF+Tk7v uq63VknGZBV1o2HeL1QeoC8LoNw2QHMfpgEjL+12w/OQXFo7+6TCv8o5Z g==; X-Mailman-Original-Authentication-Results: smtp4.osuosl.org; dmarc=pass (p=none dis=none) header.from=intel.com X-Mailman-Original-Authentication-Results: smtp4.osuosl.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=CNljoHx8 Subject: [Intel-wired-lan] [PATCH net-next 2/2] ice: ptp: add control over HW timestamp latch point X-BeenThere: intel-wired-lan@osuosl.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Intel Wired Ethernet Linux Kernel Driver Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-wired-lan-bounces@osuosl.org Sender: "Intel-wired-lan" Allow user to control the latch point of ptp HW timestamps in E825 devices. Reviewed-by: Aleksandr Loktionov Signed-off-by: Arkadiusz Kubalewski --- drivers/net/ethernet/intel/ice/ice_ptp.c | 46 +++++++++++++++++ drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 57 +++++++++++++++++++++ drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 2 + 3 files changed, 105 insertions(+) diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c b/drivers/net/ethernet/intel/ice/ice_ptp.c index a999fface272..47444412ed9a 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp.c @@ -2509,6 +2509,50 @@ static int ice_ptp_parse_sdp_entries(struct ice_pf *pf, __le16 *entries, return 0; } +/** + * ice_get_ts_point - get the tx timestamp latch point + * @info: the driver's PTP info structure + * @point: return the configured tx timestamp latch point + * + * Return: 0 on success, negative on failure. + */ +static int +ice_get_ts_point(struct ptp_clock_info *info, enum ptp_ts_point *point) +{ + struct ice_pf *pf = ptp_info_to_pf(info); + struct ice_hw *hw = &pf->hw; + bool sfd_ena; + int ret; + + ice_ptp_lock(hw); + ret = ice_ptp_hw_ts_point_get(hw, &sfd_ena); + ice_ptp_unlock(hw); + if (!ret) + *point = sfd_ena ? PTP_TS_POINT_SFD : PTP_TS_POINT_POST_SFD; + + return ret; +} + +/** + * ice_set_ts_point - set the tx timestamp latch point + * @info: the driver's PTP info structure + * @point: requested tx timestamp latch point + */ +static int +ice_set_ts_point(struct ptp_clock_info *info, enum ptp_ts_point point) +{ + bool sfd_ena = point == PTP_TS_POINT_SFD ? true : false; + struct ice_pf *pf = ptp_info_to_pf(info); + struct ice_hw *hw = &pf->hw; + int ret; + + ice_ptp_lock(hw); + ret = ice_ptp_hw_ts_point_set(hw, sfd_ena); + ice_ptp_unlock(hw); + + return ret; +} + /** * ice_ptp_set_funcs_e82x - Set specialized functions for E82X support * @pf: Board private structure @@ -2529,6 +2573,8 @@ static void ice_ptp_set_funcs_e82x(struct ice_pf *pf) if (ice_is_e825c(&pf->hw)) { pf->ptp.ice_pin_desc = ice_pin_desc_e825c; pf->ptp.info.n_pins = ICE_PIN_DESC_ARR_LEN(ice_pin_desc_e825c); + pf->ptp.info.set_ts_point = ice_set_ts_point; + pf->ptp.info.get_ts_point = ice_get_ts_point; } else { pf->ptp.ice_pin_desc = ice_pin_desc_e82x; pf->ptp.info.n_pins = ICE_PIN_DESC_ARR_LEN(ice_pin_desc_e82x); diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c index da88c6ccfaeb..d81525bc8a16 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c @@ -6303,3 +6303,60 @@ int ice_cgu_get_output_pin_state_caps(struct ice_hw *hw, u8 pin_id, return 0; } + +/** + * ice_ptp_hw_ts_point_get - check if tx timestamping is latched on/post SFD + * @hw: pointer to the HW struct + * @sfd_ena: on success true if tx timestamping latched at beginning of SFD, + * false if post sfd + * + * Verify if HW timestamping point is configured to measure at the beginning or + * post of SFD (Start of Frame Delimiter) + * + * Return: 0 on success, negative on error + */ +int ice_ptp_hw_ts_point_get(struct ice_hw *hw, bool *sfd_ena) +{ + u8 port = hw->port_info->lport; + u32 val; + int err; + + err = ice_read_mac_reg_eth56g(hw, port, PHY_MAC_XIF_MODE, &val); + if (err) + return err; + if (val | PHY_MAC_XIF_TS_SFD_ENA_M) + *sfd_ena = true; + else + *sfd_ena = false; + + return err; +} + +/** + * ice_ptp_hw_ts_point_set - configure timestamping on/post SFD + * @hw: pointer to the HW struct + * @sfd_ena: true to enable timestamping at beginning of SFD, false post sfd + * + * Configure timestamping to measure at the beginning/post SFD (Start of Frame + * Delimiter) + * + * Return: 0 on success, negative on error + */ +int ice_ptp_hw_ts_point_set(struct ice_hw *hw, bool sfd_ena) +{ + u8 port = hw->port_info->lport; + int err, val; + + err = ice_read_mac_reg_eth56g(hw, port, PHY_MAC_XIF_MODE, &val); + if (err) + return err; + if ((val | PHY_MAC_XIF_TS_SFD_ENA_M && sfd_ena) || + (!(val | PHY_MAC_XIF_TS_SFD_ENA_M) && !sfd_ena)) + return -EINVAL; + if (sfd_ena) + val |= PHY_MAC_XIF_TS_SFD_ENA_M; + else + val &= ~PHY_MAC_XIF_TS_SFD_ENA_M; + + return ice_write_mac_reg_eth56g(hw, port, PHY_MAC_XIF_MODE, val); +} diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h index 656daff3447e..cefedd01479a 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h @@ -348,6 +348,8 @@ void ice_ptp_init_hw(struct ice_hw *hw); int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready); int ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port, enum ice_ptp_tmr_cmd configured_cmd); +int ice_ptp_hw_ts_point_get(struct ice_hw *hw, bool *sfd_ena); +int ice_ptp_hw_ts_point_set(struct ice_hw *hw, bool sfd_ena); /* E822 family functions */ int ice_read_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 *val);