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[24.5.188.125]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7eaeab58003sm1635031a12.44.2024.10.20.12.40.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 12:40:25 -0700 (PDT) From: Vineet Gupta To: gcc-patches@gcc.gnu.org, Richard Sandiford , Vladimir Makarov , Michael Meissner , Peter Bergner , Wilco Dijkstra Cc: Jeff Law , gnu-toolchain@rivosinc.com, Vineet Gupta Subject: [PATCH 1/4] sched1: hookize pressure scheduling spilling agressiveness Date: Sun, 20 Oct 2024 12:40:15 -0700 Message-ID: <20241020194018.3051160-2-vineetg@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241020194018.3051160-1-vineetg@rivosinc.com> References: <20241020194018.3051160-1-vineetg@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Pressure senstive scheduling seems to prefer "wide" schedules with more parallelism tending to more spills. This works better for in-order cores [1][2]. The Excess Change Cost (ECC) of an insn, essentially a proxy of register pressure attributed to an insn, deliberately ignores negative values (Pressure reduction), making them 0 (neutral), leading to the above heuristic. However this heuristic induces sched1 spill frenzy on RISC-V, especially on SPEC2017 507.Cactu. If insn scheduling is disabled completely, the total dynamic icounts for this workload are reduced in half from ~2.5 trillion insns to ~1.3 (w/ -fno-schedule-insns). This patch allows for an opt-in target hook TARGET_SCHED_PRESSURE_PREFER_NARROW: - The default hook (returns false) preserves existing behavior of wider schedules, more parallelism and potentially more spills. - targets implementing the hook as true get the reverse effect. RISC-V backend implements this hook in next patch. [1] https://gcc.gnu.org/pipermail/gcc-patches/2024-August/659847.html [2] https://gcc.gnu.org/legacy-ml/gcc-patches/2011-12/msg01684.html gcc/ChangeLog: PR target/11472 * target.def (pressure_prefer_narrow): Add target hook. * doc/tm.texi.in: Add TARGET_SCHED_PRESSURE_PREFER_NARROW. * doc/tm.texi: Regenerated. * haifa-sched.cc (model_excess_group_cost): Return negative delta if targetm.sched.pressure_prefer_narrow returns true. (model_excess_cost): Ceil negative baseECC to 0 only if targetm.sched.pressure_prefer_narrow returns false. Signed-off-by: Vineet Gupta --- gcc/doc/tm.texi | 11 +++++++++++ gcc/doc/tm.texi.in | 2 ++ gcc/haifa-sched.cc | 30 ++++++++++++++++++++++-------- gcc/target.def | 13 +++++++++++++ 4 files changed, 48 insertions(+), 8 deletions(-) diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi index 4deb3d2c283a..0f5255436c8b 100644 --- a/gcc/doc/tm.texi +++ b/gcc/doc/tm.texi @@ -7495,6 +7495,17 @@ This is the cleanup hook corresponding to @code{TARGET_SCHED_INIT_GLOBAL}. @var{verbose} is the verbose level provided by @option{-fsched-verbose-@var{n}}. @end deftypefn +@deftypefn {Target Hook} bool TARGET_SCHED_PRESSURE_PREFER_NARROW (void) +This hooks returns target boolean preference for narrow schedules (fewer +spills) vs. wider schdules (potentially more spills) in Pressure sensistive +Instruction scheduling. The algorithm is currently slightly biased towards +in-order cores thus favors wider schdules with more parallelism +(and spills). For certain targets, depending on ISA (number of registers, +addressing modes etc) the spilling can get excessive which this hook allows +to override. The default version of this hook returns @code{false} which +preserves existing spilling behavior. +@end deftypefn + @deftypefn {Target Hook} rtx TARGET_SCHED_DFA_PRE_CYCLE_INSN (void) The hook returns an RTL insn. The automaton state used in the pipeline hazard recognizer is changed as if the insn were scheduled diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in index 9f147ccb95cc..0f24344a272b 100644 --- a/gcc/doc/tm.texi.in +++ b/gcc/doc/tm.texi.in @@ -4786,6 +4786,8 @@ them: try the first ones in this list first. @hook TARGET_SCHED_FINISH_GLOBAL +@hook TARGET_SCHED_PRESSURE_PREFER_NARROW + @hook TARGET_SCHED_DFA_PRE_CYCLE_INSN @hook TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN diff --git a/gcc/haifa-sched.cc b/gcc/haifa-sched.cc index 1bc610f9a5f9..f8c42d30d5a4 100644 --- a/gcc/haifa-sched.cc +++ b/gcc/haifa-sched.cc @@ -2398,11 +2398,18 @@ model_excess_group_cost (struct model_pressure_group *group, int pressure, cl; cl = ira_pressure_classes[pci]; - if (delta < 0 && point >= group->limits[pci].point) + if (delta < 0) { - pressure = MAX (group->limits[pci].orig_pressure, - curr_reg_pressure[cl] + delta); - return -model_spill_cost (cl, pressure, curr_reg_pressure[cl]); + if (point >= group->limits[pci].point) + { + pressure = MAX (group->limits[pci].orig_pressure, + curr_reg_pressure[cl] + delta); + return -model_spill_cost (cl, pressure, curr_reg_pressure[cl]); + } + /* if target prefers fewer spills, return the -ve delta indicating + pressure reduction. */ + else if (targetm.sched.pressure_prefer_narrow ()) + return delta; } if (delta > 0) @@ -2453,7 +2460,7 @@ model_excess_cost (rtx_insn *insn, bool print_p) } if (print_p) - fprintf (sched_dump, "\n"); + fprintf (sched_dump, " ECC %d\n", cost); return cost; } @@ -2489,8 +2496,9 @@ model_set_excess_costs (rtx_insn **insns, int count) bool print_p; /* Record the baseECC value for each instruction in the model schedule, - except that negative costs are converted to zero ones now rather than - later. Do not assign a cost to debug instructions, since they must + except that for targets which prefer wider schedules (more spills) + negative costs are converted to zero ones now rather than later. + Do not assign a cost to debug instructions, since they must not change code-generation decisions. Experiments suggest we also get better results by not assigning a cost to instructions from a different block. @@ -2512,7 +2520,7 @@ model_set_excess_costs (rtx_insn **insns, int count) print_p = true; } cost = model_excess_cost (insns[i], print_p); - if (cost <= 0) + if (!targetm.sched.pressure_prefer_narrow () && cost <= 0) { priority = INSN_PRIORITY (insns[i]) - insn_delay (insns[i]) - cost; priority_base = MAX (priority_base, priority); @@ -2523,6 +2531,12 @@ model_set_excess_costs (rtx_insn **insns, int count) if (print_p) fprintf (sched_dump, MODEL_BAR); + /* If target prefers "narrow" schedules (less spills) avoid MAX (baseECC, 0) + which changes negative baseECC (pressure reduction) to 0 (neutral) thus + favoring spills. */ + if (targetm.sched.pressure_prefer_narrow ()) + return; + /* Use MAX (baseECC, 0) and baseP to calculcate ECC for each instruction. */ for (i = 0; i < count; i++) diff --git a/gcc/target.def b/gcc/target.def index b31550108883..19333591bbc5 100644 --- a/gcc/target.def +++ b/gcc/target.def @@ -1038,6 +1038,19 @@ DEFHOOK @var{verbose} is the verbose level provided by @option{-fsched-verbose-@var{n}}.", void, (FILE *file, int verbose), NULL) +DEFHOOK +(pressure_prefer_narrow, + "This hooks returns target boolean preference for narrow schedules (fewer\n\ +spills) vs. wider schdules (potentially more spills) in Pressure sensistive\n\ +Instruction scheduling. The algorithm is currently slightly biased towards\n\ +in-order cores thus favors wider schdules with more parallelism\n\ +(and spills). For certain targets, depending on ISA (number of registers,\n\ +addressing modes etc) the spilling can get excessive which this hook allows\n\ +to override. The default version of this hook returns @code{false} which\n\ +preserves existing spilling behavior.", + bool, (void), + hook_bool_void_false) + /* Reorder insns in a machine-dependent fashion, in two different places. Default does nothing. */ DEFHOOK From patchwork Sun Oct 20 19:40:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vineet Gupta X-Patchwork-Id: 1999643 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.a=rsa-sha256 header.s=20230601 header.b=i+gx8OpC; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4XWpjj2dQ6z1xvp for ; Mon, 21 Oct 2024 06:42:01 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 96D5F3858405 for ; Sun, 20 Oct 2024 19:41:59 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pf1-x435.google.com (mail-pf1-x435.google.com [IPv6:2607:f8b0:4864:20::435]) by sourceware.org (Postfix) with ESMTPS id 1A27B3858D37 for ; Sun, 20 Oct 2024 19:40:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1A27B3858D37 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 1A27B3858D37 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::435 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1729453230; cv=none; b=CK2qOlkcpIoN+heMii9mzQPMGKaWqrlYK6+4fqQPBxDlvyx/RRIJxvmAdEMobZQqfXFLCg1D2w0t7X8FTEKUS0ESQcAFtW2pl/PKj1U9aqTVFFRy0kpzJJYXyhiRJPk544W43fVBCLSfR+yVjce1230nx8TffuJtnlh/AWdFV68= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1729453230; c=relaxed/simple; bh=nWszAxGUvce2qZnH/OK4yh7uvp08HY1YguuJI0J8QN4=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=WP3e1mXie3t/jzaJZkMSjEuF+dN6e1/ETwCpZsqIiQtHE82PtCfbVJjRI5Hd+VnW3TwcChgpATIvnR8LPhwGM2iWejNa/gnF9mUyVpO3h5N+bLez5aEGOBy9clt2ThoXzQu5htt8jWTewPHX0JsRebot9u3zxuvV8DiGSK7vFVc= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-71e52582cf8so2571854b3a.2 for ; Sun, 20 Oct 2024 12:40:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1729453227; x=1730058027; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hqa2kLqqmMoVvouLtDqlQ4N2Vmf251MwEaOfY31G2Rs=; b=i+gx8OpCm58tTmoP45xeOQU1Xvx3+aMsZPX0wrSCfxKbGz52W5rMFCNw5WGMaQGHIo EZV76VzpJQMSjxf3yb9hssm3hmXdtdezABQxdERZfniXJeVhHpSUzxJmHCv2DnuYY7Hx swJlyySpm6+TmpypBPVgO1u2G1FhKVoOdaKR92fbeLKtTbG0XRFSEaUu6xUud5uXz+Si FQd8Qefx4tMKuEKIdSSPih1p6k1eiR/BExk2/3YGe2R5tYgPCM3yzKtbJELWIquaNwkc 2Run5zLedmLQ7FyV0dOCjnaQBXwGnsu5UZ/4CAaSoSgfMtroyzQv74g8f6YLGl5gbwHO R4fQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729453227; x=1730058027; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hqa2kLqqmMoVvouLtDqlQ4N2Vmf251MwEaOfY31G2Rs=; b=lwamOyyO7vTu/4g/0VqhWjvzHy6KULP3tUuMp9Jry9Y4K9RTOYtz9noa7rjhQf+l/b GqVdO+VctSj29X6FF6h6tJ+xDCnIB7mReJSTLMTQO6KgIZxw0Ib3pkogAwne+RCDODd9 a2qpKbkPnWu6CIoAF/Kuo4ty5aZZChrMzu5MiJuUCprvTy+Yec0JEzSwDoVS/OqIXG0p shsPjKu0B/ztImnkwgXfvCFPm6l9tOX9+a/ts7BpT8YqSXYmNdR0P1qPXnDaz3c0fSZ8 JUE1qlNhMMjI/LWgDLwuAFyQOt7jQlN+mMkr/JBxfG3uNDanSvF0e3b6jIkbsYH6QFJ7 ot2w== X-Gm-Message-State: AOJu0Ywxuq9MY7aj6x1uoVvf8K6F6f4lhz7iNNKE6+3FT3zcP5vpLVD8 itdz6G7MTpBLpdtFzVII6HUroAb3FFn9lauVSIGysNZ26e+k4BpIKmd7WgQbSTWeaKVsBOBbhiC 8t6U= X-Google-Smtp-Source: AGHT+IGVJo+1SIwiAB558ruYq/fjjX1yEPLjpaAeTdk4gn44oyRIAQKryCjlUovcXKPXf4ZuSUX/Gg== X-Received: by 2002:a05:6a20:bb28:b0:1d9:3456:b71e with SMTP id adf61e73a8af0-1d93456ba08mr8377850637.12.1729453226832; Sun, 20 Oct 2024 12:40:26 -0700 (PDT) Received: from fw-ubuntu.ba.rivosinc.com (c-24-5-188-125.hsd1.ca.comcast.net. [24.5.188.125]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7eaeab58003sm1635031a12.44.2024.10.20.12.40.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 12:40:26 -0700 (PDT) From: Vineet Gupta To: gcc-patches@gcc.gnu.org, Richard Sandiford , Vladimir Makarov , Michael Meissner , Peter Bergner , Wilco Dijkstra Cc: Jeff Law , gnu-toolchain@rivosinc.com, Vineet Gupta Subject: [PATCH 2/4] RISC-V: Implement TARGET_SCHED_PRESSURE_PREFER_NARROW [PR/114729] Date: Sun, 20 Oct 2024 12:40:16 -0700 Message-ID: <20241020194018.3051160-3-vineetg@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241020194018.3051160-1-vineetg@rivosinc.com> References: <20241020194018.3051160-1-vineetg@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-9.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, URIBL_BLACK autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org This inhibits sched1 aggressive spilling on RISC-V (see prev commit for details of what the hook does). On RISC-V (BPI-F3) we see good results. (Build: -Ofast -march=rv64gcv_zba_zbb_zbs) Before: ------ Performance counter stats for './cactusBSSN_r_base.rivos spec_ref.par': 4,769,844.10 msec task-clock:u # 1.000 CPUs utilized 6,029 context-switches:u # 1.264 /sec 0 cpu-migrations:u # 0.000 /sec 201,468 page-faults:u # 42.238 /sec 7,631,707,552,979 cycles:u # 1.600 GHz 2,630,225,489,010 instructions:u # 0.34 insn per cycle 10,592,305,077 branches:u # 2.221 M/sec 16,274,388 branch-misses:u # 0.15% of all branches After: ----- Performance counter stats for './cactusBSSN_r_base.rivos spec_ref.par': 4,471,770.20 msec task-clock:u # 0.998 CPUs utilized 159,245 context-switches:u # 35.611 /sec 2 cpu-migrations:u # 0.000 /sec 204,065 page-faults:u # 45.634 /sec 7,153,778,156,281 cycles:u ( 6% faster) # 1.600 GHz 2,143,115,846,207 instructions:u (18.5% fewer) # 0.30 insn per cycle 10,592,316,035 branches:u # 2.369 M/sec 17,229,411 branch-misses:u # 0.16% of all branches Similarly, good results on Cactu on aarch64 as well (qemu dynamic icounts only) (Build: -march=armv9-a+sve2) Before: 1,382,403,783,566 After: 1,264,869,192,921 (8.5% improv) gcc/ChangeLog: PR target/114729 * config/riscv/riscv.cc (TARGET_SCHED_PRESSURE_PREFER_NARROW): Define to true. gcc/testsuite/ChangeLog: PR target/114729 * gcc.target/riscv/riscv.exp: Enable new tests to build. * gcc.target/riscv/sched1-spills/spill1.cpp: Add new test. Signed-off-by: Vineet Gupta --- gcc/config/riscv/riscv.cc | 3 ++ gcc/testsuite/gcc.target/riscv/riscv.exp | 2 ++ .../gcc.target/riscv/sched1-spills/spill1.cpp | 31 +++++++++++++++++++ 3 files changed, 36 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/sched1-spills/spill1.cpp diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 3ac40234345a..46f775b3cdcb 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -12616,6 +12616,9 @@ riscv_stack_clash_protection_alloca_probe_range (void) #undef TARGET_SCHED_ADJUST_COST #define TARGET_SCHED_ADJUST_COST riscv_sched_adjust_cost +#undef TARGET_SCHED_PRESSURE_PREFER_NARROW +#define TARGET_SCHED_PRESSURE_PREFER_NARROW hook_bool_void_true + #undef TARGET_FUNCTION_OK_FOR_SIBCALL #define TARGET_FUNCTION_OK_FOR_SIBCALL riscv_function_ok_for_sibcall diff --git a/gcc/testsuite/gcc.target/riscv/riscv.exp b/gcc/testsuite/gcc.target/riscv/riscv.exp index 187eb6640470..3cbbf63b9d0a 100644 --- a/gcc/testsuite/gcc.target/riscv/riscv.exp +++ b/gcc/testsuite/gcc.target/riscv/riscv.exp @@ -38,6 +38,8 @@ dg-init # Main loop. gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \ "" $DEFAULT_CFLAGS +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/sched1-spills/*.{\[cS\],cpp}]] \ + "" $DEFAULT_CFLAGS # All done. dg-finish diff --git a/gcc/testsuite/gcc.target/riscv/sched1-spills/spill1.cpp b/gcc/testsuite/gcc.target/riscv/sched1-spills/spill1.cpp new file mode 100644 index 000000000000..47a9d1a01ab4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sched1-spills/spill1.cpp @@ -0,0 +1,31 @@ +/* Reduced from SPEC2017 Cactu ML_BSSN_Advect.cpp + by comparing -fschedule-insn and -fno-schedule-insns builds. + Shows up one extra spill (pair of spill markers "sfp") in verbose asm + output which the patch fixes. */ + +/* { dg-options "-O2 -march=rv64gc -mabi=lp64d -save-temps -fverbose-asm" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "O1" "-Og" "-Os" "-Oz" } } */ +/* { dg-final { scan-assembler-times "%sfp" 0 } } */ + +void s(); +double b, c, d, e, f, g, h, k, l, m, n, o, p, q, t, u, v; +int *j; +double *r, *w; +long x; +void y() { + double *a((double *)s); + for (;;) + for (; j[1];) + for (int i = 1; i < j[0]; i++) { + k = l; + m = n; + o = p = q; + r[0] = t; + a[0] = u; + x = g; + e = f; + v = w[x]; + b = c; + d = h; + } +} From patchwork Sun Oct 20 19:40:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vineet Gupta X-Patchwork-Id: 1999642 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.a=rsa-sha256 header.s=20230601 header.b=WbMIroYF; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; 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[24.5.188.125]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7eaeab58003sm1635031a12.44.2024.10.20.12.40.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 12:40:27 -0700 (PDT) From: Vineet Gupta To: gcc-patches@gcc.gnu.org, Richard Sandiford , Vladimir Makarov , Michael Meissner , Peter Bergner , Wilco Dijkstra Cc: Jeff Law , gnu-toolchain@rivosinc.com, Vineet Gupta Subject: [PATCH 3/4] sched1: model: only promote true dependecies in predecessor promotion Date: Sun, 20 Oct 2024 12:40:17 -0700 Message-ID: <20241020194018.3051160-4-vineetg@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241020194018.3051160-1-vineetg@rivosinc.com> References: <20241020194018.3051160-1-vineetg@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Background ---------- sched1 runs a preliminary "model schedular" ahead of the main list schedular. Its sole purpose is to keep register pressure to mimimum [1] and it uses DFA register depenendency tracking to arrange insns. [1] https://gcc.gnu.org/legacy-ml/gcc-patches/2011-12/msg01684.html `The idea was to construct a preliminary "model" schedule in which the only objective is to keep register pressure to a minimum. This schedule ignores pipeline characteristics, latencies, and the number of available registers. The maximum pressure seen in this initial model schedule (MP) is then the benchmark for ECC(X).` It starts off with an intial "worklist" of insns w/o any prior dependencies, scheduling them, adding successors of scheduled insn to the worklist and so on until all insns in the basic block are done. It can run into situations where an otherwise to-be-scheduled candidate can't because it's predecessors haven't been scheduled yet, requiring "predecessor promotion" implemented in model_promote_predecessors (). Promotion is essentially bumping INSN model_priority so that it makes it towards the head of elligible-to-schedule list. An INSN can have multiple dependencies/predecessor nodes, some of them being true dependency REG_DEP_TRUE meaning the predecessor register output is a must have for the INSN to be scheduled. e.g. In the sched1 dump below, insn 70 has multiple deps, but 68 and 69 are true reg deps: ;; | insn | prio | ;; | 68 | 3 | r217=r144+r146 ;; | 69 | 5 | r218=flt(r143) ;; | 70 | 2 | [r217]=r218 ;; insn code bb dep prio cost reservation ;; ---- ---- -- --- ---- ---- ----------- ;; 70 286 6 6 2 1 alu : FW: 97tnm 91m 83tn 78m 76tn 72tn ;; : BK: 69t 68t 57n 60n 61n 64n ^^^ ^^^ Issue ----- Currently predecessor promotion bumps the priority of all predecessors to same value, treating the true deps and the rest alike. This simple strategy can sometimes cause a subtle inadvertent effect: given the right "other" conditions (depth, height etc) a non true dependency can get scheduled ahead of the true dep, increasing the live range between the true dep and the dependent. This increases the peak register pressure for the BB. Subsequently this inflated peak register pressure steers the main list schdular, giving it the lower bound to work with. Main schedular can make pressure worse (due to instruction latencies and pipeline models etc) but otherwise it can work with the given peak pressure. Thus a higher model pressure will ultimately lead to a less than ideal final schedule. This subtle effect get crazy exacerbated on RISC-V SPEC2017 Cactu benchmark. For the spill2.cpp testcase (reduced from Cactu itself) on RISC-V, here's what was seen: - After idx #6, insn 70 predecessors are promoted (see list above). Of the true deps, insn 68 is already schdeuled, insn 69 needs to be. insn 69 does get promoted (higher priority 4) but so does insn 60 (prio 4) with its predecessor insn 58 getting even higher promotion (prio 5). - The insn 58 and its deps chain end up being scheduled ahead of insn 70 such that now there are 3 insns seperating it from its direct dep insn 69. This blows reg pressure past the spill threshhold of sched_class_regs_num[GR_REGS] as evident from the pressure summary at the end. ;; Model schedule: ;; ;; | idx insn | mpri hght dpth prio | ;; | 0 56 | 0 8 0 15 | r210=flt(r185#0) GR_REGS:[25,+0] FP_REGS:[0,+1] ;; | 1 57 | 0 8 1 12 | [r242+low(`e')]=r210 GR_REGS:[25,+0] FP_REGS:[1,-1] ;; | 2 63 | 2 7 0 12 | r215=r141+r183 GR_REGS:[25,+1] FP_REGS:[0,+0] ;; | 3 64 | 1 8 2 11 | r216=[r215] GR_REGS:[26,-1] FP_REGS:[0,+1] ;; | 4 65 | 0 8 3 8 | r143=fix(r216) GR_REGS:[25,+1] FP_REGS:[1,-1] ;; | 5 67 | 0 8 4 4 | r146=r143<<0x3 GR_REGS:[26,+1] FP_REGS:[0,+0] ;; | 6 68 | 0 8 5 3 | r217=r144+r146 GR_REGS:[27,+1] FP_REGS:[0,+0] ;; +--- priority of 70 = 3, priority of 69 60 61 = 4 ;; | 7 69 | 4 7 4 5 | r218=flt(r143) GR_REGS:[28,+0] FP_REGS:[0,+1] ;; | 8 58 | 6 4 0 5 | r211=r138+r183 GR_REGS:[28,+1] FP_REGS:[1,+0] ^^^^^^^ ;; | 9 60 | 5 5 2 4 | r213=[r211] GR_REGS:[29,-1] FP_REGS:[1,+1] ;; | 10 61 | 4 3 0 4 | r214=[r243+low(`o')] GR_REGS:[28,+0] FP_REGS:[2,+1] ;; | 11 70 | 3 8 6 2 | [r217]=r218 GR_REGS:[28,-1] FP_REGS:[3,-1] ... ... ;; Pressure summary: GR_REGS:29 FP_REGS:3 ^^^ Solution -------- When promoting predecessors, only assign the true deps higher priority. The rest of predecessors get the same priority as depedant insn. Implementation -------------- Predecessor promotion logic can be described in pseudo "C" as follows: insn->model_priority = model_next_priority++; for (;;) #0 { FOR_EACH_DEP (insn->insn, SD_LIST_HARD_BACK, sd_it, dep) { if (pro->insn #1 && pro->model_priority != model_next_priority && QUEUE_INDEX (pro->insn) != QUEUE_SCHEDULED) { pro->model_priority = model_next_priority; #2 if (QUEUE_INDEX (pro->insn) == QUEUE_READY) { ... } else // recurse to dependent #3 { pro->next = first; first = pro; } } // if not schduled } // FOR_EACH_DEP if (!first) break; insn = first; first = insn->next; } // for model_next_priority++ ; - The core change of this patch is essentially bifurcating #2 to bump the priortiy for true dependency more than the rest of deps. - An additional gaurd added in #3, to only recurse for true deps; otherwise it can end up clobbering the recurse list with same entry showing up multiple times, (e.g. an insn could be predecessor of multiple dependant insns: as true dep for first and normal dep for the others). - The condition #1 also needs to be tightened for the two levels of predecessor priorities. - The good (and bad) thing is there is a overarching infinite loop #0 and any coding snafus tend to hit it pretty fast, just by trying to bootstrap the toolchain (specially libgcc) or building glibc off of it. - There is also a need to track true dependencies in addition to the existing all deps of an insn. This is needed at the call-site of promotion logic to only invoke promotion when there's unscheduled true dependecies. - These changes are NOT gated behing the new target hook as it seems like the right thing to do anywhere/everywhere. Improvement measurement ------------------------ Results are convincing On RISC-V (BPI-F3) run of Cactu. (Build: -Ofast -march=rv64gcv_zba_zbb_zbs) Before: ------ 7,631,707,552,979 cycles:u # 1.600 GHz 2,630,225,489,010 instructions:u # 0.34 insn per cycle After (just this fix) ----- 7,100,864,968,062 cycles:u ( 7% faster) # 1.600 GHz 2,180,957,013,712 instructions:u (17% fewer) # 0.31 insn per cycle Aggregate (with ECC fix) ---- 6,736,337,207,427 cycles:u (12% faster) # 1.600 GHz 2,078,712,047,604 instructions:u (21% fewer) # 0.31 insn per cycle ECC fix alone (prev patch) ---- 7,153,778,156,281 cycles:u ( 6% faster) # 1.600 GHz 2,143,115,846,207 instructions:u (18.5% faster) # 0.30 insn per cycle Significant gains are also seen on aarch64 (QEMU dynamic icounts only) (Build: -Ofast -march=armv9-a+sve2) Before : 1,382,403,783,566 After (just this fix) : 1,237,532,639,657 (10.4% fewer) Aggregate (with ECC fix) : 1,113,896,471,282 (19.4% fewer) Just ECC fix (prev patch): 1,264,869,192,921 (8.5% fewer) TBD --- On RISC-V the individual gains from model pressure fix (7, 17) and the ECC fix (6, 18.5) are are not adding up with both fixes (12, 21) indicating that main list schedular could be undoing some of the model schedule arrangements (which it does anyways for right reasons). On aarch64 they seem to be accumulating on top nicely, atleast in the QEMU icounts reduction. gcc/ChangeLog: PR target/114729 * haifa-sched.cc (struct model_insn_info): Add field unscheduled_true_preds. (model_analyze_insns): Initialize unscheduled_true_preds. (model_add_successors_to_worklist): Decrement unscheduled_true_preds. (model_promote_predecessors): Handle true dependencies differently than the rest. (model_choose_insn): Promote only on pending true dependencies. (model_dump_pressure_summary): Print BB index. (model_start_schedule): Call dump summary with BB reference. * sched-rgn.cc (debug_dependencies): Print predecessors for debugging aid. gcc/testsuite/ChangeLog: PR target/114729 * gcc.target/riscv/sched1-spills/hang1.c: New test. * gcc.target/riscv/sched1-spills/hang5.c: New test. * gcc.target/riscv/sched1-spills/spill2.cpp: New test. Signed-off-by: Vineet Gupta --- gcc/haifa-sched.cc | 66 ++++++++++++++----- gcc/sched-rgn.cc | 14 +++- .../gcc.target/riscv/sched1-spills/hang1.c | 32 +++++++++ .../gcc.target/riscv/sched1-spills/hang5.c | 60 +++++++++++++++++ .../gcc.target/riscv/sched1-spills/spill2.cpp | 37 +++++++++++ 5 files changed, 192 insertions(+), 17 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/sched1-spills/hang1.c create mode 100644 gcc/testsuite/gcc.target/riscv/sched1-spills/hang5.c create mode 100644 gcc/testsuite/gcc.target/riscv/sched1-spills/spill2.cpp diff --git a/gcc/haifa-sched.cc b/gcc/haifa-sched.cc index f8c42d30d5a4..67f99ce00339 100644 --- a/gcc/haifa-sched.cc +++ b/gcc/haifa-sched.cc @@ -1862,6 +1862,9 @@ struct model_insn_info { /* The number of predecessor nodes that must still be scheduled. */ int unscheduled_preds; + + /* The subset of above which have true register dependency. */ + int unscheduled_true_preds; }; /* Information about the pressure limit for a particular register class. @@ -3529,7 +3532,20 @@ model_analyze_insns (void) insn->old_queue = QUEUE_INDEX (iter); QUEUE_INDEX (iter) = QUEUE_NOWHERE; - insn->unscheduled_preds = dep_list_size (iter, SD_LIST_HARD_BACK); + insn->unscheduled_preds = 0; + insn->unscheduled_true_preds = 0; + /* opencoded dep_list_size () to get true deps as well. */ + FOR_EACH_DEP (iter, SD_LIST_HARD_BACK, sd_it, dep) + { + if (DEBUG_INSN_P (DEP_PRO (dep))) + continue; + insn->unscheduled_preds++; + if (DEP_TYPE (dep) == REG_DEP_TRUE) + insn->unscheduled_true_preds++; + } + gcc_assert (insn->unscheduled_preds + == dep_list_size (iter, SD_LIST_HARD_BACK)); + if (insn->unscheduled_preds == 0) model_add_to_worklist (insn, NULL, model_worklist); @@ -3661,6 +3677,9 @@ model_add_successors_to_worklist (struct model_insn_info *insn) { con->unscheduled_preds--; + if (DEP_TYPE (dep) == REG_DEP_TRUE) + con->unscheduled_true_preds--; + /* Update the depth field of each true-dependent successor. Increasing the depth gives them a higher priority than before. */ @@ -3692,7 +3711,7 @@ model_add_successors_to_worklist (struct model_insn_info *insn) static void model_promote_predecessors (struct model_insn_info *insn) { - struct model_insn_info *pro, *first; + struct model_insn_info *pro, *first, *leaf_true_dep = NULL; sd_iterator_def sd_it; dep_t dep; @@ -3708,16 +3727,25 @@ model_promote_predecessors (struct model_insn_info *insn) { FOR_EACH_DEP (insn->insn, SD_LIST_HARD_BACK, sd_it, dep) { + bool true_dep = (DEP_TYPE (dep) == REG_DEP_TRUE); + pro = MODEL_INSN_INFO (DEP_PRO (dep)); /* The first test is to ignore debug instructions, and instructions from other blocks. */ if (pro->insn - && pro->model_priority != model_next_priority - && QUEUE_INDEX (pro->insn) != QUEUE_SCHEDULED) + && QUEUE_INDEX (pro->insn) != QUEUE_SCHEDULED + && ((true_dep && (pro->model_priority < model_next_priority)) + || (!true_dep + && (pro->model_priority < (model_next_priority - 1))))) { - pro->model_priority = model_next_priority; + if (true_dep) + pro->model_priority = model_next_priority; + else + pro->model_priority = model_next_priority - 1; + if (sched_verbose >= 7) - fprintf (sched_dump, " %d", INSN_UID (pro->insn)); + fprintf (sched_dump, " %d=%d", INSN_UID (pro->insn), + pro->model_priority); if (QUEUE_INDEX (pro->insn) == QUEUE_READY) { /* PRO is already in the worklist, but it now has @@ -3726,12 +3754,14 @@ model_promote_predecessors (struct model_insn_info *insn) model_remove_from_worklist (pro); model_add_to_worklist (pro, NULL, model_worklist); } - else + else if (true_dep) { /* PRO isn't in the worklist. Recursively process its predecessors until we find one that is. */ pro->next = first; first = pro; + if (pro->unscheduled_true_preds == 0) + leaf_true_dep = pro; } } } @@ -3740,9 +3770,15 @@ model_promote_predecessors (struct model_insn_info *insn) insn = first; first = insn->next; } - if (sched_verbose >= 7) - fprintf (sched_dump, " = %d\n", model_next_priority); + if (leaf_true_dep) + { + gcc_assert (QUEUE_INDEX (leaf_true_dep->insn) == QUEUE_NOWHERE); + gcc_assert (leaf_true_dep->model_priority == model_next_priority); + model_add_to_worklist (leaf_true_dep, NULL, model_worklist); + } model_next_priority++; + if (sched_verbose >= 7) + fprintf (sched_dump, " NEXT prio = %d\n", model_next_priority); } /* Pick one instruction from model_worklist and process it. */ @@ -3760,10 +3796,10 @@ model_choose_insn (void) count = param_max_sched_ready_insns; while (count > 0 && insn) { - fprintf (sched_dump, ";;\t+--- %d [%d, %d, %d, %d]\n", + fprintf (sched_dump, ";;\t+--- %d [%d, %d, %d, %d][%d]\n", INSN_UID (insn->insn), insn->model_priority, insn->depth + insn->alap, insn->depth, - INSN_PRIORITY (insn->insn)); + INSN_PRIORITY (insn->insn), insn->unscheduled_preds); count--; insn = insn->next; } @@ -3824,7 +3860,7 @@ model_choose_insn (void) fprintf (sched_dump, ";;\t+--- promoting insn %d, which is ready\n", INSN_UID (insn->insn)); } - if (insn->unscheduled_preds) + if (insn->unscheduled_true_preds) /* INSN isn't yet ready to issue. Give all its predecessors the highest priority. */ model_promote_predecessors (insn); @@ -3857,11 +3893,11 @@ model_reset_queue_indices (void) to sched_dump. */ static void -model_dump_pressure_summary (void) +model_dump_pressure_summary (basic_block bb) { int pci, cl; - fprintf (sched_dump, ";; Pressure summary:"); + fprintf (sched_dump, ";; Pressure summary (bb %d):", bb->index); for (pci = 0; pci < ira_pressure_classes_num; pci++) { cl = ira_pressure_classes[pci]; @@ -3900,7 +3936,7 @@ model_start_schedule (basic_block bb) model_curr_point = 0; initiate_reg_pressure_info (df_get_live_in (bb)); if (sched_verbose >= 1) - model_dump_pressure_summary (); + model_dump_pressure_summary (bb); } /* Free the information associated with GROUP. */ diff --git a/gcc/sched-rgn.cc b/gcc/sched-rgn.cc index 3d8cff76aaf9..bedccc9f2b83 100644 --- a/gcc/sched-rgn.cc +++ b/gcc/sched-rgn.cc @@ -2855,15 +2855,25 @@ void debug_dependencies (rtx_insn *head, rtx_insn *tail) else print_reservation (sched_dump, insn); - fprintf (sched_dump, "\t: "); + fprintf (sched_dump, "\t: FW:"); { sd_iterator_def sd_it; dep_t dep; FOR_EACH_DEP (insn, SD_LIST_FORW, sd_it, dep) - fprintf (sched_dump, "%d%s%s ", INSN_UID (DEP_CON (dep)), + fprintf (sched_dump, " %d%s%s%s", INSN_UID (DEP_CON (dep)), + DEP_TYPE (dep) == REG_DEP_TRUE ? "t" : "", DEP_NONREG (dep) ? "n" : "", DEP_MULTIPLE (dep) ? "m" : ""); + if (sched_verbose >= 5) + { + fprintf (sched_dump, "\n;;\t\t\t\t\t\t: BK:"); + FOR_EACH_DEP (insn, SD_LIST_HARD_BACK, sd_it, dep) + fprintf (sched_dump, " %d%s%s%s", INSN_UID (DEP_PRO (dep)), + DEP_TYPE (dep) == REG_DEP_TRUE ? "t" : "", + DEP_NONREG (dep) ? "n" : "", + DEP_MULTIPLE (dep) ? "m" : ""); + } } fprintf (sched_dump, "\n"); } diff --git a/gcc/testsuite/gcc.target/riscv/sched1-spills/hang1.c b/gcc/testsuite/gcc.target/riscv/sched1-spills/hang1.c new file mode 100644 index 000000000000..312bea1fede0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sched1-spills/hang1.c @@ -0,0 +1,32 @@ +/* Reduced from libgcc/_divtc3.c + - Interim version of model schedule changes would cause a infinite loop + during predecessor promotion. + + insn 11 predecessor promotion called with insn 9 being predecessor + of two insn 10 and insn 11. + +;; --- Region Dependences --- b 2 bb 0 + ... +;; 10 76 2 1 4 3 alu : FW: 11tm +;; : BK: 9t +;; 11 357 2 6 1 1 alu : FW: +;; : BK: 5 6 8 9 10tm 7tm + ... +;; Model schedule: +;; +;; | idx insn | mpri hght dpth prio | +;; | 0 5 | 0 3 0 8 | r138=`a' +;; | 1 6 | 0 3 1 7 | r140=[r138] +;; | 2 7 | 0 3 2 4 | r139=abs(r140) + ... +;; +--- priority of 11 = 2, priority of 8=2 9=2 10=3 9=3 8=3 */ + + +/* { dg-options "-O2 -fPIC -march=rv64gc_zba_zbb_zbs_zfa -mabi=lp64d" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "O1" "-Og" "-Os" "-Oz" } } */ + +float a, b; +void c() { + if (__builtin_fabsl(a) < __builtin_fabsl(b)) + a = 2; +} diff --git a/gcc/testsuite/gcc.target/riscv/sched1-spills/hang5.c b/gcc/testsuite/gcc.target/riscv/sched1-spills/hang5.c new file mode 100644 index 000000000000..0edb04223234 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sched1-spills/hang5.c @@ -0,0 +1,60 @@ +/* Reduced from glibc:iconv/gconv_simple.c + - Interim version of model schedule changes would cause a infinite loop + during predecessor promotion because true dependency was not getting + added to worklist. + + insn 19 is indirect predecessor of multiple insns, but not direct of + any in the BB. + +;; --- Region Dependences --- b 4 bb 0 + ... +;; 19 275 4 0 2 1 alu : FW: 26 20 +;; : BK: +;; 20 5 4 2 2 1 alu : FW: 26tm +;; : BK: 15 19 +;; 22 125 4 1 5 3 alu : FW: 26 25t +;; : BK: 18tn +;; 25 104 4 1 2 1 alu : FW: 26tm +;; : BK: 22t +;; 26 353 4 7 1 1 alu : FW: +;; : BK: 15 16 19 22 25tm 20tm 18m + ... +;; Model schedule: +;; +;; | idx insn | mpri hght dpth prio | +;; | 0 15 | 0 5 0 10 | r161=r134+r140 +;; | 1 16 | 0 5 1 9 | r139=zxn([r161+0x4]) +;; | 2 18 | 0 5 2 6 | [r178+low(`g')]=r139#0 +;; | 3 22 | 0 5 3 5 | r164=sxn([r134]) +;; | 4 25 | 0 5 4 2 | r166=r164&0x7 + ... +;; +--- priority of 26 = 1, priority of 19=1 20=2 19=1 NEXT prio = 3 +;; +--- priority of 26 = 3, priority of 19=3 20=4 19=3 NEXT prio = 5 */ + + +/* { dg-options "-O2 -march=rv64gc_zba_zbb_zbs_zfa -mabi=lp64d" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "O1" "-Og" "-Os" "-Oz" } } */ + +typedef struct { + int a; + struct { + char b[]; + } c; +} d; +struct e { + d *f; +} i; +char g[4]; +char h; +void j(struct e *m) { + d *k; + long a = 0, l; + for (; a < (m->f->a & 7); ++a) + g[0] = m->f->c.b[a]; + for (; a < l; a++) + k->c.b[a] = h; +} +void n() { + if (i.f->a & 7) + j(&i); +} diff --git a/gcc/testsuite/gcc.target/riscv/sched1-spills/spill2.cpp b/gcc/testsuite/gcc.target/riscv/sched1-spills/spill2.cpp new file mode 100644 index 000000000000..cb739ac6a7d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sched1-spills/spill2.cpp @@ -0,0 +1,37 @@ +/* Reduced from SPEC2017 Cactu ML_BSSN_RHS.cpp + Showed spill despite the prior ECC fix (vs. -fno-schedule-insns) due to + promotion of non true predecessors (essentally led to this patch). */ + +/* { dg-options "-O2 -march=rv64gc -mabi=lp64d -save-temps -fverbose-asm" } */ +/* { dg-final { scan-assembler-times "%sfp" 0 } } */ + +void a(); +double *b, *c, *d, *f, *g, *h; +double e, o, q; +int k, l, n; +int *m; +long p; +void r() { + long ai = p; + for (;;) + for (int j; n; ++j) + for (int i(m[0]); i; i++) { + long aj = i * j; + e = aj; + double am = b[aj], ba = am, bf = ba * o; + c[aj] = aj = f[aj]; + double aq = g[aj]; + double at = ((double *)a)[aj]; + switch (l) + case 2: + (&aj)[ai] = (&d[aj])[ai]; + double ax(aq); + double ay(k == 1 ? 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[24.5.188.125]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7eaeab58003sm1635031a12.44.2024.10.20.12.40.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 12:40:29 -0700 (PDT) From: Vineet Gupta To: gcc-patches@gcc.gnu.org, Richard Sandiford , Vladimir Makarov , Michael Meissner , Peter Bergner , Wilco Dijkstra Cc: Jeff Law , gnu-toolchain@rivosinc.com, Vineet Gupta Subject: [PATCH 4/4] sched1: model: ICE on infinite loops in predecessor promotion (Not for Merge) Date: Sun, 20 Oct 2024 12:40:18 -0700 Message-ID: <20241020194018.3051160-5-vineetg@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241020194018.3051160-1-vineetg@rivosinc.com> References: <20241020194018.3051160-1-vineetg@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org This is just a testing hack in case someone runs into infinite loops with model schedule change. I did run into quite a few during the course of development and instead of sched trace files eating up the disk, better to ICE and abort. gcc/ChangeLog: * haifa-sched.cc (model_promote_predecessors): Add infinite looping checks. Signed-off-by: Vineet Gupta --- gcc/haifa-sched.cc | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/gcc/haifa-sched.cc b/gcc/haifa-sched.cc index 67f99ce00339..471f7c686e9d 100644 --- a/gcc/haifa-sched.cc +++ b/gcc/haifa-sched.cc @@ -3714,6 +3714,18 @@ model_promote_predecessors (struct model_insn_info *insn) struct model_insn_info *pro, *first, *leaf_true_dep = NULL; sd_iterator_def sd_it; dep_t dep; + int lockup_local_count = 0; + static int lockup_inter_insn, lockup_inter_count; + + if (lockup_inter_insn == insn->insn->u2.insn_uid) + { + gcc_assert (lockup_inter_count++ < 1000); + } + else + { + lockup_inter_insn = insn->insn->u2.insn_uid; + lockup_inter_count = 0; + } if (sched_verbose >= 7) fprintf (sched_dump, ";;\t+--- priority of %d = %d, priority of", @@ -3765,6 +3777,7 @@ model_promote_predecessors (struct model_insn_info *insn) } } } + gcc_assert (++lockup_local_count < 10000); if (!first) break; insn = first;