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Wed, 16 Oct 2024 23:46:10 -0700 (PDT) From: Linus Walleij Date: Thu, 17 Oct 2024 08:46:08 +0200 Subject: [PATCH v2 1/2] dt-bindings: gpio-mmio: Add ngpios property Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241017-gpio-ngpios-v2-1-cecfdb38d40e@linaro.org> References: <20241017-gpio-ngpios-v2-0-cecfdb38d40e@linaro.org> In-Reply-To: <20241017-gpio-ngpios-v2-0-cecfdb38d40e@linaro.org> To: Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Linus Walleij X-Mailer: b4 0.14.0 This adds the ngpios property to MMIO GPIO. We restrict the property to 1..63 since there is no point in 0 GPIO lines and we support up to 64bits wide registers for now. Acked-by: Rob Herring (Arm) Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/gpio/gpio-mmio.yaml | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml b/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml index b394e058256e..87e986386f32 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml +++ b/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml @@ -37,7 +37,8 @@ properties: description: A list of registers in the controller. The width of each register is determined by its size. All registers must have the same width. The number - of GPIOs is set by the width, with bit 0 corresponding to GPIO 0. + of GPIOs is set by the width, with bit 0 corresponding to GPIO 0, unless + the ngpios property further restricts the number of used lines. items: - description: Register to READ the value of the GPIO lines. If GPIO line is high, @@ -74,6 +75,15 @@ properties: native-endian: true + ngpios: + minimum: 1 + maximum: 63 + description: + If this property is present the number of usable GPIO lines are restricted + to the first 0 .. ngpios lines. This is useful when the GPIO MMIO register + has 32 bits for GPIO but only the first 12 are actually connected to + real electronics, and then we set ngpios to 12. + no-output: $ref: /schemas/types.yaml#/definitions/flag description: @@ -111,6 +121,7 @@ examples: compatible = "brcm,bcm6345-gpio"; reg-names = "dirout", "dat"; reg = <0xfffe0406 2>, <0xfffe040a 2>; + ngpios = <15>; native-endian; gpio-controller; #gpio-cells = <2>; From patchwork Thu Oct 17 06:46:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 1998417 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=G3ozVM0U; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2604:1380:4601:e00::3; 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Wed, 16 Oct 2024 23:46:13 -0700 (PDT) Received: from lino.lan ([85.235.12.238]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2fb5d1a7398sm6139271fa.105.2024.10.16.23.46.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Oct 2024 23:46:12 -0700 (PDT) From: Linus Walleij Date: Thu, 17 Oct 2024 08:46:09 +0200 Subject: [PATCH v2 2/2] gpio: mmio: Parse ngpios property Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241017-gpio-ngpios-v2-2-cecfdb38d40e@linaro.org> References: <20241017-gpio-ngpios-v2-0-cecfdb38d40e@linaro.org> In-Reply-To: <20241017-gpio-ngpios-v2-0-cecfdb38d40e@linaro.org> To: Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Linus Walleij X-Mailer: b4 0.14.0 This makes the MMIO GPIO driver parse the ngpios property from devices instatiated directly from the device tree so we can further restrict the number of GPIOs down from the number of bits on the target register. Signed-off-by: Linus Walleij --- drivers/gpio/gpio-mmio.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpio/gpio-mmio.c b/drivers/gpio/gpio-mmio.c index d89e78f0ead3..c772f1b6e694 100644 --- a/drivers/gpio/gpio-mmio.c +++ b/drivers/gpio/gpio-mmio.c @@ -694,6 +694,7 @@ MODULE_DEVICE_TABLE(of, bgpio_of_match); static struct bgpio_pdata *bgpio_parse_fw(struct device *dev, unsigned long *flags) { struct bgpio_pdata *pdata; + u32 ngpios; if (!dev_fwnode(dev)) return NULL; @@ -704,6 +705,9 @@ static struct bgpio_pdata *bgpio_parse_fw(struct device *dev, unsigned long *fla pdata->base = -1; + if (!device_property_read_u32(dev, "ngpios", &ngpios)) + pdata->ngpio = ngpios; + if (device_is_big_endian(dev)) *flags |= BGPIOF_BIG_ENDIAN_BYTE_ORDER;