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Tue, 15 Oct 2024 07:56:06 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hsd1.ca.comcast.net ([2601:647:6700:64d0:728c:1095:7130:36f8]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71e7737171fsm1400330b3a.17.2024.10.15.07.56.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2024 07:56:05 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: gkm@rivosinc.com, jeffreyalaw@gmail.com, vineetg@rivosinc.com, ewlu@rivosinc.com Subject: [PATCH v4] RISC-V: add option -m(no-)autovec-segment Date: Tue, 15 Oct 2024 07:56:00 -0700 Message-ID: <20241015145600.1354174-1-patrick@rivosinc.com> X-Mailer: git-send-email 2.46.0 MIME-Version: 1.0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Greg McGary Add option -m(no-)autovec-segment to enable/disable autovectorizer from emitting vector segment load/store instructions. This is useful for performance experiments. gcc/ChangeLog: * config/riscv/autovec.md (vec_mask_len_load_lanes, vec_mask_len_store_lanes): Predicate with TARGET_VECTOR_AUTOVEC_SEGMENT * gcc/config/riscv/riscv-opts.h (TARGET_VECTOR_AUTOVEC_SEGMENT): New macro. * gcc/config/riscv/riscv.opt (-m(no-)autovec-segment): New option. * testsuite/gcc.target/riscv/rvv/autovec/struct/*_noseg*.c, testsuite/gcc.target/riscv/rvv/autovec/no-segment.c: New tests. --- Relying on CI for testing. Please wait for that testing to complete before committing. v4 changelog: Remove ICE expectation since middle-end ICE has been resolved. --- gcc/config/riscv/autovec.md | 4 +- gcc/config/riscv/riscv-opts.h | 5 ++ gcc/config/riscv/riscv.opt | 4 ++ .../gcc.target/riscv/rvv/autovec/no-segment.c | 61 +++++++++++++++++++ .../autovec/struct/mask_struct_load_noseg-1.c | 6 ++ .../autovec/struct/mask_struct_load_noseg-2.c | 6 ++ .../autovec/struct/mask_struct_load_noseg-3.c | 6 ++ .../autovec/struct/mask_struct_load_noseg-4.c | 6 ++ .../autovec/struct/mask_struct_load_noseg-5.c | 6 ++ .../autovec/struct/mask_struct_load_noseg-6.c | 6 ++ .../autovec/struct/mask_struct_load_noseg-7.c | 6 ++ .../struct/mask_struct_load_noseg_run-1.c | 4 ++ .../struct/mask_struct_load_noseg_run-2.c | 4 ++ .../struct/mask_struct_load_noseg_run-3.c | 4 ++ .../struct/mask_struct_load_noseg_run-4.c | 4 ++ .../struct/mask_struct_load_noseg_run-5.c | 4 ++ .../struct/mask_struct_load_noseg_run-6.c | 4 ++ .../struct/mask_struct_load_noseg_run-7.c | 4 ++ .../struct/mask_struct_store_noseg-1.c | 6 ++ .../struct/mask_struct_store_noseg-2.c | 6 ++ .../struct/mask_struct_store_noseg-3.c | 6 ++ .../struct/mask_struct_store_noseg-4.c | 6 ++ .../struct/mask_struct_store_noseg-5.c | 6 ++ .../struct/mask_struct_store_noseg-6.c | 6 ++ .../struct/mask_struct_store_noseg-7.c | 6 ++ .../struct/mask_struct_store_noseg_run-1.c | 4 ++ .../struct/mask_struct_store_noseg_run-2.c | 4 ++ .../struct/mask_struct_store_noseg_run-3.c | 4 ++ .../struct/mask_struct_store_noseg_run-4.c | 4 ++ .../struct/mask_struct_store_noseg_run-5.c | 4 ++ .../struct/mask_struct_store_noseg_run-6.c | 4 ++ .../struct/mask_struct_store_noseg_run-7.c | 4 ++ .../rvv/autovec/struct/struct_vect_noseg-1.c | 8 +++ .../rvv/autovec/struct/struct_vect_noseg-10.c | 7 +++ .../rvv/autovec/struct/struct_vect_noseg-11.c | 7 +++ .../rvv/autovec/struct/struct_vect_noseg-12.c | 7 +++ .../rvv/autovec/struct/struct_vect_noseg-13.c | 6 ++ .../rvv/autovec/struct/struct_vect_noseg-14.c | 6 ++ .../rvv/autovec/struct/struct_vect_noseg-15.c | 6 ++ .../rvv/autovec/struct/struct_vect_noseg-16.c | 6 ++ .../rvv/autovec/struct/struct_vect_noseg-17.c | 6 ++ .../rvv/autovec/struct/struct_vect_noseg-18.c | 6 ++ .../rvv/autovec/struct/struct_vect_noseg-2.c | 8 +++ .../rvv/autovec/struct/struct_vect_noseg-3.c | 8 +++ .../rvv/autovec/struct/struct_vect_noseg-4.c | 8 +++ .../rvv/autovec/struct/struct_vect_noseg-5.c | 8 +++ .../rvv/autovec/struct/struct_vect_noseg-6.c | 7 +++ .../rvv/autovec/struct/struct_vect_noseg-7.c | 7 +++ .../rvv/autovec/struct/struct_vect_noseg-8.c | 7 +++ .../rvv/autovec/struct/struct_vect_noseg-9.c | 7 +++ .../autovec/struct/struct_vect_noseg_run-1.c | 4 ++ .../autovec/struct/struct_vect_noseg_run-10.c | 4 ++ .../autovec/struct/struct_vect_noseg_run-11.c | 4 ++ .../autovec/struct/struct_vect_noseg_run-12.c | 4 ++ .../autovec/struct/struct_vect_noseg_run-13.c | 4 ++ .../autovec/struct/struct_vect_noseg_run-14.c | 4 ++ .../autovec/struct/struct_vect_noseg_run-15.c | 4 ++ .../autovec/struct/struct_vect_noseg_run-16.c | 4 ++ .../autovec/struct/struct_vect_noseg_run-17.c | 4 ++ .../autovec/struct/struct_vect_noseg_run-18.c | 4 ++ .../autovec/struct/struct_vect_noseg_run-2.c | 4 ++ .../autovec/struct/struct_vect_noseg_run-3.c | 4 ++ .../autovec/struct/struct_vect_noseg_run-4.c | 4 ++ .../autovec/struct/struct_vect_noseg_run-5.c | 4 ++ .../autovec/struct/struct_vect_noseg_run-6.c | 4 ++ .../autovec/struct/struct_vect_noseg_run-7.c | 4 ++ .../autovec/struct/struct_vect_noseg_run-8.c | 4 ++ .../autovec/struct/struct_vect_noseg_run-9.c | 4 ++ 68 files changed, 409 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-11.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-12.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-13.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-14.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-15.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-17.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-18.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-9.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-11.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-12.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-13.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-14.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-15.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-17.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-18.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-9.c -- 2.34.1 diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 7dc78a48874..a34f63c9651 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -282,7 +282,7 @@ (match_operand: 2 "vector_mask_operand") (match_operand 3 "autovec_length_operand") (match_operand 4 "const_0_operand")] - "TARGET_VECTOR" + "TARGET_VECTOR_AUTOVEC_SEGMENT" { riscv_vector::expand_lanes_load_store (operands, true); DONE; @@ -295,7 +295,7 @@ (match_operand: 2 "vector_mask_operand") (match_operand 3 "autovec_length_operand") (match_operand 4 "const_0_operand")] - "TARGET_VECTOR" + "TARGET_VECTOR_AUTOVEC_SEGMENT" { riscv_vector::expand_lanes_load_store (operands, false); DONE; diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 5497d1173c4..1b2a4bcb072 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -157,4 +157,9 @@ enum riscv_tls_type { TLS_DESCRIPTORS }; +/* On some microarchitectures, vector segment loads and stores are excessively + expensive, so predicate the generation of those instrunctions. */ +#define TARGET_VECTOR_AUTOVEC_SEGMENT \ + (TARGET_VECTOR && riscv_mautovec_segment) + #endif /* ! GCC_RISCV_OPTS_H */ diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index a8758abc918..6360ed3984d 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -658,3 +658,7 @@ Specify TLS dialect. mfence-tso Target Var(TARGET_FENCE_TSO) Init(1) Specifies whether the fence.tso instruction should be used. + +mautovec-segment +Target Integer Var(riscv_mautovec_segment) Init(1) +Enable (default) or disable generation of vector segment load/store instructions. diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c new file mode 100644 index 00000000000..79d03612a22 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c @@ -0,0 +1,61 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -O3 -mno-autovec-segment" } */ + +enum e { c, d }; +enum g { f }; + +struct h +{ + float x, w; +}; + +struct k +{ + short z, y, i, j; +}; + +long r; +struct h m, p; +struct k *q; + +short +l (float s) +{ + if (s <= 0.0f) + return 0; + + if (s >= 5) + return 5; + + return s; +} + +struct n +{ + enum g colorspace; +}; + +struct n o (struct k *s, struct h *t) +{ + t->w = s->z; +} + +void +ClutImageChannel (struct n *s, enum e t) +{ + + while (s) + for (; r; r++) + { + o (q, &p); + + if (t & d) + q->y = (&m + q->y)->x; + + if (t) + q->z = l ((&m + q->z)->w); + + if (s->colorspace) + q++; + } +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-1.c new file mode 100644 index 00000000000..48b8a8a6cbf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-1.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_load-1.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-2.c new file mode 100644 index 00000000000..acd2625f9f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_load-2.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-3.c new file mode 100644 index 00000000000..43ba9d489fc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-3.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_load-3.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-4.c new file mode 100644 index 00000000000..b32257e61b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-4.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_load-4.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-5.c new file mode 100644 index 00000000000..41402fbbd15 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-5.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_load-5.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-6.c new file mode 100644 index 00000000000..64eb789985b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-6.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_load-6.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-7.c new file mode 100644 index 00000000000..9b20bcc2996 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-7.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_load-7.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-1.c new file mode 100644 index 00000000000..dc577af816b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-1.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_load_run-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-2.c new file mode 100644 index 00000000000..0bb4e599816 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-2.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_load_run-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-3.c new file mode 100644 index 00000000000..3d70c0dbca6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-3.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_load_run-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-4.c new file mode 100644 index 00000000000..ca98fd52cbc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-4.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_load_run-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-5.c new file mode 100644 index 00000000000..190b95a6669 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-5.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_load_run-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-6.c new file mode 100644 index 00000000000..769d709ce50 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-6.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_load_run-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-7.c new file mode 100644 index 00000000000..bcd31f3229c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-7.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_load_run-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-1.c new file mode 100644 index 00000000000..ef40495d63e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-1.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_store-1.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-2.c new file mode 100644 index 00000000000..efb7c212ce9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_store-2.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-3.c new file mode 100644 index 00000000000..ff0f5b31baf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-3.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_store-3.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-4.c new file mode 100644 index 00000000000..271a239c6d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-4.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_store-4.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-5.c new file mode 100644 index 00000000000..faa5c2907b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-5.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_store-5.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-6.c new file mode 100644 index 00000000000..4188373487b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-6.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_store-6.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-7.c new file mode 100644 index 00000000000..b33541bc30f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-7.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_store-7.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-1.c new file mode 100644 index 00000000000..ec7b3811982 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-1.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_store_run-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-2.c new file mode 100644 index 00000000000..ca3b3d77136 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-2.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_store_run-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-3.c new file mode 100644 index 00000000000..e4fdea08dd2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-3.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_store_run-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-4.c new file mode 100644 index 00000000000..7f63d204349 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-4.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_store_run-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-5.c new file mode 100644 index 00000000000..df0448dcab9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-5.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_store_run-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-6.c new file mode 100644 index 00000000000..e6268b36098 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-6.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_store_run-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-7.c new file mode 100644 index 00000000000..0fdcb8ba85e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-7.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "mask_struct_store_run-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-1.c new file mode 100644 index 00000000000..96040d0b2ff --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-1.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */ + +#include "struct_vect-1.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*16,\s*e8,\s*m1,\s*t[au],\s*m[au]} 8 } } */ +/* { dg-final { scan-assembler-not {vsetvli} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-10.c new file mode 100644 index 00000000000..e0d2da42519 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-10.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect-10.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+} 0 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-11.c new file mode 100644 index 00000000000..79480750c6d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-11.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect-11.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+} 0 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-12.c new file mode 100644 index 00000000000..1d07036daac --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-12.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect-12.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+} 0 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-13.c new file mode 100644 index 00000000000..438a123c71b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-13.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect-13.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-14.c new file mode 100644 index 00000000000..84afb998edf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-14.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect-14.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-15.c new file mode 100644 index 00000000000..62c152ba720 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-15.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect-15.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-16.c new file mode 100644 index 00000000000..c9c986e28bf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-16.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect-16.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-17.c new file mode 100644 index 00000000000..b5508b24134 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-17.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect-17.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-18.c new file mode 100644 index 00000000000..a82a0ecf67a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-18.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect-18.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-2.c new file mode 100644 index 00000000000..0f32727cc9b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-2.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */ + +#include "struct_vect-2.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*8,\s*e16,\s*m1,\s*t[au],\s*m[au]} 8 } } */ +/* { dg-final { scan-assembler-not {vsetvli} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-3.c new file mode 100644 index 00000000000..e3525484a99 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-3.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */ + +#include "struct_vect-3.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*4,\s*e32,\s*m1,\s*t[au],\s*m[au]} 17 } } */ +/* { dg-final { scan-assembler-not {vsetvli} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-4.c new file mode 100644 index 00000000000..343f9f96bb6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-4.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */ + +#include "struct_vect-4.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*2,\s*e64,\s*m1,\s*t[au],\s*m[au]} 46 } } */ +/* { dg-final { scan-assembler-not {vsetvli} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-5.c new file mode 100644 index 00000000000..342051b67fc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-5.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */ + +#include "struct_vect-5.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*4,\s*e32,\s*m1,\s*t[au],\s*m[au]} 17 } } */ +/* { dg-final { scan-assembler-not {vsetvli} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-6.c new file mode 100644 index 00000000000..86c74910511 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-6.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect-6.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]} 0 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-7.c new file mode 100644 index 00000000000..c5dce07e196 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-7.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect-7.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+} 0 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-8.c new file mode 100644 index 00000000000..190cf8dca6b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-8.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect-8.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+} 0 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-9.c new file mode 100644 index 00000000000..1ffef4a5934 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-9.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect-9.c" + +/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+} 0 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-1.c new file mode 100644 index 00000000000..2a50b7133be --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-1.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */ + +#include "struct_vect_run-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-10.c new file mode 100644 index 00000000000..887a7f9a6e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-10.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v && riscv_zvfh } } } */ +/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect_run-10.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-11.c new file mode 100644 index 00000000000..f99db9b8f6c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-11.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect_run-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-12.c new file mode 100644 index 00000000000..3c320991a0f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-12.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect_run-12.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-13.c new file mode 100644 index 00000000000..588c728968a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-13.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect_run-13.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-14.c new file mode 100644 index 00000000000..7d4d1bfc899 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-14.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect_run-14.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-15.c new file mode 100644 index 00000000000..c462a1cb925 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-15.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect_run-15.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-16.c new file mode 100644 index 00000000000..35d0febb029 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-16.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect_run-16.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-17.c new file mode 100644 index 00000000000..4cedba48683 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-17.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect_run-17.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-18.c new file mode 100644 index 00000000000..2bf1cd6984d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-18.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect_run-18.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-2.c new file mode 100644 index 00000000000..36772aaf900 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-2.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */ + +#include "struct_vect_run-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-3.c new file mode 100644 index 00000000000..58201220915 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-3.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */ + +#include "struct_vect_run-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-4.c new file mode 100644 index 00000000000..4ac2c39c4ca --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-4.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */ + +#include "struct_vect_run-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-5.c new file mode 100644 index 00000000000..dd90a1771a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-5.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */ + +#include "struct_vect_run-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-6.c new file mode 100644 index 00000000000..0efbee0db9c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-6.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect_run-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-7.c new file mode 100644 index 00000000000..c08d13063f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-7.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect_run-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-8.c new file mode 100644 index 00000000000..404f5d664f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-8.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect_run-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-9.c new file mode 100644 index 00000000000..e14ceb9cbf8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-9.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */ + +#include "struct_vect_run-9.c"