From patchwork Mon Oct 14 11:10:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1996817 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=NrGJ2WQb; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4XRvjf3Br5z1xvK for ; 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X-CSE-ConnectionGUID: k6GEy1nRQ+KMfoHotrOUJw== X-CSE-MsgGUID: IoYvKDtfQ1a7ePW0hsTRrQ== X-IronPort-AV: E=McAfee;i="6700,10204,11224"; a="31129474" X-IronPort-AV: E=Sophos;i="6.11,202,1725346800"; d="scan'208";a="31129474" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Oct 2024 04:12:34 -0700 X-CSE-ConnectionGUID: yYM+kEHLQou9WvwGZPHQig== X-CSE-MsgGUID: wLehR6kvTC6uPnxbFIe1hQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,202,1725346800"; d="scan'208";a="114998485" Received: from panli.sh.intel.com ([10.239.154.73]) by orviesa001.jf.intel.com with ESMTP; 14 Oct 2024 04:12:31 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: richard.guenther@gmail.com, Tamar.Christina@arm.com, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH 01/11] Match: Support form 1 for vector signed integer SAT_TRUNC Date: Mon, 14 Oct 2024 19:10:48 +0800 Message-ID: <20241014111058.1033886-1-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li This patch would like to support the form 1 of the vector signed integer SAT_TRUNC. Aka below example: Form 1: #define DEF_VEC_SAT_S_TRUNC_FMT_1(NT, WT, NT_MIN, NT_MAX) \ void __attribute__((noinline)) \ vec_sat_s_trunc_##NT##_##WT##_fmt_1 (NT *out, WT *in, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \ { \ WT x = in[i]; \ NT trunc = (NT)x; \ out[i] = (WT)NT_MIN <= x && x <= (WT)NT_MAX \ ? trunc \ : x < 0 ? NT_MIN : NT_MAX; \ } \ } DEF_VEC_SAT_S_TRUNC_FMT_1(int32_t, int64_t, INT32_MIN, INT32_MAX) Before this patch: 48 │ _87 = .SELECT_VL (ivtmp_85, POLY_INT_CST [2, 2]); 49 │ ivtmp_64 = _87 * 8; 50 │ vect_x_14.10_67 = .MASK_LEN_LOAD (vectp_in.8_65, 64B, { -1, ... }, _87, 0); 51 │ vect_trunc_15.21_78 = (vector([2,2]) int) vect_x_14.10_67; 52 │ _61 = VIEW_CONVERT_EXPR(vect_x_14.10_67); 53 │ _32 = _61 >> 63; 54 │ vect_patt_52.16_73 = (vector([2,2]) int) _32; 55 │ vect__46.17_74 = VIEW_CONVERT_EXPR(vect_patt_52.16_73); 56 │ vect__47.18_75 = -vect__46.17_74; 57 │ vect__21.19_76 = VIEW_CONVERT_EXPR(vect__47.18_75); 58 │ vect_x.11_68 = VIEW_CONVERT_EXPR(vect_x_14.10_67); 59 │ vect__5.12_69 = vect_x.11_68 + { 2147483648, ... }; 60 │ mask__34.13_70 = vect__5.12_69 > { 4294967295, ... }; 61 │ _25 = .COND_XOR (mask__34.13_70, vect__21.19_76, { 2147483647, ... }, vect_trunc_15.21_78); 62 │ ivtmp_80 = _87 * 4; 63 │ .MASK_LEN_STORE (vectp_out.23_81, 32B, { -1, ... }, _87, 0, _25); 64 │ vectp_in.8_66 = vectp_in.8_65 + ivtmp_64; 65 │ vectp_out.23_82 = vectp_out.23_81 + ivtmp_80; 66 │ ivtmp_86 = ivtmp_85 - _87; After this patch: 38 │ _77 = .SELECT_VL (ivtmp_75, POLY_INT_CST [2, 2]); 39 │ ivtmp_65 = _77 * 8; 40 │ vect_x_14.10_68 = .MASK_LEN_LOAD (vectp_in.8_66, 64B, { -1, ... }, _77, 0); 41 │ vect_patt_53.11_69 = .SAT_TRUNC (vect_x_14.10_68); 42 │ ivtmp_70 = _77 * 4; 43 │ .MASK_LEN_STORE (vectp_out.12_71, 32B, { -1, ... }, _77, 0, vect_patt_53.11_69); 44 │ vectp_in.8_67 = vectp_in.8_66 + ivtmp_65; 45 │ vectp_out.12_72 = vectp_out.12_71 + ivtmp_70; 46 │ ivtmp_76 = ivtmp_75 - _77; The below test suites are passed for this patch. * The rv64gcv fully regression test. * The x86 bootstrap test. * The x86 fully regression test. gcc/ChangeLog: * match.pd: Refine matching for vector signed SAT_TRUNC form 1. Signed-off-by: Pan Li --- gcc/match.pd | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/gcc/match.pd b/gcc/match.pd index 2ab76f9d055..36195d0c920 100644 --- a/gcc/match.pd +++ b/gcc/match.pd @@ -3493,7 +3493,9 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) SAT_S_TRUNC(X) = (unsigned)X + NT_MAX + 1 > Unsigned_MAX ? (NT)X. */ (match (signed_integer_sat_trunc @0) (cond^ (gt (plus:c (convert@4 @0) INTEGER_CST@1) INTEGER_CST@2) - (bit_xor:c (negate (convert (lt @0 integer_zerop))) INTEGER_CST@3) + (bit_xor:c (nop_convert? + (negate (nop_convert? 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X-CSE-ConnectionGUID: ZnwbaxvWQyWeRg/vf5CYuQ== X-CSE-MsgGUID: S7JrwT80RDuic6qLiErNwg== X-IronPort-AV: E=McAfee;i="6700,10204,11224"; a="31129481" X-IronPort-AV: E=Sophos;i="6.11,202,1725346800"; d="scan'208";a="31129481" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Oct 2024 04:12:36 -0700 X-CSE-ConnectionGUID: vLi2XU7WQZiepld3PmNLlA== X-CSE-MsgGUID: +iyvDI2dQEmq9qaw0bHm6g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,202,1725346800"; d="scan'208";a="114998491" Received: from panli.sh.intel.com ([10.239.154.73]) by orviesa001.jf.intel.com with ESMTP; 14 Oct 2024 04:12:34 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: richard.guenther@gmail.com, Tamar.Christina@arm.com, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH 02/11] Vect: Try the pattern of vector signed integer SAT_TRUNC Date: Mon, 14 Oct 2024 19:10:49 +0800 Message-ID: <20241014111058.1033886-2-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241014111058.1033886-1-pan2.li@intel.com> References: <20241014111058.1033886-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li Almost the same as vector unsigned integer SAT_TRUNC, try to match the signed version during the vector pattern matching. The below test suites are passed for this patch. * The rv64gcv fully regression test. * The x86 bootstrap test. * The x86 fully regression test. gcc/ChangeLog: * tree-vect-patterns.cc (gimple_signed_integer_sat_trunc): Add new func decl for signed SAT_TRUNC. (vect_recog_sat_trunc_pattern): Try signed match pattern for the SAT_TRUNC. Signed-off-by: Pan Li --- gcc/tree-vect-patterns.cc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/gcc/tree-vect-patterns.cc b/gcc/tree-vect-patterns.cc index 746f100a084..ce5a528141f 100644 --- a/gcc/tree-vect-patterns.cc +++ b/gcc/tree-vect-patterns.cc @@ -4539,6 +4539,7 @@ extern bool gimple_unsigned_integer_sat_trunc (tree, tree*, tree (*)(tree)); extern bool gimple_signed_integer_sat_add (tree, tree*, tree (*)(tree)); extern bool gimple_signed_integer_sat_sub (tree, tree*, tree (*)(tree)); +extern bool gimple_signed_integer_sat_trunc (tree, tree*, tree (*)(tree)); static gimple * vect_recog_build_binary_gimple_stmt (vec_info *vinfo, stmt_vec_info stmt_info, @@ -4770,7 +4771,8 @@ vect_recog_sat_trunc_pattern (vec_info *vinfo, stmt_vec_info stmt_vinfo, tree lhs = gimple_assign_lhs (last_stmt); tree otype = TREE_TYPE (lhs); - if (gimple_unsigned_integer_sat_trunc (lhs, ops, NULL) + if ((gimple_unsigned_integer_sat_trunc (lhs, ops, NULL) + || gimple_signed_integer_sat_trunc (lhs, ops, NULL)) && type_has_mode_precision_p (otype)) { tree itype = TREE_TYPE (ops[0]); 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X-CSE-ConnectionGUID: nQrZsUfuQ0iMWHZtGxtd9A== X-CSE-MsgGUID: 4+9kHof8SpKzG68OxEvnZw== X-IronPort-AV: E=McAfee;i="6700,10204,11224"; a="31129490" X-IronPort-AV: E=Sophos;i="6.11,202,1725346800"; d="scan'208";a="31129490" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Oct 2024 04:12:39 -0700 X-CSE-ConnectionGUID: S3HsIC0YT9e7QalkXOV1Jg== X-CSE-MsgGUID: pJX7MTUHSBWJYV/QPAePWQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,202,1725346800"; d="scan'208";a="114998495" Received: from panli.sh.intel.com ([10.239.154.73]) by orviesa001.jf.intel.com with ESMTP; 14 Oct 2024 04:12:36 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: richard.guenther@gmail.com, Tamar.Christina@arm.com, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH 03/11] RISC-V: Implement vector SAT_TRUNC for signed integer Date: Mon, 14 Oct 2024 19:10:50 +0800 Message-ID: <20241014111058.1033886-3-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241014111058.1033886-1-pan2.li@intel.com> References: <20241014111058.1033886-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_ASCII_DIVIDERS, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li This patch would like to implement the sstrunc for vector signed integer. Form 1: #define DEF_VEC_SAT_S_TRUNC_FMT_1(NT, WT, NT_MIN, NT_MAX) \ void __attribute__((noinline)) \ vec_sat_s_trunc_##NT##_##WT##_fmt_1 (NT *out, WT *in, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \ { \ WT x = in[i]; \ NT trunc = (NT)x; \ out[i] = (WT)NT_MIN <= x && x <= (WT)NT_MAX \ ? trunc \ : x < 0 ? NT_MIN : NT_MAX; \ } \ } DEF_VEC_SAT_S_TRUNC_FMT_1(int32_t, int64_t, INT32_MIN, INT32_MAX) Before this patch: 27 │ vsetvli a5,a2,e64,m1,ta,ma 28 │ vle64.v v1,0(a1) 29 │ slli a3,a5,3 30 │ slli a4,a5,2 31 │ sub a2,a2,a5 32 │ add a1,a1,a3 33 │ vadd.vv v0,v1,v5 34 │ vsetvli zero,zero,e32,mf2,ta,ma 35 │ vnsrl.wx v2,v1,a6 36 │ vncvt.x.x.w v1,v1 37 │ vsetvli zero,zero,e64,m1,ta,ma 38 │ vmsgtu.vv v0,v0,v4 39 │ vsetvli zero,zero,e32,mf2,ta,mu 40 │ vneg.v v2,v2 41 │ vxor.vv v1,v2,v3,v0.t 42 │ vse32.v v1,0(a0) 43 │ add a0,a0,a4 44 │ bne a2,zero,.L3 After this patch: 16 │ vsetvli a5,a2,e32,mf2,ta,ma 17 │ vle64.v v1,0(a1) 18 │ slli a3,a5,3 19 │ slli a4,a5,2 20 │ sub a2,a2,a5 21 │ add a1,a1,a3 22 │ vnclip.wi v1,v1,0 23 │ vse32.v v1,0(a0) 24 │ add a0,a0,a4 25 │ bne a2,zero,.L3 The below test suites are passed for this patch. * The rv64gcv fully regression test. gcc/ChangeLog: * config/riscv/autovec.md (sstrunc2): Add new pattern sstrunc for double trunc. (sstrunc2): Ditto but for quad trunc. (sstrunc2): Ditto but for oct trunc. * config/riscv/riscv-protos.h (expand_vec_double_sstrunc): Add new func decl to expand double trunc. (expand_vec_quad_sstrunc): Ditto but for quad trunc. (expand_vec_oct_sstrunc): Ditto but for oct trunc. * config/riscv/riscv-v.cc (expand_vec_double_sstrunc): Add new func to expand double trunc. (expand_vec_quad_sstrunc): Ditto but for quad trunc. (expand_vec_oct_sstrunc): Ditto but for oct trunc. Signed-off-by: Pan Li --- gcc/config/riscv/autovec.md | 34 ++++++++++++++++++++++++ gcc/config/riscv/riscv-protos.h | 4 +++ gcc/config/riscv/riscv-v.cc | 46 +++++++++++++++++++++++++++++++++ 3 files changed, 84 insertions(+) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 7dc78a48874..82d65a95e7a 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -2779,6 +2779,40 @@ (define_expand "ustrunc2" } ) +(define_expand "sstrunc2" + [(match_operand: 0 "register_operand") + (match_operand:VWEXTI 1 "register_operand")] + "TARGET_VECTOR" + { + riscv_vector::expand_vec_double_sstrunc (operands[0], operands[1], + mode); + DONE; + } +) + +(define_expand "sstrunc2" + [(match_operand: 0 "register_operand") + (match_operand:VQEXTI 1 "register_operand")] + "TARGET_VECTOR" + { + riscv_vector::expand_vec_quad_sstrunc (operands[0], operands[1], mode, + mode); + DONE; + } +) + +(define_expand "sstrunc2" + [(match_operand: 0 "register_operand") + (match_operand:VOEXTI 1 "register_operand")] + "TARGET_VECTOR" + { + riscv_vector::expand_vec_oct_sstrunc (operands[0], operands[1], mode, + mode, + mode); + DONE; + } +) + ;; ========================================================================= ;; == Early break auto-vectorization patterns ;; ========================================================================= diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index b2f5d72f494..2b2378468e2 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -651,9 +651,13 @@ void expand_vec_ssadd (rtx, rtx, rtx, machine_mode); void expand_vec_ussub (rtx, rtx, rtx, machine_mode); void expand_vec_sssub (rtx, rtx, rtx, machine_mode); void expand_vec_double_ustrunc (rtx, rtx, machine_mode); +void expand_vec_double_sstrunc (rtx, rtx, machine_mode); void expand_vec_quad_ustrunc (rtx, rtx, machine_mode, machine_mode); +void expand_vec_quad_sstrunc (rtx, rtx, machine_mode, machine_mode); void expand_vec_oct_ustrunc (rtx, rtx, machine_mode, machine_mode, machine_mode); +void expand_vec_oct_sstrunc (rtx, rtx, machine_mode, machine_mode, + machine_mode); #endif bool sew64_scalar_helper (rtx *, rtx *, rtx, machine_mode, bool, void (*)(rtx *, rtx), enum avl_type); diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index fba35652cc2..65d36dc31d2 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -4927,6 +4927,22 @@ expand_vec_double_ustrunc (rtx op_0, rtx op_1, machine_mode vec_mode) emit_vlmax_insn (icode, BINARY_OP_VXRM_RNU, ops); } +/* Expand the standard name sstrunc2 for double vector mode, like + DI => SI. we can leverage the vector fixed point vector narrowing + fixed-point clip directly. */ + +void +expand_vec_double_sstrunc (rtx op_0, rtx op_1, machine_mode vec_mode) +{ + insn_code icode; + rtx zero = CONST0_RTX (Xmode); + enum unspec unspec = UNSPEC_VNCLIP; + rtx ops[] = {op_0, op_1, zero}; + + icode = code_for_pred_narrow_clip_scalar (unspec, vec_mode); + emit_vlmax_insn (icode, BINARY_OP_VXRM_RNU, ops); +} + /* Expand the standard name ustrunc2 for double vector mode, like DI => HI. we can leverage the vector fixed point vector narrowing fixed-point clip directly. */ @@ -4941,6 +4957,20 @@ expand_vec_quad_ustrunc (rtx op_0, rtx op_1, machine_mode vec_mode, expand_vec_double_ustrunc (op_0, double_rtx, double_mode); } +/* Expand the standard name sstrunc2 for quad vector mode, like + DI => HI. we can leverage the vector fixed point vector narrowing + fixed-point clip directly. */ + +void +expand_vec_quad_sstrunc (rtx op_0, rtx op_1, machine_mode vec_mode, + machine_mode double_mode) +{ + rtx double_rtx = gen_reg_rtx (double_mode); + + expand_vec_double_sstrunc (double_rtx, op_1, vec_mode); + expand_vec_double_sstrunc (op_0, double_rtx, double_mode); +} + /* Expand the standard name ustrunc2 for double vector mode, like DI => QI. we can leverage the vector fixed point vector narrowing fixed-point clip directly. */ @@ -4957,6 +4987,22 @@ expand_vec_oct_ustrunc (rtx op_0, rtx op_1, machine_mode vec_mode, expand_vec_double_ustrunc (op_0, quad_rtx, quad_mode); } +/* Expand the standard name sstrunc2 for oct vector mode, like + DI => QI. we can leverage the vector fixed point vector narrowing + fixed-point clip directly. */ + +void +expand_vec_oct_sstrunc (rtx op_0, rtx op_1, machine_mode vec_mode, + machine_mode double_mode, machine_mode quad_mode) +{ + rtx double_rtx = gen_reg_rtx (double_mode); + rtx quad_rtx = gen_reg_rtx (quad_mode); + + expand_vec_double_sstrunc (double_rtx, op_1, vec_mode); + expand_vec_double_sstrunc (quad_rtx, double_rtx, double_mode); + expand_vec_double_sstrunc (op_0, quad_rtx, quad_mode); +} + /* Vectorize popcount by the Wilkes-Wheeler-Gill algorithm that libgcc uses as well. */ void From patchwork Mon Oct 14 11:10:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1996826 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=B9Se1toD; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; 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\ for (i = 0; i < limit; i++) \ { \ WT x = in[i]; \ NT trunc = (NT)x; \ out[i] = (WT)NT_MIN <= x && x <= (WT)NT_MAX \ ? trunc \ : x < 0 ? NT_MIN : NT_MAX; \ } \ } The below test are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/unop/vec_sat_data.h: Add test data for signed SAT_TRUNC. * gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper macros. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i16-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i32-to-i16.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i32-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i64-to-i16.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i64-to-i32.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i64-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i16-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i32-to-i16.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i32-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i64-to-i16.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i64-to-i32.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i64-to-i8.c: New test. Signed-off-by: Pan Li --- .../riscv/rvv/autovec/unop/vec_sat_data.h | 291 ++++++++++++++++++ .../unop/vec_sat_s_trunc-1-i16-to-i8.c | 9 + .../unop/vec_sat_s_trunc-1-i32-to-i16.c | 9 + .../unop/vec_sat_s_trunc-1-i32-to-i8.c | 9 + .../unop/vec_sat_s_trunc-1-i64-to-i16.c | 9 + .../unop/vec_sat_s_trunc-1-i64-to-i32.c | 9 + .../unop/vec_sat_s_trunc-1-i64-to-i8.c | 9 + .../unop/vec_sat_s_trunc-run-1-i16-to-i8.c | 16 + .../unop/vec_sat_s_trunc-run-1-i32-to-i16.c | 16 + .../unop/vec_sat_s_trunc-run-1-i32-to-i8.c | 16 + .../unop/vec_sat_s_trunc-run-1-i64-to-i16.c | 16 + .../unop/vec_sat_s_trunc-run-1-i64-to-i32.c | 16 + .../unop/vec_sat_s_trunc-run-1-i64-to-i8.c | 16 + .../riscv/rvv/autovec/vec_sat_arith.h | 22 ++ 14 files changed, 463 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i16-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i32-to-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i32-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i64-to-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i64-to-i32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i64-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i16-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i32-to-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i32-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i64-to-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i64-to-i32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i64-to-i8.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_data.h index 6b23ec809f6..a3643c5e121 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_data.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_data.h @@ -25,6 +25,15 @@ TEST_UNARY_STRUCT(uint16_t, uint64_t) TEST_UNARY_STRUCT(uint32_t, uint64_t) +TEST_UNARY_STRUCT(int8_t, int16_t) +TEST_UNARY_STRUCT(int8_t, int32_t) +TEST_UNARY_STRUCT(int8_t, int64_t) + +TEST_UNARY_STRUCT(int16_t, int32_t) +TEST_UNARY_STRUCT(int16_t, int64_t) + +TEST_UNARY_STRUCT(int32_t, int64_t) + TEST_UNARY_STRUCT_DECL(uint8_t, uint16_t) \ TEST_UNARY_DATA(uint8_t, uint16_t)[] = { @@ -391,4 +400,286 @@ TEST_UNARY_STRUCT_DECL(uint32_t, uint64_t) \ }, }; +TEST_UNARY_STRUCT_DECL(int8_t, int16_t) \ + TEST_UNARY_DATA(int8_t, int16_t)[] = +{ + { + { + 0, 0, 0, 0, + -1, -1, -1, -1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + }, + { + { + 127, 127, 127, 127, + 128, 128, 128, 128, + -128, -128, -128, -128, + -129, -129, -129, -129, + }, + { + 127, 127, 127, 127, + 127, 127, 127, 127, + -128, -128, -128, -128, + -128, -128, -128, -128, + }, + }, + { + { + 32766, 32766, 32766, 32766, + 32767, 32767, 32767, 32767, + -32767, -32767, -32767, -32767, + -32768, -32768, -32768, -32768, + }, + { + 127, 127, 127, 127, + 127, 127, 127, 127, + -128, -128, -128, -128, + -128, -128, -128, -128, + }, + }, +}; + +TEST_UNARY_STRUCT_DECL(int8_t, int32_t) \ + TEST_UNARY_DATA(int8_t, int32_t)[] = +{ + { + { + 0, 0, 0, 0, + -1, -1, -1, -1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + }, + { + { + 127, 127, 127, 127, + 128, 128, 128, 128, + -128, -128, -128, -128, + -129, -129, -129, -129, + }, + { + 127, 127, 127, 127, + 127, 127, 127, 127, + -128, -128, -128, -128, + -128, -128, -128, -128, + }, + }, + { + { + 2147483646, 2147483646, 2147483646, 2147483646, + 2147483647, 2147483647, 2147483647, 2147483647, + -2147483647, -2147483647, -2147483647, -2147483647, + -2147483648, -2147483648, -2147483648, -2147483648, + }, + { + 127, 127, 127, 127, + 127, 127, 127, 127, + -128, -128, -128, -128, + -128, -128, -128, -128, + }, + }, +}; + +TEST_UNARY_STRUCT_DECL(int8_t, int64_t) \ + TEST_UNARY_DATA(int8_t, int64_t)[] = +{ + { + { + 0, 0, 0, 0, + -1, -1, -1, -1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + }, + { + { + 127, 127, 127, 127, + 128, 128, 128, 128, + -128, -128, -128, -128, + -129, -129, -129, -129, + }, + { + 127, 127, 127, 127, + 127, 127, 127, 127, + -128, -128, -128, -128, + -128, -128, -128, -128, + }, + }, + { + { + 9223372036854775806ll, 9223372036854775806ll, 9223372036854775806ll, 9223372036854775806ll, + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + -9223372036854775807ll, -9223372036854775807ll, -9223372036854775807ll, -9223372036854775807ll, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + }, + { + 127, 127, 127, 127, + 127, 127, 127, 127, + -128, -128, -128, -128, + -128, -128, -128, -128, + }, + }, +}; + +TEST_UNARY_STRUCT_DECL(int16_t, int32_t) \ + TEST_UNARY_DATA(int16_t, int32_t)[] = +{ + { + { + 0, 0, 0, 0, + -1, -1, -1, -1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + }, + { + { + 32767, 32767, 32767, 32767, + 32768, 32768, 32768, 32768, + -32768, -32768, -32768, -32768, + -32769, -32769, -32769, -32769, + }, + { + 32767, 32767, 32767, 32767, + 32767, 32767, 32767, 32767, + -32768, -32768, -32768, -32768, + -32768, -32768, -32768, -32768, + }, + }, + { + { + 2147483646, 2147483646, 2147483646, 2147483646, + 2147483647, 2147483647, 2147483647, 2147483647, + -2147483647, -2147483647, -2147483647, -2147483647, + -2147483648, -2147483648, -2147483648, -2147483648, + }, + { + 32767, 32767, 32767, 32767, + 32767, 32767, 32767, 32767, + -32768, -32768, -32768, -32768, + -32768, -32768, -32768, -32768, + }, + }, +}; + +TEST_UNARY_STRUCT_DECL(int16_t, int64_t) \ + TEST_UNARY_DATA(int16_t, int64_t)[] = +{ + { + { + 0, 0, 0, 0, + -1, -1, -1, -1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + }, + { + { + 32767, 32767, 32767, 32767, + 32768, 32768, 32768, 32768, + -32768, -32768, -32768, -32768, + -32769, -32769, -32769, -32769, + }, + { + 32767, 32767, 32767, 32767, + 32767, 32767, 32767, 32767, + -32768, -32768, -32768, -32768, + -32768, -32768, -32768, -32768, + }, + }, + { + { + 9223372036854775806ll, 9223372036854775806ll, 9223372036854775806ll, 9223372036854775806ll, + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + -9223372036854775807ll, -9223372036854775807ll, -9223372036854775807ll, -9223372036854775807ll, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + }, + { + 32767, 32767, 32767, 32767, + 32767, 32767, 32767, 32767, + -32768, -32768, -32768, -32768, + -32768, -32768, -32768, -32768, + }, + }, +}; + +TEST_UNARY_STRUCT_DECL(int32_t, int64_t) \ + TEST_UNARY_DATA(int32_t, int64_t)[] = +{ + { + { + 0, 0, 0, 0, + -1, -1, -1, -1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + }, + { + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483649, -2147483649, -2147483649, -2147483649, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483647, 2147483647, 2147483647, 2147483647, + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483648, -2147483648, -2147483648, -2147483648, + }, + }, + { + { + 9223372036854775806ll, 9223372036854775806ll, 9223372036854775806ll, 9223372036854775806ll, + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + -9223372036854775807ll, -9223372036854775807ll, -9223372036854775807ll, -9223372036854775807ll, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483647, 2147483647, 2147483647, 2147483647, + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483648, -2147483648, -2147483648, -2147483648, + }, + }, +}; + #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i16-to-i8.c new file mode 100644 index 00000000000..dd87dfd0f64 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i16-to-i8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_1(int8_t, int16_t, INT8_MIN, INT8_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i32-to-i16.c new file mode 100644 index 00000000000..caf646f9520 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i32-to-i16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_1(int16_t, int32_t, INT16_MIN, INT16_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i32-to-i8.c new file mode 100644 index 00000000000..f06267a5c47 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i32-to-i8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_1(int8_t, int32_t, INT8_MIN, INT8_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i64-to-i16.c new file mode 100644 index 00000000000..f784937fd48 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i64-to-i16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_1(int16_t, int64_t, INT16_MIN, INT16_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i64-to-i32.c new file mode 100644 index 00000000000..1e5289c751c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i64-to-i32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_1(int32_t, int64_t, INT32_MIN, INT32_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i64-to-i8.c new file mode 100644 index 00000000000..2fb604b7ddc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i64-to-i8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_1(int8_t, int64_t, INT8_MIN, INT8_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i16-to-i8.c new file mode 100644 index 00000000000..508cf348fc9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i16-to-i8.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int8_t +#define T2 int16_t + +DEF_VEC_SAT_S_TRUNC_FMT_1_WRAP(T1, T2, INT8_MIN, INT8_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_1_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i32-to-i16.c new file mode 100644 index 00000000000..3b7c3b6a882 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i32-to-i16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int16_t +#define T2 int32_t + +DEF_VEC_SAT_S_TRUNC_FMT_1_WRAP(T1, T2, INT16_MIN, INT16_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_1_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i32-to-i8.c new file mode 100644 index 00000000000..508cf348fc9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i32-to-i8.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int8_t +#define T2 int16_t + +DEF_VEC_SAT_S_TRUNC_FMT_1_WRAP(T1, T2, INT8_MIN, INT8_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_1_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i64-to-i16.c new file mode 100644 index 00000000000..4a049ce679a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i64-to-i16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int16_t +#define T2 int64_t + +DEF_VEC_SAT_S_TRUNC_FMT_1_WRAP(T1, T2, INT16_MIN, INT16_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_1_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i64-to-i32.c new file mode 100644 index 00000000000..15b6670b1c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i64-to-i32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int32_t +#define T2 int64_t + +DEF_VEC_SAT_S_TRUNC_FMT_1_WRAP(T1, T2, INT32_MIN, INT32_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_1_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i64-to-i8.c new file mode 100644 index 00000000000..5a1dd857b44 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i64-to-i8.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int8_t +#define T2 int64_t + +DEF_VEC_SAT_S_TRUNC_FMT_1_WRAP(T1, T2, INT8_MIN, INT8_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_1_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h index b5ed662f3a9..2c98e15fd2b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h @@ -647,6 +647,23 @@ vec_sat_u_trunc_##NT##_##WT##_fmt_4 (NT *out, WT *in, unsigned limit) \ } #define DEF_VEC_SAT_U_TRUNC_FMT_4_WRAP(NT, WT) DEF_VEC_SAT_U_TRUNC_FMT_4(NT, WT) +#define DEF_VEC_SAT_S_TRUNC_FMT_1(NT, WT, NT_MIN, NT_MAX) \ +void __attribute__((noinline)) \ +vec_sat_s_trunc_##NT##_##WT##_fmt_1 (NT *out, WT *in, unsigned limit) \ +{ \ + unsigned i; \ + for (i = 0; i < limit; i++) \ + { \ + WT x = in[i]; \ + NT trunc = (NT)x; \ + out[i] = (WT)NT_MIN <= x && x <= (WT)NT_MAX \ + ? trunc \ + : x < 0 ? NT_MIN : NT_MAX; \ + } \ +} +#define DEF_VEC_SAT_S_TRUNC_FMT_1_WRAP(NT, WT, NT_MIN, NT_MAX) \ + DEF_VEC_SAT_S_TRUNC_FMT_1(NT, WT, NT_MIN, NT_MAX) + #define RUN_VEC_SAT_U_TRUNC_FMT_1(NT, WT, out, in, N) \ vec_sat_u_trunc_##NT##_##WT##_fmt_1 (out, in, N) #define RUN_VEC_SAT_U_TRUNC_FMT_1_WRAP(NT, WT, out, in, N) \ @@ -667,4 +684,9 @@ vec_sat_u_trunc_##NT##_##WT##_fmt_4 (NT *out, WT *in, unsigned limit) \ #define RUN_VEC_SAT_U_TRUNC_FMT_4_WRAP(NT, WT, out, in, N) \ RUN_VEC_SAT_U_TRUNC_FMT_4(NT, WT, out, in, N) +#define RUN_VEC_SAT_S_TRUNC_FMT_1(NT, WT, out, in, N) \ + vec_sat_s_trunc_##NT##_##WT##_fmt_1 (out, in, N) +#define RUN_VEC_SAT_S_TRUNC_FMT_1_WRAP(NT, WT, out, in, N) \ + RUN_VEC_SAT_S_TRUNC_FMT_1(NT, WT, out, in, N) + #endif From patchwork Mon Oct 14 11:10:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1996828 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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14 Oct 2024 04:12:44 -0700 X-CSE-ConnectionGUID: hIUBkPoSR5yb2nY+JTu9lw== X-CSE-MsgGUID: /8LURRB/RTyQphAW8AdWgA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,202,1725346800"; d="scan'208";a="114998512" Received: from panli.sh.intel.com ([10.239.154.73]) by orviesa001.jf.intel.com with ESMTP; 14 Oct 2024 04:12:41 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: richard.guenther@gmail.com, Tamar.Christina@arm.com, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH 05/11] RISC-V: Add testcases for form 2 of vector signed SAT_TRUNC Date: Mon, 14 Oct 2024 19:10:52 +0800 Message-ID: <20241014111058.1033886-5-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241014111058.1033886-1-pan2.li@intel.com> References: <20241014111058.1033886-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li Form 2: #define DEF_VEC_SAT_S_TRUNC_FMT_2(NT, WT, NT_MIN, NT_MAX) \ void __attribute__((noinline)) \ vec_sat_s_trunc_##NT##_##WT##_fmt_2 (NT *out, WT *in, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \ { \ WT x = in[i]; \ NT trunc = (NT)x; \ out[i] = (WT)NT_MIN < x && x < (WT)NT_MAX \ ? trunc \ : x < 0 ? NT_MIN : NT_MAX; \ } \ } The below test are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper macros. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i16-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i32-to-i16.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i32-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i64-to-i16.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i64-to-i32.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i64-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i16-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i32-to-i16.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i32-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i64-to-i16.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i64-to-i32.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i64-to-i8.c: New test. Signed-off-by: Pan Li --- .../unop/vec_sat_s_trunc-2-i16-to-i8.c | 9 ++++++++ .../unop/vec_sat_s_trunc-2-i32-to-i16.c | 9 ++++++++ .../unop/vec_sat_s_trunc-2-i32-to-i8.c | 9 ++++++++ .../unop/vec_sat_s_trunc-2-i64-to-i16.c | 9 ++++++++ .../unop/vec_sat_s_trunc-2-i64-to-i32.c | 9 ++++++++ .../unop/vec_sat_s_trunc-2-i64-to-i8.c | 9 ++++++++ .../unop/vec_sat_s_trunc-run-2-i16-to-i8.c | 16 ++++++++++++++ .../unop/vec_sat_s_trunc-run-2-i32-to-i16.c | 16 ++++++++++++++ .../unop/vec_sat_s_trunc-run-2-i32-to-i8.c | 16 ++++++++++++++ .../unop/vec_sat_s_trunc-run-2-i64-to-i16.c | 16 ++++++++++++++ .../unop/vec_sat_s_trunc-run-2-i64-to-i32.c | 16 ++++++++++++++ .../unop/vec_sat_s_trunc-run-2-i64-to-i8.c | 16 ++++++++++++++ .../riscv/rvv/autovec/vec_sat_arith.h | 22 +++++++++++++++++++ 13 files changed, 172 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i16-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i32-to-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i32-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i64-to-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i64-to-i32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i64-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i16-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i32-to-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i32-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i64-to-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i64-to-i32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i64-to-i8.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i16-to-i8.c new file mode 100644 index 00000000000..3e26e788c08 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i16-to-i8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_2(int8_t, int16_t, INT8_MIN, INT8_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i32-to-i16.c new file mode 100644 index 00000000000..63797705a04 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i32-to-i16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_2(int16_t, int32_t, INT16_MIN, INT16_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i32-to-i8.c new file mode 100644 index 00000000000..aa996f3e416 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i32-to-i8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_2(int8_t, int32_t, INT8_MIN, INT8_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i64-to-i16.c new file mode 100644 index 00000000000..2a15556632d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i64-to-i16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_2(int16_t, int64_t, INT16_MIN, INT16_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i64-to-i32.c new file mode 100644 index 00000000000..d9649fc8656 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i64-to-i32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_2(int32_t, int64_t, INT32_MIN, INT32_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i64-to-i8.c new file mode 100644 index 00000000000..1ad2b3f2546 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i64-to-i8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_2(int8_t, int64_t, INT8_MIN, INT8_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i16-to-i8.c new file mode 100644 index 00000000000..a98447de11f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i16-to-i8.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int8_t +#define T2 int16_t + +DEF_VEC_SAT_S_TRUNC_FMT_2_WRAP(T1, T2, INT8_MIN, INT8_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_2_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i32-to-i16.c new file mode 100644 index 00000000000..93f40b674fd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i32-to-i16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int16_t +#define T2 int32_t + +DEF_VEC_SAT_S_TRUNC_FMT_2_WRAP(T1, T2, INT16_MIN, INT16_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_2_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i32-to-i8.c new file mode 100644 index 00000000000..a98447de11f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i32-to-i8.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int8_t +#define T2 int16_t + +DEF_VEC_SAT_S_TRUNC_FMT_2_WRAP(T1, T2, INT8_MIN, INT8_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_2_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i64-to-i16.c new file mode 100644 index 00000000000..c946ac32264 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i64-to-i16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int16_t +#define T2 int64_t + +DEF_VEC_SAT_S_TRUNC_FMT_2_WRAP(T1, T2, INT16_MIN, INT16_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_2_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i64-to-i32.c new file mode 100644 index 00000000000..1d3b03471f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i64-to-i32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int32_t +#define T2 int64_t + +DEF_VEC_SAT_S_TRUNC_FMT_2_WRAP(T1, T2, INT32_MIN, INT32_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_2_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i64-to-i8.c new file mode 100644 index 00000000000..98a637e91e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i64-to-i8.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int8_t +#define T2 int64_t + +DEF_VEC_SAT_S_TRUNC_FMT_2_WRAP(T1, T2, INT8_MIN, INT8_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_2_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h index 2c98e15fd2b..5c8436f7e28 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h @@ -664,6 +664,23 @@ vec_sat_s_trunc_##NT##_##WT##_fmt_1 (NT *out, WT *in, unsigned limit) \ #define DEF_VEC_SAT_S_TRUNC_FMT_1_WRAP(NT, WT, NT_MIN, NT_MAX) \ DEF_VEC_SAT_S_TRUNC_FMT_1(NT, WT, NT_MIN, NT_MAX) +#define DEF_VEC_SAT_S_TRUNC_FMT_2(NT, WT, NT_MIN, NT_MAX) \ +void __attribute__((noinline)) \ +vec_sat_s_trunc_##NT##_##WT##_fmt_2 (NT *out, WT *in, unsigned limit) \ +{ \ + unsigned i; \ + for (i = 0; i < limit; i++) \ + { \ + WT x = in[i]; \ + NT trunc = (NT)x; \ + out[i] = (WT)NT_MIN < x && x < (WT)NT_MAX \ + ? trunc \ + : x < 0 ? NT_MIN : NT_MAX; \ + } \ +} +#define DEF_VEC_SAT_S_TRUNC_FMT_2_WRAP(NT, WT, NT_MIN, NT_MAX) \ + DEF_VEC_SAT_S_TRUNC_FMT_2(NT, WT, NT_MIN, NT_MAX) + #define RUN_VEC_SAT_U_TRUNC_FMT_1(NT, WT, out, in, N) \ vec_sat_u_trunc_##NT##_##WT##_fmt_1 (out, in, N) #define RUN_VEC_SAT_U_TRUNC_FMT_1_WRAP(NT, WT, out, in, N) \ @@ -689,4 +706,9 @@ vec_sat_s_trunc_##NT##_##WT##_fmt_1 (NT *out, WT *in, unsigned limit) \ #define RUN_VEC_SAT_S_TRUNC_FMT_1_WRAP(NT, WT, out, in, N) \ RUN_VEC_SAT_S_TRUNC_FMT_1(NT, WT, out, in, N) +#define RUN_VEC_SAT_S_TRUNC_FMT_2(NT, WT, out, in, N) \ + vec_sat_s_trunc_##NT##_##WT##_fmt_2 (out, in, N) +#define RUN_VEC_SAT_S_TRUNC_FMT_2_WRAP(NT, WT, out, in, N) \ + RUN_VEC_SAT_S_TRUNC_FMT_2(NT, WT, out, in, N) + #endif From patchwork Mon Oct 14 11:10:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1996821 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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14 Oct 2024 04:12:47 -0700 X-CSE-ConnectionGUID: vjBsKcwzSwKj8LBg/Hl7Xg== X-CSE-MsgGUID: DsxL/OkFT/iQ5pHfeo/d/A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,202,1725346800"; d="scan'208";a="114998522" Received: from panli.sh.intel.com ([10.239.154.73]) by orviesa001.jf.intel.com with ESMTP; 14 Oct 2024 04:12:44 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: richard.guenther@gmail.com, Tamar.Christina@arm.com, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH 06/11] RISC-V: Add testcases for form 3 of vector signed SAT_TRUNC Date: Mon, 14 Oct 2024 19:10:53 +0800 Message-ID: <20241014111058.1033886-6-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241014111058.1033886-1-pan2.li@intel.com> References: <20241014111058.1033886-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li Form 3: #define DEF_VEC_SAT_S_TRUNC_FMT_3(NT, WT, NT_MIN, NT_MAX) \ void __attribute__((noinline)) \ vec_sat_s_trunc_##NT##_##WT##_fmt_3 (NT *out, WT *in, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \ { \ WT x = in[i]; \ NT trunc = (NT)x; \ out[i] = (WT)NT_MIN < x && x < (WT)NT_MAX \ ? trunc \ : x < 0 ? NT_MIN : NT_MAX; \ } \ } The below test are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper macros. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i16-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i32-to-i16.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i32-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i64-to-i16.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i64-to-i32.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i64-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i16-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i32-to-i16.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i32-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i64-to-i16.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i64-to-i32.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i64-to-i8.c: New test. Signed-off-by: Pan Li --- .../unop/vec_sat_s_trunc-3-i16-to-i8.c | 9 ++++++++ .../unop/vec_sat_s_trunc-3-i32-to-i16.c | 9 ++++++++ .../unop/vec_sat_s_trunc-3-i32-to-i8.c | 9 ++++++++ .../unop/vec_sat_s_trunc-3-i64-to-i16.c | 9 ++++++++ .../unop/vec_sat_s_trunc-3-i64-to-i32.c | 9 ++++++++ .../unop/vec_sat_s_trunc-3-i64-to-i8.c | 9 ++++++++ .../unop/vec_sat_s_trunc-run-3-i16-to-i8.c | 16 ++++++++++++++ .../unop/vec_sat_s_trunc-run-3-i32-to-i16.c | 16 ++++++++++++++ .../unop/vec_sat_s_trunc-run-3-i32-to-i8.c | 16 ++++++++++++++ .../unop/vec_sat_s_trunc-run-3-i64-to-i16.c | 16 ++++++++++++++ .../unop/vec_sat_s_trunc-run-3-i64-to-i32.c | 16 ++++++++++++++ .../unop/vec_sat_s_trunc-run-3-i64-to-i8.c | 16 ++++++++++++++ .../riscv/rvv/autovec/vec_sat_arith.h | 22 +++++++++++++++++++ 13 files changed, 172 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i16-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i32-to-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i32-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i64-to-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i64-to-i32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i64-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i16-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i32-to-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i32-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i64-to-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i64-to-i32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i64-to-i8.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i16-to-i8.c new file mode 100644 index 00000000000..392366def06 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i16-to-i8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_3(int8_t, int16_t, INT8_MIN, INT8_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i32-to-i16.c new file mode 100644 index 00000000000..2b16049994a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i32-to-i16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_3(int16_t, int32_t, INT16_MIN, INT16_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i32-to-i8.c new file mode 100644 index 00000000000..b444d2ea9c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i32-to-i8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_3(int8_t, int32_t, INT8_MIN, INT8_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i64-to-i16.c new file mode 100644 index 00000000000..06606581e8f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i64-to-i16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_3(int16_t, int64_t, INT16_MIN, INT16_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i64-to-i32.c new file mode 100644 index 00000000000..72ec727274b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i64-to-i32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_3(int32_t, int64_t, INT32_MIN, INT32_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i64-to-i8.c new file mode 100644 index 00000000000..7915d5417a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i64-to-i8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_3(int8_t, int64_t, INT8_MIN, INT8_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i16-to-i8.c new file mode 100644 index 00000000000..0b658f3d0aa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i16-to-i8.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int8_t +#define T2 int16_t + +DEF_VEC_SAT_S_TRUNC_FMT_3_WRAP(T1, T2, INT8_MIN, INT8_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_3_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i32-to-i16.c new file mode 100644 index 00000000000..41e1789dd62 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i32-to-i16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int16_t +#define T2 int32_t + +DEF_VEC_SAT_S_TRUNC_FMT_3_WRAP(T1, T2, INT16_MIN, INT16_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_3_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i32-to-i8.c new file mode 100644 index 00000000000..0b658f3d0aa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i32-to-i8.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int8_t +#define T2 int16_t + +DEF_VEC_SAT_S_TRUNC_FMT_3_WRAP(T1, T2, INT8_MIN, INT8_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_3_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i64-to-i16.c new file mode 100644 index 00000000000..28cd5c806f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i64-to-i16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int16_t +#define T2 int64_t + +DEF_VEC_SAT_S_TRUNC_FMT_3_WRAP(T1, T2, INT16_MIN, INT16_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_3_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i64-to-i32.c new file mode 100644 index 00000000000..a6501f93df7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i64-to-i32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int32_t +#define T2 int64_t + +DEF_VEC_SAT_S_TRUNC_FMT_3_WRAP(T1, T2, INT32_MIN, INT32_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_3_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i64-to-i8.c new file mode 100644 index 00000000000..eef36e8dbdb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i64-to-i8.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int8_t +#define T2 int64_t + +DEF_VEC_SAT_S_TRUNC_FMT_3_WRAP(T1, T2, INT8_MIN, INT8_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_3_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h index 5c8436f7e28..c0524bae2d0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h @@ -681,6 +681,23 @@ vec_sat_s_trunc_##NT##_##WT##_fmt_2 (NT *out, WT *in, unsigned limit) \ #define DEF_VEC_SAT_S_TRUNC_FMT_2_WRAP(NT, WT, NT_MIN, NT_MAX) \ DEF_VEC_SAT_S_TRUNC_FMT_2(NT, WT, NT_MIN, NT_MAX) +#define DEF_VEC_SAT_S_TRUNC_FMT_3(NT, WT, NT_MIN, NT_MAX) \ +void __attribute__((noinline)) \ +vec_sat_s_trunc_##NT##_##WT##_fmt_3 (NT *out, WT *in, unsigned limit) \ +{ \ + unsigned i; \ + for (i = 0; i < limit; i++) \ + { \ + WT x = in[i]; \ + NT trunc = (NT)x; \ + out[i] = (WT)NT_MIN < x && x <= (WT)NT_MAX \ + ? trunc \ + : x < 0 ? NT_MIN : NT_MAX; \ + } \ +} +#define DEF_VEC_SAT_S_TRUNC_FMT_3_WRAP(NT, WT, NT_MIN, NT_MAX) \ + DEF_VEC_SAT_S_TRUNC_FMT_3(NT, WT, NT_MIN, NT_MAX) + #define RUN_VEC_SAT_U_TRUNC_FMT_1(NT, WT, out, in, N) \ vec_sat_u_trunc_##NT##_##WT##_fmt_1 (out, in, N) #define RUN_VEC_SAT_U_TRUNC_FMT_1_WRAP(NT, WT, out, in, N) \ @@ -711,4 +728,9 @@ vec_sat_s_trunc_##NT##_##WT##_fmt_2 (NT *out, WT *in, unsigned limit) \ #define RUN_VEC_SAT_S_TRUNC_FMT_2_WRAP(NT, WT, out, in, N) \ RUN_VEC_SAT_S_TRUNC_FMT_2(NT, WT, out, in, N) +#define RUN_VEC_SAT_S_TRUNC_FMT_3(NT, WT, out, in, N) \ + vec_sat_s_trunc_##NT##_##WT##_fmt_3 (out, in, N) +#define RUN_VEC_SAT_S_TRUNC_FMT_3_WRAP(NT, WT, out, in, N) \ + RUN_VEC_SAT_S_TRUNC_FMT_3(NT, WT, out, in, N) + #endif From patchwork Mon Oct 14 11:10:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1996819 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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14 Oct 2024 04:12:49 -0700 X-CSE-ConnectionGUID: mn30+NV0RuO8PgEBowEUaA== X-CSE-MsgGUID: 6cJNd0nKTbCynYpAGHDj8A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,202,1725346800"; d="scan'208";a="114998532" Received: from panli.sh.intel.com ([10.239.154.73]) by orviesa001.jf.intel.com with ESMTP; 14 Oct 2024 04:12:46 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: richard.guenther@gmail.com, Tamar.Christina@arm.com, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH 07/11] RISC-V: Add testcases for form 4 of vector signed SAT_TRUNC Date: Mon, 14 Oct 2024 19:10:54 +0800 Message-ID: <20241014111058.1033886-7-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241014111058.1033886-1-pan2.li@intel.com> References: <20241014111058.1033886-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li Form 4: #define DEF_VEC_SAT_S_TRUNC_FMT_4(NT, WT, NT_MIN, NT_MAX) \ void __attribute__((noinline)) \ vec_sat_s_trunc_##NT##_##WT##_fmt_4 (NT *out, WT *in, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \ { \ WT x = in[i]; \ NT trunc = (NT)x; \ out[i] = (WT)NT_MIN <= x && x < (WT)NT_MAX \ ? trunc \ : x < 0 ? NT_MIN : NT_MAX; \ } \ } The below test are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper macros. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i16-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i32-to-i16.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i32-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i64-to-i16.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i64-to-i32.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i64-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i16-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i32-to-i16.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i32-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i64-to-i16.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i64-to-i32.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i64-to-i8.c: New test. Signed-off-by: Pan Li --- .../unop/vec_sat_s_trunc-4-i16-to-i8.c | 9 ++++++++ .../unop/vec_sat_s_trunc-4-i32-to-i16.c | 9 ++++++++ .../unop/vec_sat_s_trunc-4-i32-to-i8.c | 9 ++++++++ .../unop/vec_sat_s_trunc-4-i64-to-i16.c | 9 ++++++++ .../unop/vec_sat_s_trunc-4-i64-to-i32.c | 9 ++++++++ .../unop/vec_sat_s_trunc-4-i64-to-i8.c | 9 ++++++++ .../unop/vec_sat_s_trunc-run-4-i16-to-i8.c | 16 ++++++++++++++ .../unop/vec_sat_s_trunc-run-4-i32-to-i16.c | 16 ++++++++++++++ .../unop/vec_sat_s_trunc-run-4-i32-to-i8.c | 16 ++++++++++++++ .../unop/vec_sat_s_trunc-run-4-i64-to-i16.c | 16 ++++++++++++++ .../unop/vec_sat_s_trunc-run-4-i64-to-i32.c | 16 ++++++++++++++ .../unop/vec_sat_s_trunc-run-4-i64-to-i8.c | 16 ++++++++++++++ .../riscv/rvv/autovec/vec_sat_arith.h | 22 +++++++++++++++++++ 13 files changed, 172 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i16-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i32-to-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i32-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i64-to-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i64-to-i32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i64-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i16-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i32-to-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i32-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i64-to-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i64-to-i32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i64-to-i8.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i16-to-i8.c new file mode 100644 index 00000000000..2ac96aa1a35 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i16-to-i8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_4(int8_t, int16_t, INT8_MIN, INT8_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i32-to-i16.c new file mode 100644 index 00000000000..7fe8f277476 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i32-to-i16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_4(int16_t, int32_t, INT16_MIN, INT16_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i32-to-i8.c new file mode 100644 index 00000000000..96500562cc3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i32-to-i8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_4(int8_t, int32_t, INT8_MIN, INT8_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i64-to-i16.c new file mode 100644 index 00000000000..b1ed04f0e4e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i64-to-i16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_4(int16_t, int64_t, INT16_MIN, INT16_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i64-to-i32.c new file mode 100644 index 00000000000..94afc448d07 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i64-to-i32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_4(int32_t, int64_t, INT32_MIN, INT32_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i64-to-i8.c new file mode 100644 index 00000000000..483c9e833a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i64-to-i8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_4(int8_t, int64_t, INT8_MIN, INT8_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i16-to-i8.c new file mode 100644 index 00000000000..d07b736f5e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i16-to-i8.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int8_t +#define T2 int16_t + +DEF_VEC_SAT_S_TRUNC_FMT_4_WRAP(T1, T2, INT8_MIN, INT8_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_4_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i32-to-i16.c new file mode 100644 index 00000000000..06afa3fff68 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i32-to-i16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int16_t +#define T2 int32_t + +DEF_VEC_SAT_S_TRUNC_FMT_4_WRAP(T1, T2, INT16_MIN, INT16_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_4_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i32-to-i8.c new file mode 100644 index 00000000000..d07b736f5e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i32-to-i8.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int8_t +#define T2 int16_t + +DEF_VEC_SAT_S_TRUNC_FMT_4_WRAP(T1, T2, INT8_MIN, INT8_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_4_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i64-to-i16.c new file mode 100644 index 00000000000..de26b5cec1b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i64-to-i16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int16_t +#define T2 int64_t + +DEF_VEC_SAT_S_TRUNC_FMT_4_WRAP(T1, T2, INT16_MIN, INT16_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_4_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i64-to-i32.c new file mode 100644 index 00000000000..c1907f7d87a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i64-to-i32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int32_t +#define T2 int64_t + +DEF_VEC_SAT_S_TRUNC_FMT_4_WRAP(T1, T2, INT32_MIN, INT32_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_4_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i64-to-i8.c new file mode 100644 index 00000000000..645d7648ab5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i64-to-i8.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int8_t +#define T2 int64_t + +DEF_VEC_SAT_S_TRUNC_FMT_4_WRAP(T1, T2, INT8_MIN, INT8_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_4_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h index c0524bae2d0..74142ac6adf 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h @@ -698,6 +698,23 @@ vec_sat_s_trunc_##NT##_##WT##_fmt_3 (NT *out, WT *in, unsigned limit) \ #define DEF_VEC_SAT_S_TRUNC_FMT_3_WRAP(NT, WT, NT_MIN, NT_MAX) \ DEF_VEC_SAT_S_TRUNC_FMT_3(NT, WT, NT_MIN, NT_MAX) +#define DEF_VEC_SAT_S_TRUNC_FMT_4(NT, WT, NT_MIN, NT_MAX) \ +void __attribute__((noinline)) \ +vec_sat_s_trunc_##NT##_##WT##_fmt_4 (NT *out, WT *in, unsigned limit) \ +{ \ + unsigned i; \ + for (i = 0; i < limit; i++) \ + { \ + WT x = in[i]; \ + NT trunc = (NT)x; \ + out[i] = (WT)NT_MIN <= x && x < (WT)NT_MAX \ + ? trunc \ + : x < 0 ? NT_MIN : NT_MAX; \ + } \ +} +#define DEF_VEC_SAT_S_TRUNC_FMT_4_WRAP(NT, WT, NT_MIN, NT_MAX) \ + DEF_VEC_SAT_S_TRUNC_FMT_4(NT, WT, NT_MIN, NT_MAX) + #define RUN_VEC_SAT_U_TRUNC_FMT_1(NT, WT, out, in, N) \ vec_sat_u_trunc_##NT##_##WT##_fmt_1 (out, in, N) #define RUN_VEC_SAT_U_TRUNC_FMT_1_WRAP(NT, WT, out, in, N) \ @@ -733,4 +750,9 @@ vec_sat_s_trunc_##NT##_##WT##_fmt_3 (NT *out, WT *in, unsigned limit) \ #define RUN_VEC_SAT_S_TRUNC_FMT_3_WRAP(NT, WT, out, in, N) \ RUN_VEC_SAT_S_TRUNC_FMT_3(NT, WT, out, in, N) +#define RUN_VEC_SAT_S_TRUNC_FMT_4(NT, WT, out, in, N) \ + vec_sat_s_trunc_##NT##_##WT##_fmt_4 (out, in, N) +#define RUN_VEC_SAT_S_TRUNC_FMT_4_WRAP(NT, WT, out, in, N) \ + RUN_VEC_SAT_S_TRUNC_FMT_4(NT, WT, out, in, N) + #endif From patchwork Mon Oct 14 11:10:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1996829 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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14 Oct 2024 04:12:52 -0700 X-CSE-ConnectionGUID: YG3aLOVdQW2sFRFljrf+kw== X-CSE-MsgGUID: L/VhpkoMRPKV8ybG8L9jMQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,202,1725346800"; d="scan'208";a="114998555" Received: from panli.sh.intel.com ([10.239.154.73]) by orviesa001.jf.intel.com with ESMTP; 14 Oct 2024 04:12:49 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: richard.guenther@gmail.com, Tamar.Christina@arm.com, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH 08/11] RISC-V: Add testcases for form 5 of vector signed SAT_TRUNC Date: Mon, 14 Oct 2024 19:10:55 +0800 Message-ID: <20241014111058.1033886-8-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241014111058.1033886-1-pan2.li@intel.com> References: <20241014111058.1033886-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li Form 5: #define DEF_VEC_SAT_S_TRUNC_FMT_5(NT, WT, NT_MIN, NT_MAX) \ void __attribute__((noinline)) \ vec_sat_s_trunc_##NT##_##WT##_fmt_5 (NT *out, WT *in, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \ { \ WT x = in[i]; \ NT trunc = (NT)x; \ out[i] = (WT)NT_MIN > x || x > (WT)NT_MAX \ ? x < 0 ? NT_MIN : NT_MAX \ : trunc; \ } \ } The below test are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper macros. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i16-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i32-to-i16.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i32-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i64-to-i16.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i64-to-i32.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i64-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i16-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i32-to-i16.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i32-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i64-to-i16.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i64-to-i32.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i64-to-i8.c: New test. Signed-off-by: Pan Li --- .../unop/vec_sat_s_trunc-5-i16-to-i8.c | 9 ++++++++ .../unop/vec_sat_s_trunc-5-i32-to-i16.c | 9 ++++++++ .../unop/vec_sat_s_trunc-5-i32-to-i8.c | 9 ++++++++ .../unop/vec_sat_s_trunc-5-i64-to-i16.c | 9 ++++++++ .../unop/vec_sat_s_trunc-5-i64-to-i32.c | 9 ++++++++ .../unop/vec_sat_s_trunc-5-i64-to-i8.c | 9 ++++++++ .../unop/vec_sat_s_trunc-run-5-i16-to-i8.c | 16 ++++++++++++++ .../unop/vec_sat_s_trunc-run-5-i32-to-i16.c | 16 ++++++++++++++ .../unop/vec_sat_s_trunc-run-5-i32-to-i8.c | 16 ++++++++++++++ .../unop/vec_sat_s_trunc-run-5-i64-to-i16.c | 16 ++++++++++++++ .../unop/vec_sat_s_trunc-run-5-i64-to-i32.c | 16 ++++++++++++++ .../unop/vec_sat_s_trunc-run-5-i64-to-i8.c | 16 ++++++++++++++ .../riscv/rvv/autovec/vec_sat_arith.h | 22 +++++++++++++++++++ 13 files changed, 172 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i16-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i32-to-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i32-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i64-to-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i64-to-i32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i64-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i16-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i32-to-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i32-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i64-to-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i64-to-i32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i64-to-i8.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i16-to-i8.c new file mode 100644 index 00000000000..49c076ad277 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i16-to-i8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_5(int8_t, int16_t, INT8_MIN, INT8_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i32-to-i16.c new file mode 100644 index 00000000000..a2a1aa40e01 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i32-to-i16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_5(int16_t, int32_t, INT16_MIN, INT16_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i32-to-i8.c new file mode 100644 index 00000000000..ba09734efb9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i32-to-i8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_5(int8_t, int32_t, INT8_MIN, INT8_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i64-to-i16.c new file mode 100644 index 00000000000..7bc191d0356 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i64-to-i16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_5(int16_t, int64_t, INT16_MIN, INT16_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i64-to-i32.c new file mode 100644 index 00000000000..b896cbea5a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i64-to-i32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_5(int32_t, int64_t, INT32_MIN, INT32_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i64-to-i8.c new file mode 100644 index 00000000000..67477e5351c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i64-to-i8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_5(int8_t, int64_t, INT8_MIN, INT8_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i16-to-i8.c new file mode 100644 index 00000000000..c2b7b7b1289 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i16-to-i8.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int8_t +#define T2 int16_t + +DEF_VEC_SAT_S_TRUNC_FMT_5_WRAP(T1, T2, INT8_MIN, INT8_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_5_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i32-to-i16.c new file mode 100644 index 00000000000..238e0d76c34 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i32-to-i16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int16_t +#define T2 int32_t + +DEF_VEC_SAT_S_TRUNC_FMT_5_WRAP(T1, T2, INT16_MIN, INT16_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_5_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i32-to-i8.c new file mode 100644 index 00000000000..c2b7b7b1289 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i32-to-i8.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int8_t +#define T2 int16_t + +DEF_VEC_SAT_S_TRUNC_FMT_5_WRAP(T1, T2, INT8_MIN, INT8_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_5_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i64-to-i16.c new file mode 100644 index 00000000000..e5ef086c65a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i64-to-i16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int16_t +#define T2 int64_t + +DEF_VEC_SAT_S_TRUNC_FMT_5_WRAP(T1, T2, INT16_MIN, INT16_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_5_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i64-to-i32.c new file mode 100644 index 00000000000..61158efdcc9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i64-to-i32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int32_t +#define T2 int64_t + +DEF_VEC_SAT_S_TRUNC_FMT_5_WRAP(T1, T2, INT32_MIN, INT32_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_5_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i64-to-i8.c new file mode 100644 index 00000000000..b688c1190fc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i64-to-i8.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int8_t +#define T2 int64_t + +DEF_VEC_SAT_S_TRUNC_FMT_5_WRAP(T1, T2, INT8_MIN, INT8_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_5_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h index 74142ac6adf..30996e14a3b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h @@ -715,6 +715,23 @@ vec_sat_s_trunc_##NT##_##WT##_fmt_4 (NT *out, WT *in, unsigned limit) \ #define DEF_VEC_SAT_S_TRUNC_FMT_4_WRAP(NT, WT, NT_MIN, NT_MAX) \ DEF_VEC_SAT_S_TRUNC_FMT_4(NT, WT, NT_MIN, NT_MAX) +#define DEF_VEC_SAT_S_TRUNC_FMT_5(NT, WT, NT_MIN, NT_MAX) \ +void __attribute__((noinline)) \ +vec_sat_s_trunc_##NT##_##WT##_fmt_5 (NT *out, WT *in, unsigned limit) \ +{ \ + unsigned i; \ + for (i = 0; i < limit; i++) \ + { \ + WT x = in[i]; \ + NT trunc = (NT)x; \ + out[i] = (WT)NT_MIN > x || x > (WT)NT_MAX \ + ? x < 0 ? NT_MIN : NT_MAX \ + : trunc; \ + } \ +} +#define DEF_VEC_SAT_S_TRUNC_FMT_5_WRAP(NT, WT, NT_MIN, NT_MAX) \ + DEF_VEC_SAT_S_TRUNC_FMT_5(NT, WT, NT_MIN, NT_MAX) + #define RUN_VEC_SAT_U_TRUNC_FMT_1(NT, WT, out, in, N) \ vec_sat_u_trunc_##NT##_##WT##_fmt_1 (out, in, N) #define RUN_VEC_SAT_U_TRUNC_FMT_1_WRAP(NT, WT, out, in, N) \ @@ -755,4 +772,9 @@ vec_sat_s_trunc_##NT##_##WT##_fmt_4 (NT *out, WT *in, unsigned limit) \ #define RUN_VEC_SAT_S_TRUNC_FMT_4_WRAP(NT, WT, out, in, N) \ RUN_VEC_SAT_S_TRUNC_FMT_4(NT, WT, out, in, N) +#define RUN_VEC_SAT_S_TRUNC_FMT_5(NT, WT, out, in, N) \ + vec_sat_s_trunc_##NT##_##WT##_fmt_5 (out, in, N) +#define RUN_VEC_SAT_S_TRUNC_FMT_5_WRAP(NT, WT, out, in, N) \ + RUN_VEC_SAT_S_TRUNC_FMT_5(NT, WT, out, in, N) + #endif From patchwork Mon Oct 14 11:10:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1996820 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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14 Oct 2024 04:12:54 -0700 X-CSE-ConnectionGUID: ZSqm3syGQmG52vvqakNtNw== X-CSE-MsgGUID: pR98EMXiQLmUFRbs4/DJuA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,202,1725346800"; d="scan'208";a="114998571" Received: from panli.sh.intel.com ([10.239.154.73]) by orviesa001.jf.intel.com with ESMTP; 14 Oct 2024 04:12:51 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: richard.guenther@gmail.com, Tamar.Christina@arm.com, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH 09/11] RISC-V: Add testcases for form 6 of vector signed SAT_TRUNC Date: Mon, 14 Oct 2024 19:10:56 +0800 Message-ID: <20241014111058.1033886-9-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241014111058.1033886-1-pan2.li@intel.com> References: <20241014111058.1033886-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li Form 6: #define DEF_VEC_SAT_S_TRUNC_FMT_6(NT, WT, NT_MIN, NT_MAX) \ void __attribute__((noinline)) \ vec_sat_s_trunc_##NT##_##WT##_fmt_6 (NT *out, WT *in, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \ { \ WT x = in[i]; \ NT trunc = (NT)x; \ out[i] = (WT)NT_MIN >= x || x > (WT)NT_MAX \ ? x < 0 ? NT_MIN : NT_MAX \ j: trunc; \ } \ } The below test are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper macros. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i16-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i32-to-i16.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i32-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i64-to-i16.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i64-to-i32.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i64-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i16-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i32-to-i16.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i32-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i64-to-i16.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i64-to-i32.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i64-to-i8.c: New test. Signed-off-by: Pan Li --- .../unop/vec_sat_s_trunc-6-i16-to-i8.c | 9 ++++++++ .../unop/vec_sat_s_trunc-6-i32-to-i16.c | 9 ++++++++ .../unop/vec_sat_s_trunc-6-i32-to-i8.c | 9 ++++++++ .../unop/vec_sat_s_trunc-6-i64-to-i16.c | 9 ++++++++ .../unop/vec_sat_s_trunc-6-i64-to-i32.c | 9 ++++++++ .../unop/vec_sat_s_trunc-6-i64-to-i8.c | 9 ++++++++ .../unop/vec_sat_s_trunc-run-6-i16-to-i8.c | 16 ++++++++++++++ .../unop/vec_sat_s_trunc-run-6-i32-to-i16.c | 16 ++++++++++++++ .../unop/vec_sat_s_trunc-run-6-i32-to-i8.c | 16 ++++++++++++++ .../unop/vec_sat_s_trunc-run-6-i64-to-i16.c | 16 ++++++++++++++ .../unop/vec_sat_s_trunc-run-6-i64-to-i32.c | 16 ++++++++++++++ .../unop/vec_sat_s_trunc-run-6-i64-to-i8.c | 16 ++++++++++++++ .../riscv/rvv/autovec/vec_sat_arith.h | 22 +++++++++++++++++++ 13 files changed, 172 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i16-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i32-to-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i32-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i64-to-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i64-to-i32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i64-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i16-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i32-to-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i32-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i64-to-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i64-to-i32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i64-to-i8.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i16-to-i8.c new file mode 100644 index 00000000000..c97057355c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i16-to-i8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_6(int8_t, int16_t, INT8_MIN, INT8_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i32-to-i16.c new file mode 100644 index 00000000000..629c07347bb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i32-to-i16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_6(int16_t, int32_t, INT16_MIN, INT16_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i32-to-i8.c new file mode 100644 index 00000000000..c70c8321c06 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i32-to-i8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_6(int8_t, int32_t, INT8_MIN, INT8_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i64-to-i16.c new file mode 100644 index 00000000000..d1967baf901 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i64-to-i16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_6(int16_t, int64_t, INT16_MIN, INT16_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i64-to-i32.c new file mode 100644 index 00000000000..8e2625fbed1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i64-to-i32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_6(int32_t, int64_t, INT32_MIN, INT32_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i64-to-i8.c new file mode 100644 index 00000000000..b75a82e342c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i64-to-i8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_6(int8_t, int64_t, INT8_MIN, INT8_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i16-to-i8.c new file mode 100644 index 00000000000..457abd6ee07 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i16-to-i8.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int8_t +#define T2 int16_t + +DEF_VEC_SAT_S_TRUNC_FMT_6_WRAP(T1, T2, INT8_MIN, INT8_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_6_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i32-to-i16.c new file mode 100644 index 00000000000..694a771689c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i32-to-i16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int16_t +#define T2 int32_t + +DEF_VEC_SAT_S_TRUNC_FMT_6_WRAP(T1, T2, INT16_MIN, INT16_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_6_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i32-to-i8.c new file mode 100644 index 00000000000..457abd6ee07 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i32-to-i8.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int8_t +#define T2 int16_t + +DEF_VEC_SAT_S_TRUNC_FMT_6_WRAP(T1, T2, INT8_MIN, INT8_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_6_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i64-to-i16.c new file mode 100644 index 00000000000..6fb64a3e5ff --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i64-to-i16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int16_t +#define T2 int64_t + +DEF_VEC_SAT_S_TRUNC_FMT_6_WRAP(T1, T2, INT16_MIN, INT16_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_6_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i64-to-i32.c new file mode 100644 index 00000000000..0c8bc7458ae --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i64-to-i32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int32_t +#define T2 int64_t + +DEF_VEC_SAT_S_TRUNC_FMT_6_WRAP(T1, T2, INT32_MIN, INT32_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_6_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i64-to-i8.c new file mode 100644 index 00000000000..3c4513cad75 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i64-to-i8.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int8_t +#define T2 int64_t + +DEF_VEC_SAT_S_TRUNC_FMT_6_WRAP(T1, T2, INT8_MIN, INT8_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_6_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h index 30996e14a3b..1586a99603f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h @@ -732,6 +732,23 @@ vec_sat_s_trunc_##NT##_##WT##_fmt_5 (NT *out, WT *in, unsigned limit) \ #define DEF_VEC_SAT_S_TRUNC_FMT_5_WRAP(NT, WT, NT_MIN, NT_MAX) \ DEF_VEC_SAT_S_TRUNC_FMT_5(NT, WT, NT_MIN, NT_MAX) +#define DEF_VEC_SAT_S_TRUNC_FMT_6(NT, WT, NT_MIN, NT_MAX) \ +void __attribute__((noinline)) \ +vec_sat_s_trunc_##NT##_##WT##_fmt_6 (NT *out, WT *in, unsigned limit) \ +{ \ + unsigned i; \ + for (i = 0; i < limit; i++) \ + { \ + WT x = in[i]; \ + NT trunc = (NT)x; \ + out[i] = (WT)NT_MIN >= x || x > (WT)NT_MAX \ + ? x < 0 ? NT_MIN : NT_MAX \ + : trunc; \ + } \ +} +#define DEF_VEC_SAT_S_TRUNC_FMT_6_WRAP(NT, WT, NT_MIN, NT_MAX) \ + DEF_VEC_SAT_S_TRUNC_FMT_6(NT, WT, NT_MIN, NT_MAX) + #define RUN_VEC_SAT_U_TRUNC_FMT_1(NT, WT, out, in, N) \ vec_sat_u_trunc_##NT##_##WT##_fmt_1 (out, in, N) #define RUN_VEC_SAT_U_TRUNC_FMT_1_WRAP(NT, WT, out, in, N) \ @@ -777,4 +794,9 @@ vec_sat_s_trunc_##NT##_##WT##_fmt_5 (NT *out, WT *in, unsigned limit) \ #define RUN_VEC_SAT_S_TRUNC_FMT_5_WRAP(NT, WT, out, in, N) \ RUN_VEC_SAT_S_TRUNC_FMT_5(NT, WT, out, in, N) +#define RUN_VEC_SAT_S_TRUNC_FMT_6(NT, WT, out, in, N) \ + vec_sat_s_trunc_##NT##_##WT##_fmt_6 (out, in, N) +#define RUN_VEC_SAT_S_TRUNC_FMT_6_WRAP(NT, WT, out, in, N) \ + RUN_VEC_SAT_S_TRUNC_FMT_6(NT, WT, out, in, N) + #endif From patchwork Mon Oct 14 11:10:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1996830 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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14 Oct 2024 04:12:57 -0700 X-CSE-ConnectionGUID: QCw4Co6RRkimAcw5hR4VfA== X-CSE-MsgGUID: 1SwWd+SKTVO25MhcEEou/Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,202,1725346800"; d="scan'208";a="114998591" Received: from panli.sh.intel.com ([10.239.154.73]) by orviesa001.jf.intel.com with ESMTP; 14 Oct 2024 04:12:54 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: richard.guenther@gmail.com, Tamar.Christina@arm.com, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH 10/11] RISC-V: Add testcases for form 7 of vector signed SAT_TRUNC Date: Mon, 14 Oct 2024 19:10:57 +0800 Message-ID: <20241014111058.1033886-10-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241014111058.1033886-1-pan2.li@intel.com> References: <20241014111058.1033886-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li Form 7: #define DEF_VEC_SAT_S_TRUNC_FMT_7(NT, WT, NT_MIN, NT_MAX) \ void __attribute__((noinline)) \ vec_sat_s_trunc_##NT##_##WT##_fmt_7 (NT *out, WT *in, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \ { \ WT x = in[i]; \ NT trunc = (NT)x; \ out[i] = (WT)NT_MIN > x || x >= (WT)NT_MAX \ ? x < 0 ? NT_MIN : NT_MAX \ : trunc; \ } \ } The below test are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper macros. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i16-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i32-to-i16.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i32-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i64-to-i16.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i64-to-i32.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i64-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i16-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i32-to-i16.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i32-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i64-to-i16.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i64-to-i32.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i64-to-i8.c: New test. Signed-off-by: Pan Li --- .../unop/vec_sat_s_trunc-7-i16-to-i8.c | 9 ++++++++ .../unop/vec_sat_s_trunc-7-i32-to-i16.c | 9 ++++++++ .../unop/vec_sat_s_trunc-7-i32-to-i8.c | 9 ++++++++ .../unop/vec_sat_s_trunc-7-i64-to-i16.c | 9 ++++++++ .../unop/vec_sat_s_trunc-7-i64-to-i32.c | 9 ++++++++ .../unop/vec_sat_s_trunc-7-i64-to-i8.c | 9 ++++++++ .../unop/vec_sat_s_trunc-run-7-i16-to-i8.c | 16 ++++++++++++++ .../unop/vec_sat_s_trunc-run-7-i32-to-i16.c | 16 ++++++++++++++ .../unop/vec_sat_s_trunc-run-7-i32-to-i8.c | 16 ++++++++++++++ .../unop/vec_sat_s_trunc-run-7-i64-to-i16.c | 16 ++++++++++++++ .../unop/vec_sat_s_trunc-run-7-i64-to-i32.c | 16 ++++++++++++++ .../unop/vec_sat_s_trunc-run-7-i64-to-i8.c | 16 ++++++++++++++ .../riscv/rvv/autovec/vec_sat_arith.h | 22 +++++++++++++++++++ 13 files changed, 172 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i16-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i32-to-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i32-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i64-to-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i64-to-i32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i64-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i16-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i32-to-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i32-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i64-to-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i64-to-i32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i64-to-i8.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i16-to-i8.c new file mode 100644 index 00000000000..a6eb2d5b0b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i16-to-i8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_7(int8_t, int16_t, INT8_MIN, INT8_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i32-to-i16.c new file mode 100644 index 00000000000..fd01c74d2df --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i32-to-i16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_7(int16_t, int32_t, INT16_MIN, INT16_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i32-to-i8.c new file mode 100644 index 00000000000..6af61538d59 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i32-to-i8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_7(int8_t, int32_t, INT8_MIN, INT8_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i64-to-i16.c new file mode 100644 index 00000000000..aee896e3df3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i64-to-i16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_7(int16_t, int64_t, INT16_MIN, INT16_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i64-to-i32.c new file mode 100644 index 00000000000..ce3ca80e416 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i64-to-i32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_7(int32_t, int64_t, INT32_MIN, INT32_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i64-to-i8.c new file mode 100644 index 00000000000..b3cb744dd97 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i64-to-i8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_7(int8_t, int64_t, INT8_MIN, INT8_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i16-to-i8.c new file mode 100644 index 00000000000..53c046436ea --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i16-to-i8.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int8_t +#define T2 int16_t + +DEF_VEC_SAT_S_TRUNC_FMT_7_WRAP(T1, T2, INT8_MIN, INT8_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_7_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i32-to-i16.c new file mode 100644 index 00000000000..132de83458d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i32-to-i16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int16_t +#define T2 int32_t + +DEF_VEC_SAT_S_TRUNC_FMT_7_WRAP(T1, T2, INT16_MIN, INT16_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_7_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i32-to-i8.c new file mode 100644 index 00000000000..53c046436ea --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i32-to-i8.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int8_t +#define T2 int16_t + +DEF_VEC_SAT_S_TRUNC_FMT_7_WRAP(T1, T2, INT8_MIN, INT8_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_7_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i64-to-i16.c new file mode 100644 index 00000000000..3747149cdb7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i64-to-i16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int16_t +#define T2 int64_t + +DEF_VEC_SAT_S_TRUNC_FMT_7_WRAP(T1, T2, INT16_MIN, INT16_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_7_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i64-to-i32.c new file mode 100644 index 00000000000..8a85d40dc08 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i64-to-i32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int32_t +#define T2 int64_t + +DEF_VEC_SAT_S_TRUNC_FMT_7_WRAP(T1, T2, INT32_MIN, INT32_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_7_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i64-to-i8.c new file mode 100644 index 00000000000..11f758ffda3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i64-to-i8.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int8_t +#define T2 int64_t + +DEF_VEC_SAT_S_TRUNC_FMT_7_WRAP(T1, T2, INT8_MIN, INT8_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_7_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h index 1586a99603f..ec499812e91 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h @@ -749,6 +749,23 @@ vec_sat_s_trunc_##NT##_##WT##_fmt_6 (NT *out, WT *in, unsigned limit) \ #define DEF_VEC_SAT_S_TRUNC_FMT_6_WRAP(NT, WT, NT_MIN, NT_MAX) \ DEF_VEC_SAT_S_TRUNC_FMT_6(NT, WT, NT_MIN, NT_MAX) +#define DEF_VEC_SAT_S_TRUNC_FMT_7(NT, WT, NT_MIN, NT_MAX) \ +void __attribute__((noinline)) \ +vec_sat_s_trunc_##NT##_##WT##_fmt_7 (NT *out, WT *in, unsigned limit) \ +{ \ + unsigned i; \ + for (i = 0; i < limit; i++) \ + { \ + WT x = in[i]; \ + NT trunc = (NT)x; \ + out[i] = (WT)NT_MIN > x || x >= (WT)NT_MAX \ + ? x < 0 ? NT_MIN : NT_MAX \ + : trunc; \ + } \ +} +#define DEF_VEC_SAT_S_TRUNC_FMT_7_WRAP(NT, WT, NT_MIN, NT_MAX) \ + DEF_VEC_SAT_S_TRUNC_FMT_7(NT, WT, NT_MIN, NT_MAX) + #define RUN_VEC_SAT_U_TRUNC_FMT_1(NT, WT, out, in, N) \ vec_sat_u_trunc_##NT##_##WT##_fmt_1 (out, in, N) #define RUN_VEC_SAT_U_TRUNC_FMT_1_WRAP(NT, WT, out, in, N) \ @@ -799,4 +816,9 @@ vec_sat_s_trunc_##NT##_##WT##_fmt_6 (NT *out, WT *in, unsigned limit) \ #define RUN_VEC_SAT_S_TRUNC_FMT_6_WRAP(NT, WT, out, in, N) \ RUN_VEC_SAT_S_TRUNC_FMT_6(NT, WT, out, in, N) +#define RUN_VEC_SAT_S_TRUNC_FMT_7(NT, WT, out, in, N) \ + vec_sat_s_trunc_##NT##_##WT##_fmt_7 (out, in, N) +#define RUN_VEC_SAT_S_TRUNC_FMT_7_WRAP(NT, WT, out, in, N) \ + RUN_VEC_SAT_S_TRUNC_FMT_7(NT, WT, out, in, N) + #endif From patchwork Mon Oct 14 11:10:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1996834 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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14 Oct 2024 04:12:59 -0700 X-CSE-ConnectionGUID: Wwl+xtXWRI6lFpa2sGsk3w== X-CSE-MsgGUID: HMJh8h/FSGC2uwG5NxTYJw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,202,1725346800"; d="scan'208";a="114998609" Received: from panli.sh.intel.com ([10.239.154.73]) by orviesa001.jf.intel.com with ESMTP; 14 Oct 2024 04:12:56 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: richard.guenther@gmail.com, Tamar.Christina@arm.com, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH 11/11] RISC-V: Add testcases for form 8 of vector signed SAT_TRUNC Date: Mon, 14 Oct 2024 19:10:58 +0800 Message-ID: <20241014111058.1033886-11-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241014111058.1033886-1-pan2.li@intel.com> References: <20241014111058.1033886-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li Form 8: #define DEF_VEC_SAT_S_TRUNC_FMT_8(NT, WT, NT_MIN, NT_MAX) \ void __attribute__((noinline)) \ vec_sat_s_trunc_##NT##_##WT##_fmt_8 (NT *out, WT *in, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \ { \ WT x = in[i]; \ NT trunc = (NT)x; \ out[i] = (WT)NT_MIN >= x || x >= (WT)NT_MAX \ ? x < 0 ? NT_MIN : NT_MAX \ : trunc; \ } \ } The below test are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper macros. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i16-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i32-to-i16.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i32-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i64-to-i16.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i64-to-i32.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i64-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i16-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i32-to-i16.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i32-to-i8.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i64-to-i16.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i64-to-i32.c: New test. * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i64-to-i8.c: New test. Signed-off-by: Pan Li --- .../unop/vec_sat_s_trunc-8-i16-to-i8.c | 9 ++++++++ .../unop/vec_sat_s_trunc-8-i32-to-i16.c | 9 ++++++++ .../unop/vec_sat_s_trunc-8-i32-to-i8.c | 9 ++++++++ .../unop/vec_sat_s_trunc-8-i64-to-i16.c | 9 ++++++++ .../unop/vec_sat_s_trunc-8-i64-to-i32.c | 9 ++++++++ .../unop/vec_sat_s_trunc-8-i64-to-i8.c | 9 ++++++++ .../unop/vec_sat_s_trunc-run-8-i16-to-i8.c | 16 ++++++++++++++ .../unop/vec_sat_s_trunc-run-8-i32-to-i16.c | 16 ++++++++++++++ .../unop/vec_sat_s_trunc-run-8-i32-to-i8.c | 16 ++++++++++++++ .../unop/vec_sat_s_trunc-run-8-i64-to-i16.c | 16 ++++++++++++++ .../unop/vec_sat_s_trunc-run-8-i64-to-i32.c | 16 ++++++++++++++ .../unop/vec_sat_s_trunc-run-8-i64-to-i8.c | 16 ++++++++++++++ .../riscv/rvv/autovec/vec_sat_arith.h | 22 +++++++++++++++++++ 13 files changed, 172 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i16-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i32-to-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i32-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i64-to-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i64-to-i32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i64-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i16-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i32-to-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i32-to-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i64-to-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i64-to-i32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i64-to-i8.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i16-to-i8.c new file mode 100644 index 00000000000..64f140f764e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i16-to-i8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_8(int8_t, int16_t, INT8_MIN, INT8_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i32-to-i16.c new file mode 100644 index 00000000000..9bd95a52a01 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i32-to-i16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_8(int16_t, int32_t, INT16_MIN, INT16_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i32-to-i8.c new file mode 100644 index 00000000000..0cb9d7796ef --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i32-to-i8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_8(int8_t, int32_t, INT8_MIN, INT8_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i64-to-i16.c new file mode 100644 index 00000000000..8d766e33e88 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i64-to-i16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_8(int16_t, int64_t, INT16_MIN, INT16_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i64-to-i32.c new file mode 100644 index 00000000000..98ede144020 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i64-to-i32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_8(int32_t, int64_t, INT32_MIN, INT32_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i64-to-i8.c new file mode 100644 index 00000000000..2d9870f6c2b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i64-to-i8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ + +#include "../vec_sat_arith.h" + +DEF_VEC_SAT_S_TRUNC_FMT_8(int8_t, int64_t, INT8_MIN, INT8_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i16-to-i8.c new file mode 100644 index 00000000000..4964599d545 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i16-to-i8.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int8_t +#define T2 int16_t + +DEF_VEC_SAT_S_TRUNC_FMT_8_WRAP(T1, T2, INT8_MIN, INT8_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_8_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i32-to-i16.c new file mode 100644 index 00000000000..6c424b2bfa0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i32-to-i16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int16_t +#define T2 int32_t + +DEF_VEC_SAT_S_TRUNC_FMT_8_WRAP(T1, T2, INT16_MIN, INT16_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_8_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i32-to-i8.c new file mode 100644 index 00000000000..4964599d545 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i32-to-i8.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int8_t +#define T2 int16_t + +DEF_VEC_SAT_S_TRUNC_FMT_8_WRAP(T1, T2, INT8_MIN, INT8_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_8_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i64-to-i16.c new file mode 100644 index 00000000000..e7b6cdb9c94 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i64-to-i16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int16_t +#define T2 int64_t + +DEF_VEC_SAT_S_TRUNC_FMT_8_WRAP(T1, T2, INT16_MIN, INT16_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_8_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i64-to-i32.c new file mode 100644 index 00000000000..02456e900f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i64-to-i32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int32_t +#define T2 int64_t + +DEF_VEC_SAT_S_TRUNC_FMT_8_WRAP(T1, T2, INT32_MIN, INT32_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_8_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i64-to-i8.c new file mode 100644 index 00000000000..23cc7f0248e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i64-to-i8.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 int8_t +#define T2 int64_t + +DEF_VEC_SAT_S_TRUNC_FMT_8_WRAP(T1, T2, INT8_MIN, INT8_MAX) + +#define T TEST_UNARY_STRUCT_DECL(T1, T2) +#define DATA TEST_UNARY_DATA_WRAP(T1, T2) +#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_8_WRAP(T1, T2, out, in, N) + +#include "vec_sat_unary_vv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h index ec499812e91..f9376c26102 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h @@ -766,6 +766,23 @@ vec_sat_s_trunc_##NT##_##WT##_fmt_7 (NT *out, WT *in, unsigned limit) \ #define DEF_VEC_SAT_S_TRUNC_FMT_7_WRAP(NT, WT, NT_MIN, NT_MAX) \ DEF_VEC_SAT_S_TRUNC_FMT_7(NT, WT, NT_MIN, NT_MAX) +#define DEF_VEC_SAT_S_TRUNC_FMT_8(NT, WT, NT_MIN, NT_MAX) \ +void __attribute__((noinline)) \ +vec_sat_s_trunc_##NT##_##WT##_fmt_8 (NT *out, WT *in, unsigned limit) \ +{ \ + unsigned i; \ + for (i = 0; i < limit; i++) \ + { \ + WT x = in[i]; \ + NT trunc = (NT)x; \ + out[i] = (WT)NT_MIN >= x || x >= (WT)NT_MAX \ + ? x < 0 ? NT_MIN : NT_MAX \ + : trunc; \ + } \ +} +#define DEF_VEC_SAT_S_TRUNC_FMT_8_WRAP(NT, WT, NT_MIN, NT_MAX) \ + DEF_VEC_SAT_S_TRUNC_FMT_8(NT, WT, NT_MIN, NT_MAX) + #define RUN_VEC_SAT_U_TRUNC_FMT_1(NT, WT, out, in, N) \ vec_sat_u_trunc_##NT##_##WT##_fmt_1 (out, in, N) #define RUN_VEC_SAT_U_TRUNC_FMT_1_WRAP(NT, WT, out, in, N) \ @@ -821,4 +838,9 @@ vec_sat_s_trunc_##NT##_##WT##_fmt_7 (NT *out, WT *in, unsigned limit) \ #define RUN_VEC_SAT_S_TRUNC_FMT_7_WRAP(NT, WT, out, in, N) \ RUN_VEC_SAT_S_TRUNC_FMT_7(NT, WT, out, in, N) +#define RUN_VEC_SAT_S_TRUNC_FMT_8(NT, WT, out, in, N) \ + vec_sat_s_trunc_##NT##_##WT##_fmt_8 (out, in, N) +#define RUN_VEC_SAT_S_TRUNC_FMT_8_WRAP(NT, WT, out, in, N) \ + RUN_VEC_SAT_S_TRUNC_FMT_8(NT, WT, out, in, N) + #endif