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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230040)(35042699022)(376014)(36860700013)(1800799024)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Oct 2024 10:54:30.0655 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a7fdac65-435c-45c7-d99e-08dcec3e9459 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DU2PEPF0001E9C3.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS4PR08MB7687 X-Spam-Status: No, score=-10.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FORGED_SPF_HELO, GIT_PATCH_0, KAM_LOTSOFHASH, KAM_SHORT, MAIL_SCAM, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Hi All, The patch series will adjust how zeros are created. In principal it doesn't matter the exact lane size a zero gets created on but this makes the tests a bit fragile. This preparation patch will update the testsuite to accept multiple variants of ways to create vector zeros to accept both the current syntax and the one being transitioned to in the series. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master? Thanks, Tamar gcc/testsuite/ChangeLog: * gcc.target/aarch64/ldp_stp_18.c: Update zero regexpr. * gcc.target/aarch64/memset-corner-cases.c: Likewise. * gcc.target/aarch64/sme/acle-asm/revd_bf16.c: Likewise. * gcc.target/aarch64/sme/acle-asm/revd_f16.c: Likewise. * gcc.target/aarch64/sme/acle-asm/revd_f32.c: Likewise. * gcc.target/aarch64/sme/acle-asm/revd_f64.c: Likewise. * gcc.target/aarch64/sme/acle-asm/revd_s16.c: Likewise. * gcc.target/aarch64/sme/acle-asm/revd_s32.c: Likewise. * gcc.target/aarch64/sme/acle-asm/revd_s64.c: Likewise. * gcc.target/aarch64/sme/acle-asm/revd_s8.c: Likewise. * gcc.target/aarch64/sme/acle-asm/revd_u16.c: Likewise. * gcc.target/aarch64/sme/acle-asm/revd_u32.c: Likewise. * gcc.target/aarch64/sme/acle-asm/revd_u64.c: Likewise. * gcc.target/aarch64/sme/acle-asm/revd_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/acge_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/acge_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/acge_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/acgt_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/acgt_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/acgt_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/acle_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/acle_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/acle_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/aclt_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/aclt_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/aclt_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/bic_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/bic_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/cmpuo_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/cmpuo_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/cmpuo_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/dup_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/dup_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/dup_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/dup_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/dup_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/dup_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/dup_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/dup_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/dup_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/dup_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/dup_u8.c: Likewise. * gcc.target/aarch64/sve/const_fold_div_1.c: Likewise. * gcc.target/aarch64/sve/const_fold_mul_1.c: Likewise. * gcc.target/aarch64/sve/dup_imm_1.c: Likewise. * gcc.target/aarch64/sve/fdup_1.c: Likewise. * gcc.target/aarch64/sve/fold_div_zero.c: Likewise. * gcc.target/aarch64/sve/fold_mul_zero.c: Likewise. * gcc.target/aarch64/sve/pcs/args_2.c: Likewise. * gcc.target/aarch64/sve/pcs/args_3.c: Likewise. * gcc.target/aarch64/sve/pcs/args_4.c: Likewise. * gcc.target/aarch64/vect-fmovd-zero.c: Likewise. --- -- diff --git a/gcc/testsuite/gcc.target/aarch64/ldp_stp_18.c b/gcc/testsuite/gcc.target/aarch64/ldp_stp_18.c index eaa855c3859a736012871584b0906bf93bc3d36c..ea9fffc220827f69559259ea04d66e986e5fcd7b 100644 --- a/gcc/testsuite/gcc.target/aarch64/ldp_stp_18.c +++ b/gcc/testsuite/gcc.target/aarch64/ldp_stp_18.c @@ -15,7 +15,7 @@ CONST_FN (4, double, 0); /* ** const_8_double_0: -** movi v([0-9]+)\.2d, .* +** movi v([0-9]+)\.\d+[bhsd], .* ** stp q\1, q\1, \[x0\] ** stp q\1, q\1, \[x0, #?32\] ** ret diff --git a/gcc/testsuite/gcc.target/aarch64/memset-corner-cases.c b/gcc/testsuite/gcc.target/aarch64/memset-corner-cases.c index d4c752711f8dd7d5b297d33dd96f39d09048c5aa..be30428afda323a8a57f393447d077e3cb9ecef2 100644 --- a/gcc/testsuite/gcc.target/aarch64/memset-corner-cases.c +++ b/gcc/testsuite/gcc.target/aarch64/memset-corner-cases.c @@ -29,7 +29,7 @@ set0byte (int64_t *src) /* 35bytes would become 4 scalar instructions. So favour NEON. **set0neon: -** movi v([0-9]+).4s, 0 +** movi v([0-9]+).\d+[bhsd], 0 ** stp q\1, q\1, \[x0\] ** str wzr, \[x0, 31\] ** ret diff --git a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_bf16.c b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_bf16.c index 6507c5a9c15477de473e077d3a33a866f899fba5..1a879924a13c4e9ece800a0d24b95cb14c596368 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_bf16.c +++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_bf16.c @@ -48,7 +48,7 @@ TEST_UNIFORM_Z (revd_bf16_z_tied1, svbfloat16_t, /* ** revd_bf16_z_untied: -** mov z0\.[bhsd], #0 +** mov (d0|z0.[bhsd]), #0 ** revd z0\.q, p0/m, z1\.q ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_f16.c b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_f16.c index 1a2f893d686139b0b396c576ebfc615c42cbf388..d147976e4919e978b69378d38e4f3d7fa0cdd8f6 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_f16.c +++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_f16.c @@ -48,7 +48,7 @@ TEST_UNIFORM_Z (revd_f16_z_tied1, svfloat16_t, /* ** revd_f16_z_untied: -** mov z0\.[bhsd], #0 +** mov (d0|z0.[bhsd]), #0 ** revd z0\.q, p0/m, z1\.q ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_f32.c b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_f32.c index 81c77d52460c5734779deb9e1cfe6689cb259600..80f32b1d71c713ab1678cf92f41f156ae7365dda 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_f32.c +++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_f32.c @@ -48,7 +48,7 @@ TEST_UNIFORM_Z (revd_f32_z_tied1, svfloat32_t, /* ** revd_f32_z_untied: -** mov z0\.[bhsd], #0 +** mov (d0|z0.[bhsd]), #0 ** revd z0\.q, p0/m, z1\.q ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_f64.c b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_f64.c index fce6d6514c73a708f56a5f42d77daa9915631e4c..6bccc00906c5bf395b2668b604682ab6fd30e60b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_f64.c +++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_f64.c @@ -48,7 +48,7 @@ TEST_UNIFORM_Z (revd_f64_z_tied1, svfloat64_t, /* ** revd_f64_z_untied: -** mov z0\.[bhsd], #0 +** mov (d0|z0.[bhsd]), #0 ** revd z0\.q, p0/m, z1\.q ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_s16.c b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_s16.c index a2eba6a609fb23da1bdf7f78cfbcd7d4379bfac3..e7c7d1dd3860b0693fb6ddc2ebc453dd6c84cff1 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_s16.c @@ -48,7 +48,7 @@ TEST_UNIFORM_Z (revd_s16_z_tied1, svint16_t, /* ** revd_s16_z_untied: -** mov z0\.[bhsd], #0 +** mov (d0|z0.b), #0 ** revd z0\.q, p0/m, z1\.q ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_s32.c b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_s32.c index cbc0dc0a0b669dbb0bfdf860fd22cb291dc89540..dc41a3c92eb44caead3ea6971eb87e4409b7425b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_s32.c +++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_s32.c @@ -48,7 +48,7 @@ TEST_UNIFORM_Z (revd_s32_z_tied1, svint32_t, /* ** revd_s32_z_untied: -** mov z0\.[bhsd], #0 +** mov (d0|z0.b), #0 ** revd z0\.q, p0/m, z1\.q ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_s64.c b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_s64.c index aa963d388e005d1df80524343a9ef8895f84f017..859ebea85f3946efe79c1ac38752e7ca20cb9f89 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_s64.c +++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_s64.c @@ -48,7 +48,7 @@ TEST_UNIFORM_Z (revd_s64_z_tied1, svint64_t, /* ** revd_s64_z_untied: -** mov z0\.[bhsd], #0 +** mov (d0|z0.b), #0 ** revd z0\.q, p0/m, z1\.q ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_s8.c b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_s8.c index 4291b7197c6491fd6ebe475e4ce83a20105f5622..0b5e7bb296f71d014a2115dc32459266d47de94e 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_s8.c @@ -48,7 +48,7 @@ TEST_UNIFORM_Z (revd_s8_z_tied1, svint8_t, /* ** revd_s8_z_untied: -** mov z0\.[bhsd], #0 +** mov (d0|z0.b), #0 ** revd z0\.q, p0/m, z1\.q ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_u16.c b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_u16.c index eaed0d13259e9e2641de9c99a704d22bd3a77f36..9b1e9bdb3dd51a3e214ef1df811ab3641b4f66ad 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_u16.c @@ -48,7 +48,7 @@ TEST_UNIFORM_Z (revd_u16_z_tied1, svuint16_t, /* ** revd_u16_z_untied: -** mov z0\.[bhsd], #0 +** mov (d0|z0.b), #0 ** revd z0\.q, p0/m, z1\.q ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_u32.c b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_u32.c index 3b76c7000efb99924bf2a50d7d6d43d94342cf19..f9a3cd2e1504bb872abeb9e277982a90f45932d8 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_u32.c +++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_u32.c @@ -48,7 +48,7 @@ TEST_UNIFORM_Z (revd_u32_z_tied1, svuint32_t, /* ** revd_u32_z_untied: -** mov z0\.[bhsd], #0 +** mov (d0|z0.b), #0 ** revd z0\.q, p0/m, z1\.q ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_u64.c b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_u64.c index 4589c4635e7b91536bd2c86f0b5af05a3d28049a..ddf4170e45afd78208a2d4738d5d4140d9276c86 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_u64.c +++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_u64.c @@ -48,7 +48,7 @@ TEST_UNIFORM_Z (revd_u64_z_tied1, svuint64_t, /* ** revd_u64_z_untied: -** mov z0\.[bhsd], #0 +** mov (d0|z0.b), #0 ** revd z0\.q, p0/m, z1\.q ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_u8.c b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_u8.c index ac5d749818eeaeda173536b30e9262e3c84a62dd..2c831b36f79bb340aaef20200388b7a228840c6f 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/revd_u8.c @@ -48,7 +48,7 @@ TEST_UNIFORM_Z (revd_u8_z_tied1, svuint8_t, /* ** revd_u8_z_untied: -** mov z0\.[bhsd], #0 +** mov (d0|z0.b), #0 ** revd z0\.q, p0/m, z1\.q ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acge_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acge_f16.c index acef17309b72207fe9196755d537faa1c60b7cfc..f7aff8acc970c5e0f88666fcdf3d1237ebcb5712 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acge_f16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acge_f16.c @@ -44,9 +44,9 @@ TEST_COMPARE_ZD (acge_h4_f16, svfloat16_t, float16_t, /* ** acge_0_f16: -** mov (z[0-9]+\.h), #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ( -** facge p0\.h, p1/z, z0\.h, \1 +** facge p0\.h, p1/z, z0\.h, z\1\.h ** | ** facle p0\.h, p1/z, \1, z0\.h ** ) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acge_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acge_f32.c index c3d195ab89fd94bad971bd5bf2209a8b94a9f8bc..8ca6ea29c3b0a09a7bbaef96ceffc0baa60d399d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acge_f32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acge_f32.c @@ -44,9 +44,9 @@ TEST_COMPARE_ZD (acge_s4_f32, svfloat32_t, float32_t, /* ** acge_0_f32: -** mov (z[0-9]+\.s), #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ( -** facge p0\.s, p1/z, z0\.s, \1 +** facge p0\.s, p1/z, z0\.s, z\1\.s ** | ** facle p0\.s, p1/z, \1, z0\.s ** ) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acge_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acge_f64.c index 207ce93a236a3eea22b8e99038791d66ac7244b6..aa537736c9e8d1abe36fc4721a9ddb7590b26f91 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acge_f64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acge_f64.c @@ -44,9 +44,9 @@ TEST_COMPARE_ZD (acge_d4_f64, svfloat64_t, float64_t, /* ** acge_0_f64: -** mov (z[0-9]+\.d), #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ( -** facge p0\.d, p1/z, z0\.d, \1 +** facge p0\.d, p1/z, z0\.d, z\1\.d ** | ** facle p0\.d, p1/z, \1, z0\.d ** ) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acgt_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acgt_f16.c index 53c63351cf1ababfd1e6b49cfff5fbd72afc8f01..a66a24a3b2742490be9369b1e426286d3b03e988 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acgt_f16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acgt_f16.c @@ -44,9 +44,9 @@ TEST_COMPARE_ZD (acgt_h4_f16, svfloat16_t, float16_t, /* ** acgt_0_f16: -** mov (z[0-9]+\.h), #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ( -** facgt p0\.h, p1/z, z0\.h, \1 +** facgt p0\.h, p1/z, z0\.h, z\1\.h ** | ** faclt p0\.h, p1/z, \1, z0\.h ** ) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acgt_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acgt_f32.c index d71c84ea611dd4532847d606c9b148bcd680218b..09f6adeade68306d1b5012feb08e963bfe3023eb 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acgt_f32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acgt_f32.c @@ -44,9 +44,9 @@ TEST_COMPARE_ZD (acgt_s4_f32, svfloat32_t, float32_t, /* ** acgt_0_f32: -** mov (z[0-9]+\.s), #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ( -** facgt p0\.s, p1/z, z0\.s, \1 +** facgt p0\.s, p1/z, z0\.s, z\1\.s ** | ** faclt p0\.s, p1/z, \1, z0\.s ** ) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acgt_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acgt_f64.c index 15d549e1836e7388752389b907ffa74923c1c7e4..4dc232dd15d9671f5a16d433b40a8b38144fee8f 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acgt_f64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acgt_f64.c @@ -44,9 +44,9 @@ TEST_COMPARE_ZD (acgt_d4_f64, svfloat64_t, float64_t, /* ** acgt_0_f64: -** mov (z[0-9]+\.d), #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ( -** facgt p0\.d, p1/z, z0\.d, \1 +** facgt p0\.d, p1/z, z0\.d, z\1\.d ** | ** faclt p0\.d, p1/z, \1, z0\.d ** ) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acle_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acle_f16.c index ed6721d57194597c417800709fb9faa06995057a..18ff2156c1612ccd772a50e4aa07541e63dda969 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acle_f16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acle_f16.c @@ -44,11 +44,11 @@ TEST_COMPARE_ZD (acle_h4_f16, svfloat16_t, float16_t, /* ** acle_0_f16: -** mov (z[0-9]+\.h), #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ( ** facge p0\.h, p1/z, \1, z0\.h ** | -** facle p0\.h, p1/z, z0\.h, \1 +** facle p0\.h, p1/z, z0\.h, z\1\.h ** ) ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acle_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acle_f32.c index 7fc9da701d34586b77f3c1f7ac42d45172337655..4c54298fec60cc06cdfbf6712188ae4c7d627164 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acle_f32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acle_f32.c @@ -44,11 +44,11 @@ TEST_COMPARE_ZD (acle_s4_f32, svfloat32_t, float32_t, /* ** acle_0_f32: -** mov (z[0-9]+\.s), #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ( ** facge p0\.s, p1/z, \1, z0\.s ** | -** facle p0\.s, p1/z, z0\.s, \1 +** facle p0\.s, p1/z, z0\.s, z\1\.s ** ) ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acle_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acle_f64.c index ecbb8e5007c365da3f45bd76ef68775cf8e4ea45..485413ab109fad25a1971b444ac64bdd410f8c07 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acle_f64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acle_f64.c @@ -44,11 +44,11 @@ TEST_COMPARE_ZD (acle_d4_f64, svfloat64_t, float64_t, /* ** acle_0_f64: -** mov (z[0-9]+\.d), #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ( ** facge p0\.d, p1/z, \1, z0\.d ** | -** facle p0\.d, p1/z, z0\.d, \1 +** facle p0\.d, p1/z, z0\.d, z\1\.d ** ) ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/aclt_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/aclt_f16.c index e5f5040c7d1b7a35c77b511669d4d53696f2d0eb..ec9fa18a05670298c82d8f85980149c82e8e0a48 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/aclt_f16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/aclt_f16.c @@ -44,11 +44,11 @@ TEST_COMPARE_ZD (aclt_h4_f16, svfloat16_t, float16_t, /* ** aclt_0_f16: -** mov (z[0-9]+\.h), #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ( ** facgt p0\.h, p1/z, \1, z0\.h ** | -** faclt p0\.h, p1/z, z0\.h, \1 +** faclt p0\.h, p1/z, z0\.h, z\1\.h ** ) ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/aclt_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/aclt_f32.c index f40826445f8d50e23c5579b977016332b3797e7d..6c884f19d5e93c717337202bd17ab1aa223915c9 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/aclt_f32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/aclt_f32.c @@ -44,11 +44,11 @@ TEST_COMPARE_ZD (aclt_s4_f32, svfloat32_t, float32_t, /* ** aclt_0_f32: -** mov (z[0-9]+\.s), #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ( ** facgt p0\.s, p1/z, \1, z0\.s ** | -** faclt p0\.s, p1/z, z0\.s, \1 +** faclt p0\.s, p1/z, z0\.s, z\1\.s ** ) ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/aclt_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/aclt_f64.c index 0170b330700167830f1a2cfa74fc2419f8d08748..10493fb1c06e6882128e86379d594eb31c027825 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/aclt_f64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/aclt_f64.c @@ -44,11 +44,11 @@ TEST_COMPARE_ZD (aclt_d4_f64, svfloat64_t, float64_t, /* ** aclt_0_f64: -** mov (z[0-9]+\.d), #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ( ** facgt p0\.d, p1/z, \1, z0\.d ** | -** faclt p0\.d, p1/z, z0\.d, \1 +** faclt p0\.d, p1/z, z0\.d, z\1\.d ** ) ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_s8.c index d1ffefa77ee08c4074abbf01ef61ef38fd03d8cc..519e575ee09e502afb01071a6d9dcbaa6029e27e 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_s8.c @@ -250,7 +250,7 @@ TEST_UNIFORM_Z (bic_128_s8_x, svint8_t, /* ** bic_255_s8_x: -** mov z0\.b, #0 +** mov(?:i\td0|\tz0.b), #0 ** ret */ TEST_UNIFORM_Z (bic_255_s8_x, svint8_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_u8.c index b7528ceac336968db9436bbdd34d4b0dce664651..e424fcebd26ddd1367398d62e6723ac993d46c40 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_u8.c @@ -250,7 +250,7 @@ TEST_UNIFORM_Z (bic_128_u8_x, svuint8_t, /* ** bic_255_u8_x: -** mov z0\.b, #0 +** mov(?:i\td0|\tz0.b), #0 ** ret */ TEST_UNIFORM_Z (bic_255_u8_x, svuint8_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpuo_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpuo_f16.c index 8f702cddef8073d3dbd63b46a54d18fa3c667f51..99d8dcd047203ed150766d218914077aa7efe266 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpuo_f16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpuo_f16.c @@ -32,8 +32,8 @@ TEST_COMPARE_ZD (cmpuo_h4_f16, svfloat16_t, float16_t, /* ** cmpuo_0_f16: -** mov (z[0-9]+\.h), #0 -** fcmuo p0\.h, p1/z, (z0\.h, \1|\1, z0\.h) +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** fcmuo p0\.h, p1/z, (z0\.h, z\1\.h|z\1\.h, z0\.h) ** ret */ TEST_COMPARE_Z (cmpuo_0_f16, svfloat16_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpuo_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpuo_f32.c index 8827604aa3f035aaddb1b16004af4482a89cdce6..216c5db6ed6462bb09898afb84fdff7f106aa4a6 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpuo_f32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpuo_f32.c @@ -32,8 +32,8 @@ TEST_COMPARE_ZD (cmpuo_s4_f32, svfloat32_t, float32_t, /* ** cmpuo_0_f32: -** mov (z[0-9]+\.s), #0 -** fcmuo p0\.s, p1/z, (z0\.s, \1|\1, z0\.s) +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** fcmuo p0\.s, p1/z, (z0\.s, z\1\.s|z\1\.s, z0\.s) ** ret */ TEST_COMPARE_Z (cmpuo_0_f32, svfloat32_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpuo_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpuo_f64.c index d7a71eca464d8c5d26c3197538267815a44cc216..be4240215829ae544207ff467697b10dceec1828 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpuo_f64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpuo_f64.c @@ -32,8 +32,8 @@ TEST_COMPARE_ZD (cmpuo_d4_f64, svfloat64_t, float64_t, /* ** cmpuo_0_f64: -** mov (z[0-9]+\.d), #0 -** fcmuo p0\.d, p1/z, (z0\.d, \1|\1, z0\.d) +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** fcmuo p0\.d, p1/z, (z0\.d, z\1\.d|z\1\.d, z0\.d) ** ret */ TEST_COMPARE_Z (cmpuo_0_f64, svfloat64_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f16.c index a90c7118448cdf058db264f57c61a6cc51e89e5e..96fd4c5fae191939a6727b27e43583a00dc70e47 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f16.c @@ -13,7 +13,7 @@ TEST_UNIFORM_Z (dup_1_f16, svfloat16_t, /* ** dup_0_f16: -** mov z0\.h, #0 +** mov(?:i\td0|\tz0.[bhsd]), #0 ** ret */ TEST_UNIFORM_Z (dup_0_f16, svfloat16_t, @@ -120,7 +120,7 @@ TEST_UNIFORM_Z (dup_1_f16_z, svfloat16_t, /* ** dup_0_f16_z: -** mov z0\.[bhsd], #0 +** mov(?:i\td0|\tz0.[bhsd]), #0 ** ret */ TEST_UNIFORM_Z (dup_0_f16_z, svfloat16_t, @@ -170,7 +170,7 @@ TEST_UNIFORM_Z (dup_1_f16_x, svfloat16_t, /* ** dup_0_f16_x: -** mov z0\.h, #0 +** mov(?:i\td0|\tz0.[bhsd]), #0 ** ret */ TEST_UNIFORM_Z (dup_0_f16_x, svfloat16_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f32.c index ba23781429c87509606d168d0d96530dd70cc8f2..49b85874c9b0a8963ccc7446490f33a70593c461 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f32.c @@ -13,7 +13,7 @@ TEST_UNIFORM_Z (dup_1_f32, svfloat32_t, /* ** dup_0_f32: -** mov z0\.s, #0 +** mov(?:i\td0|\tz0.[bhsd]), #0 ** ret */ TEST_UNIFORM_Z (dup_0_f32, svfloat32_t, @@ -118,7 +118,7 @@ TEST_UNIFORM_Z (dup_1_f32_z, svfloat32_t, /* ** dup_0_f32_z: -** mov z0\.[bhsd], #0 +** mov(?:i\td0|\tz0.[bhsd]), #0 ** ret */ TEST_UNIFORM_Z (dup_0_f32_z, svfloat32_t, @@ -166,7 +166,7 @@ TEST_UNIFORM_Z (dup_1_f32_x, svfloat32_t, /* ** dup_0_f32_x: -** mov z0\.s, #0 +** mov(?:i\td0|\tz0.[bhsd]), #0 ** ret */ TEST_UNIFORM_Z (dup_0_f32_x, svfloat32_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f64.c index b397da885673a565c994415e6d6659f517c71e3a..1dbde173850b314e69d68ce8baf7917ad99d556d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f64.c @@ -13,7 +13,7 @@ TEST_UNIFORM_Z (dup_1_f64, svfloat64_t, /* ** dup_0_f64: -** mov z0\.d, #0 +** mov(?:i\td0|\tz0.[bhsd]), #0 ** ret */ TEST_UNIFORM_Z (dup_0_f64, svfloat64_t, @@ -118,7 +118,7 @@ TEST_UNIFORM_Z (dup_1_f64_z, svfloat64_t, /* ** dup_0_f64_z: -** mov z0\.[bhsd], #0 +** mov(?:i\td0|\tz0.[bhsd]), #0 ** ret */ TEST_UNIFORM_Z (dup_0_f64_z, svfloat64_t, @@ -166,7 +166,7 @@ TEST_UNIFORM_Z (dup_1_f64_x, svfloat64_t, /* ** dup_0_f64_x: -** mov z0\.d, #0 +** mov(?:i\td0|\tz0.[bhsd]), #0 ** ret */ TEST_UNIFORM_Z (dup_0_f64_x, svfloat64_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s16.c index 9c91a5bbad99ed8ec6b6aac582d44326bb369a10..0aa0237e930681b77ab2b22d6c4da92b3de9469f 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s16.c @@ -612,13 +612,13 @@ TEST_UNIFORM_Z (dup_127_s16_z, svint16_t, /* ** dup_128_s16_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.h), #128 -** sel z0\.h, p0, \2, \1\.h +** sel z0\.h, p0, \2, z\1\.h ** | ** mov (z[0-9]+\.h), #128 -** mov (z[0-9]+)\.b, #0 -** sel z0\.h, p0, \3, \4\.h +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.h, p0, \3, z\4\.h ** ) ** ret */ @@ -639,13 +639,13 @@ TEST_UNIFORM_Z (dup_253_s16_z, svint16_t, /* ** dup_254_s16_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.h), #254 -** sel z0\.h, p0, \2, \1\.h +** sel z0\.h, p0, \2, z\1\.h ** | ** mov (z[0-9]+\.h), #254 -** mov (z[0-9]+)\.b, #0 -** sel z0\.h, p0, \3, \4\.h +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.h, p0, \3, z\4\.h ** ) ** ret */ @@ -656,13 +656,13 @@ TEST_UNIFORM_Z (dup_254_s16_z, svint16_t, /* ** dup_255_s16_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.h), #255 -** sel z0\.h, p0, \2, \1\.h +** sel z0\.h, p0, \2, z\1\.h ** | ** mov (z[0-9]+\.h), #255 -** mov (z[0-9]+)\.b, #0 -** sel z0\.h, p0, \3, \4\.h +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.h, p0, \3, z\4\.h ** ) ** ret */ @@ -682,13 +682,13 @@ TEST_UNIFORM_Z (dup_256_s16_z, svint16_t, /* ** dup_257_s16_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+)\.b, #1 -** sel z0\.h, p0, \2\.h, \1\.h +** sel z0\.h, p0, \2\.h, z\1\.h ** | ** mov (z[0-9]+)\.b, #1 -** mov (z[0-9]+)\.b, #0 -** sel z0\.h, p0, \3\.h, \4\.h +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.h, p0, \3\.h, z\4\.h ** ) ** ret */ @@ -727,13 +727,13 @@ TEST_UNIFORM_Z (dup_7ffd_s16_z, svint16_t, /* ** dup_7ffe_s16_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.h), #32766 -** sel z0\.h, p0, \2, \1\.h +** sel z0\.h, p0, \2, z\1\.h ** | ** mov (z[0-9]+\.h), #32766 -** mov (z[0-9]+)\.b, #0 -** sel z0\.h, p0, \3, \4\.h +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.h, p0, \3, z\4\.h ** ) ** ret */ @@ -744,13 +744,13 @@ TEST_UNIFORM_Z (dup_7ffe_s16_z, svint16_t, /* ** dup_7fff_s16_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.h), #32767 -** sel z0\.h, p0, \2, \1\.h +** sel z0\.h, p0, \2, z\1\.h ** | ** mov (z[0-9]+\.h), #32767 -** mov (z[0-9]+)\.b, #0 -** sel z0\.h, p0, \3, \4\.h +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.h, p0, \3, z\4\.h ** ) ** ret */ @@ -779,13 +779,13 @@ TEST_UNIFORM_Z (dup_m128_s16_z, svint16_t, /* ** dup_m129_s16_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.h), #-129 -** sel z0\.h, p0, \2, \1\.h +** sel z0\.h, p0, \2, z\1\.h ** | ** mov (z[0-9]+\.h), #-129 -** mov (z[0-9]+)\.b, #0 -** sel z0\.h, p0, \3, \4\.h +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.h, p0, \3, z\4\.h ** ) ** ret */ @@ -806,13 +806,13 @@ TEST_UNIFORM_Z (dup_m254_s16_z, svint16_t, /* ** dup_m255_s16_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.h), #-255 -** sel z0\.h, p0, \2, \1\.h +** sel z0\.h, p0, \2, z\1\.h ** | ** mov (z[0-9]+\.h), #-255 -** mov (z[0-9]+)\.b, #0 -** sel z0\.h, p0, \3, \4\.h +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.h, p0, \3, z\4\.h ** ) ** ret */ @@ -832,13 +832,13 @@ TEST_UNIFORM_Z (dup_m256_s16_z, svint16_t, /* ** dup_m257_s16_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.h), #-257 -** sel z0\.h, p0, \2, \1\.h +** sel z0\.h, p0, \2, z\1\.h ** | ** mov (z[0-9]+\.h), #-257 -** mov (z[0-9]+)\.b, #0 -** sel z0\.h, p0, \3, \4\.h +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.h, p0, \3, z\4\.h ** ) ** ret */ @@ -849,13 +849,13 @@ TEST_UNIFORM_Z (dup_m257_s16_z, svint16_t, /* ** dup_m258_s16_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+)\.b, #-2 -** sel z0\.h, p0, \2\.h, \1\.h +** sel z0\.h, p0, \2\.h, z\1\.h ** | ** mov (z[0-9]+)\.b, #-2 -** mov (z[0-9]+)\.b, #0 -** sel z0\.h, p0, \3\.h, \4\.h +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.h, p0, \3\.h, z\4\.h ** ) ** ret */ @@ -889,13 +889,13 @@ TEST_UNIFORM_Z (dup_m7f00_s16_z, svint16_t, /* ** dup_m7f01_s16_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.h), #-32513 -** sel z0\.h, p0, \2, \1\.h +** sel z0\.h, p0, \2, z\1\.h ** | ** mov (z[0-9]+\.h), #-32513 -** mov (z[0-9]+)\.b, #0 -** sel z0\.h, p0, \3, \4\.h +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.h, p0, \3, z\4\.h ** ) ** ret */ @@ -916,13 +916,13 @@ TEST_UNIFORM_Z (dup_m7ffe_s16_z, svint16_t, /* ** dup_m7fff_s16_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.h), #-32767 -** sel z0\.h, p0, \2, \1\.h +** sel z0\.h, p0, \2, z\1\.h ** | ** mov (z[0-9]+\.h), #-32767 -** mov (z[0-9]+)\.b, #0 -** sel z0\.h, p0, \3, \4\.h +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.h, p0, \3, z\4\.h ** ) ** ret */ @@ -941,7 +941,7 @@ TEST_UNIFORM_Z (dup_m8000_s16_z, svint16_t, /* ** dup_0_s16_z: -** mov z0\.[bhsd], #0 +** mov(?:i\td0|\tz0.b), #0 ** ret */ TEST_UNIFORM_Z (dup_0_s16_z, svint16_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s32.c index 1cfecd962a4853b8eb4e42cd1578e4c26106a965..1a6596c1b1e919751feab698fb3abe221df050e3 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s32.c @@ -604,13 +604,13 @@ TEST_UNIFORM_Z (dup_127_s32_z, svint32_t, /* ** dup_128_s32_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.s), #128 -** sel z0\.s, p0, \2, \1\.s +** sel z0\.s, p0, \2, z\1\.s ** | ** mov (z[0-9]+\.s), #128 -** mov (z[0-9]+)\.b, #0 -** sel z0\.s, p0, \3, \4\.s +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.s, p0, \3, z\4\.s ** ) ** ret */ @@ -631,13 +631,13 @@ TEST_UNIFORM_Z (dup_253_s32_z, svint32_t, /* ** dup_254_s32_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.s), #254 -** sel z0\.s, p0, \2, \1\.s +** sel z0\.s, p0, \2, z\1\.s ** | ** mov (z[0-9]+\.s), #254 -** mov (z[0-9]+)\.b, #0 -** sel z0\.s, p0, \3, \4\.s +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.s, p0, \3, z\4\.s ** ) ** ret */ @@ -648,13 +648,13 @@ TEST_UNIFORM_Z (dup_254_s32_z, svint32_t, /* ** dup_255_s32_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.s), #255 -** sel z0\.s, p0, \2, \1\.s +** sel z0\.s, p0, \2, z\1\.s ** | ** mov (z[0-9]+\.s), #255 -** mov (z[0-9]+)\.b, #0 -** sel z0\.s, p0, \3, \4\.s +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.s, p0, \3, z\4\.s ** ) ** ret */ @@ -707,13 +707,13 @@ TEST_UNIFORM_Z (dup_7ffd_s32_z, svint32_t, /* ** dup_7ffe_s32_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.s), #32766 -** sel z0\.s, p0, \2, \1\.s +** sel z0\.s, p0, \2, z\1\.s ** | ** mov (z[0-9]+\.s), #32766 -** mov (z[0-9]+)\.b, #0 -** sel z0\.s, p0, \3, \4\.s +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.s, p0, \3, z\4\.s ** ) ** ret */ @@ -724,13 +724,13 @@ TEST_UNIFORM_Z (dup_7ffe_s32_z, svint32_t, /* ** dup_7fff_s32_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.s), #32767 -** sel z0\.s, p0, \2, \1\.s +** sel z0\.s, p0, \2, z\1\.s ** | ** mov (z[0-9]+\.s), #32767 -** mov (z[0-9]+)\.b, #0 -** sel z0\.s, p0, \3, \4\.s +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.s, p0, \3, z\4\.s ** ) ** ret */ @@ -759,13 +759,13 @@ TEST_UNIFORM_Z (dup_m128_s32_z, svint32_t, /* ** dup_m129_s32_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.s), #-129 -** sel z0\.s, p0, \2, \1\.s +** sel z0\.s, p0, \2, z\1\.s ** | ** mov (z[0-9]+\.s), #-129 -** mov (z[0-9]+)\.b, #0 -** sel z0\.s, p0, \3, \4\.s +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.s, p0, \3, z\4\.s ** ) ** ret */ @@ -786,13 +786,13 @@ TEST_UNIFORM_Z (dup_m254_s32_z, svint32_t, /* ** dup_m255_s32_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.s), #-255 -** sel z0\.s, p0, \2, \1\.s +** sel z0\.s, p0, \2, z\1\.s ** | ** mov (z[0-9]+\.s), #-255 -** mov (z[0-9]+)\.b, #0 -** sel z0\.s, p0, \3, \4\.s +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.s, p0, \3, z\4\.s ** ) ** ret */ @@ -812,13 +812,13 @@ TEST_UNIFORM_Z (dup_m256_s32_z, svint32_t, /* ** dup_m257_s32_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.s), #-257 -** sel z0\.s, p0, \2, \1\.s +** sel z0\.s, p0, \2, z\1\.s ** | ** mov (z[0-9]+\.s), #-257 -** mov (z[0-9]+)\.b, #0 -** sel z0\.s, p0, \3, \4\.s +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.s, p0, \3, z\4\.s ** ) ** ret */ @@ -857,13 +857,13 @@ TEST_UNIFORM_Z (dup_m7f00_s32_z, svint32_t, /* ** dup_m7f01_s32_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.s), #-32513 -** sel z0\.s, p0, \2, \1\.s +** sel z0\.s, p0, \2, z\1\.s ** | ** mov (z[0-9]+\.s), #-32513 -** mov (z[0-9]+)\.b, #0 -** sel z0\.s, p0, \3, \4\.s +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.s, p0, \3, z\4\.s ** ) ** ret */ @@ -884,13 +884,13 @@ TEST_UNIFORM_Z (dup_m7ffe_s32_z, svint32_t, /* ** dup_m7fff_s32_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.s), #-32767 -** sel z0\.s, p0, \2, \1\.s +** sel z0\.s, p0, \2, z\1\.s ** | ** mov (z[0-9]+\.s), #-32767 -** mov (z[0-9]+)\.b, #0 -** sel z0\.s, p0, \3, \4\.s +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.s, p0, \3, z\4\.s ** ) ** ret */ @@ -909,7 +909,7 @@ TEST_UNIFORM_Z (dup_m8000_s32_z, svint32_t, /* ** dup_0_s32_z: -** mov z0\.[bhsd], #0 +** mov(?:i\td0|\tz0.b), #0 ** ret */ TEST_UNIFORM_Z (dup_0_s32_z, svint32_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s64.c index 5189dcf590ab5887cee824b878ccc76473f21737..2cd930021b399759e4ef976f0871762229d374c0 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s64.c @@ -604,13 +604,13 @@ TEST_UNIFORM_Z (dup_127_s64_z, svint64_t, /* ** dup_128_s64_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.d), #128 -** sel z0\.d, p0, \2, \1\.d +** sel z0\.d, p0, \2, z\1\.d ** | ** mov (z[0-9]+\.d), #128 -** mov (z[0-9]+)\.b, #0 -** sel z0\.d, p0, \3, \4\.d +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.d, p0, \3, z\4\.d ** ) ** ret */ @@ -631,13 +631,13 @@ TEST_UNIFORM_Z (dup_253_s64_z, svint64_t, /* ** dup_254_s64_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.d), #254 -** sel z0\.d, p0, \2, \1\.d +** sel z0\.d, p0, \2, z\1\.d ** | ** mov (z[0-9]+\.d), #254 -** mov (z[0-9]+)\.b, #0 -** sel z0\.d, p0, \3, \4\.d +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.d, p0, \3, z\4\.d ** ) ** ret */ @@ -648,13 +648,13 @@ TEST_UNIFORM_Z (dup_254_s64_z, svint64_t, /* ** dup_255_s64_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.d), #255 -** sel z0\.d, p0, \2, \1\.d +** sel z0\.d, p0, \2, z\1\.d ** | ** mov (z[0-9]+\.d), #255 -** mov (z[0-9]+)\.b, #0 -** sel z0\.d, p0, \3, \4\.d +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.d, p0, \3, z\4\.d ** ) ** ret */ @@ -707,13 +707,13 @@ TEST_UNIFORM_Z (dup_7ffd_s64_z, svint64_t, /* ** dup_7ffe_s64_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.d), #32766 -** sel z0\.d, p0, \2, \1\.d +** sel z0\.d, p0, \2, z\1\.d ** | ** mov (z[0-9]+\.d), #32766 -** mov (z[0-9]+)\.b, #0 -** sel z0\.d, p0, \3, \4\.d +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.d, p0, \3, z\4\.d ** ) ** ret */ @@ -724,13 +724,13 @@ TEST_UNIFORM_Z (dup_7ffe_s64_z, svint64_t, /* ** dup_7fff_s64_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.d), #32767 -** sel z0\.d, p0, \2, \1\.d +** sel z0\.d, p0, \2, z\1\.d ** | ** mov (z[0-9]+\.d), #32767 -** mov (z[0-9]+)\.b, #0 -** sel z0\.d, p0, \3, \4\.d +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.d, p0, \3, z\4\.d ** ) ** ret */ @@ -759,13 +759,13 @@ TEST_UNIFORM_Z (dup_m128_s64_z, svint64_t, /* ** dup_m129_s64_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.d), #-129 -** sel z0\.d, p0, \2, \1\.d +** sel z0\.d, p0, \2, z\1\.d ** | ** mov (z[0-9]+\.d), #-129 -** mov (z[0-9]+)\.b, #0 -** sel z0\.d, p0, \3, \4\.d +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.d, p0, \3, z\4\.d ** ) ** ret */ @@ -786,13 +786,13 @@ TEST_UNIFORM_Z (dup_m254_s64_z, svint64_t, /* ** dup_m255_s64_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.d), #-255 -** sel z0\.d, p0, \2, \1\.d +** sel z0\.d, p0, \2, z\1\.d ** | ** mov (z[0-9]+\.d), #-255 -** mov (z[0-9]+)\.b, #0 -** sel z0\.d, p0, \3, \4\.d +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.d, p0, \3, z\4\.d ** ) ** ret */ @@ -812,13 +812,13 @@ TEST_UNIFORM_Z (dup_m256_s64_z, svint64_t, /* ** dup_m257_s64_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.d), #-257 -** sel z0\.d, p0, \2, \1\.d +** sel z0\.d, p0, \2, z\1\.d ** | ** mov (z[0-9]+\.d), #-257 -** mov (z[0-9]+)\.b, #0 -** sel z0\.d, p0, \3, \4\.d +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.d, p0, \3, z\4\.d ** ) ** ret */ @@ -857,13 +857,13 @@ TEST_UNIFORM_Z (dup_m7f00_s64_z, svint64_t, /* ** dup_m7f01_s64_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.d), #-32513 -** sel z0\.d, p0, \2, \1\.d +** sel z0\.d, p0, \2, z\1\.d ** | ** mov (z[0-9]+\.d), #-32513 -** mov (z[0-9]+)\.b, #0 -** sel z0\.d, p0, \3, \4\.d +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.d, p0, \3, z\4\.d ** ) ** ret */ @@ -884,13 +884,13 @@ TEST_UNIFORM_Z (dup_m7ffe_s64_z, svint64_t, /* ** dup_m7fff_s64_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.d), #-32767 -** sel z0\.d, p0, \2, \1\.d +** sel z0\.d, p0, \2, z\1\.d ** | ** mov (z[0-9]+\.d), #-32767 -** mov (z[0-9]+)\.b, #0 -** sel z0\.d, p0, \3, \4\.d +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.d, p0, \3, z\4\.d ** ) ** ret */ @@ -909,7 +909,7 @@ TEST_UNIFORM_Z (dup_m8000_s64_z, svint64_t, /* ** dup_0_s64_z: -** mov z0\.[bhsd], #0 +** mov(?:i\td0|\tz0.b), #0 ** ret */ TEST_UNIFORM_Z (dup_0_s64_z, svint64_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s8.c index f3c9db8ead70187dd9ce0e0570ce0e499399bded..1ca4711c6f2d6c731dadeff3c5b0874d97eb5681 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s8.c @@ -275,7 +275,7 @@ TEST_UNIFORM_Z (dup_m128_s8_z, svint8_t, /* ** dup_0_s8_z: -** mov z0\.[bhsd], #0 +** mov(?:i\td0|\tz0.b), #0 ** ret */ TEST_UNIFORM_Z (dup_0_s8_z, svint8_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u16.c index 09fecd44b882883cebab33c55c594b3dd09d5a7b..5ec452857aa26698aaced662cd92270bd651f9e5 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u16.c @@ -612,13 +612,13 @@ TEST_UNIFORM_Z (dup_127_u16_z, svuint16_t, /* ** dup_128_u16_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.h), #128 -** sel z0\.h, p0, \2, \1\.h +** sel z0\.h, p0, \2, z\1\.h ** | ** mov (z[0-9]+\.h), #128 -** mov (z[0-9]+)\.b, #0 -** sel z0\.h, p0, \3, \4\.h +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.h, p0, \3, z\4\.h ** ) ** ret */ @@ -639,13 +639,13 @@ TEST_UNIFORM_Z (dup_253_u16_z, svuint16_t, /* ** dup_254_u16_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.h), #254 -** sel z0\.h, p0, \2, \1\.h +** sel z0\.h, p0, \2, z\1\.h ** | ** mov (z[0-9]+\.h), #254 -** mov (z[0-9]+)\.b, #0 -** sel z0\.h, p0, \3, \4\.h +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.h, p0, \3, z\4\.h ** ) ** ret */ @@ -656,13 +656,13 @@ TEST_UNIFORM_Z (dup_254_u16_z, svuint16_t, /* ** dup_255_u16_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.h), #255 -** sel z0\.h, p0, \2, \1\.h +** sel z0\.h, p0, \2, z\1\.h ** | ** mov (z[0-9]+\.h), #255 -** mov (z[0-9]+)\.b, #0 -** sel z0\.h, p0, \3, \4\.h +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.h, p0, \3, z\4\.h ** ) ** ret */ @@ -682,13 +682,13 @@ TEST_UNIFORM_Z (dup_256_u16_z, svuint16_t, /* ** dup_257_u16_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+)\.b, #1 -** sel z0\.h, p0, \2\.h, \1\.h +** sel z0\.h, p0, \2\.h, z\1\.h ** | ** mov (z[0-9]+)\.b, #1 -** mov (z[0-9]+)\.b, #0 -** sel z0\.h, p0, \3\.h, \4\.h +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.h, p0, \3\.h, z\4\.h ** ) ** ret */ @@ -727,13 +727,13 @@ TEST_UNIFORM_Z (dup_7ffd_u16_z, svuint16_t, /* ** dup_7ffe_u16_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.h), #32766 -** sel z0\.h, p0, \2, \1\.h +** sel z0\.h, p0, \2, z\1\.h ** | ** mov (z[0-9]+\.h), #32766 -** mov (z[0-9]+)\.b, #0 -** sel z0\.h, p0, \3, \4\.h +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.h, p0, \3, z\4\.h ** ) ** ret */ @@ -744,13 +744,13 @@ TEST_UNIFORM_Z (dup_7ffe_u16_z, svuint16_t, /* ** dup_7fff_u16_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.h), #32767 -** sel z0\.h, p0, \2, \1\.h +** sel z0\.h, p0, \2, z\1\.h ** | ** mov (z[0-9]+\.h), #32767 -** mov (z[0-9]+)\.b, #0 -** sel z0\.h, p0, \3, \4\.h +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.h, p0, \3, z\4\.h ** ) ** ret */ @@ -779,13 +779,13 @@ TEST_UNIFORM_Z (dup_m128_u16_z, svuint16_t, /* ** dup_m129_u16_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.h), #-129 -** sel z0\.h, p0, \2, \1\.h +** sel z0\.h, p0, \2, z\1\.h ** | ** mov (z[0-9]+\.h), #-129 -** mov (z[0-9]+)\.b, #0 -** sel z0\.h, p0, \3, \4\.h +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.h, p0, \3, z\4\.h ** ) ** ret */ @@ -806,13 +806,13 @@ TEST_UNIFORM_Z (dup_m254_u16_z, svuint16_t, /* ** dup_m255_u16_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.h), #-255 -** sel z0\.h, p0, \2, \1\.h +** sel z0\.h, p0, \2, z\1\.h ** | ** mov (z[0-9]+\.h), #-255 -** mov (z[0-9]+)\.b, #0 -** sel z0\.h, p0, \3, \4\.h +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.h, p0, \3, z\4\.h ** ) ** ret */ @@ -832,13 +832,13 @@ TEST_UNIFORM_Z (dup_m256_u16_z, svuint16_t, /* ** dup_m257_u16_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.h), #-257 -** sel z0\.h, p0, \2, \1\.h +** sel z0\.h, p0, \2, z\1\.h ** | ** mov (z[0-9]+\.h), #-257 -** mov (z[0-9]+)\.b, #0 -** sel z0\.h, p0, \3, \4\.h +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.h, p0, \3, z\4\.h ** ) ** ret */ @@ -849,13 +849,13 @@ TEST_UNIFORM_Z (dup_m257_u16_z, svuint16_t, /* ** dup_m258_u16_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+)\.b, #-2 -** sel z0\.h, p0, \2\.h, \1\.h +** sel z0\.h, p0, \2\.h, z\1\.h ** | ** mov (z[0-9]+)\.b, #-2 -** mov (z[0-9]+)\.b, #0 -** sel z0\.h, p0, \3\.h, \4\.h +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.h, p0, \3\.h, z\4\.h ** ) ** ret */ @@ -889,13 +889,13 @@ TEST_UNIFORM_Z (dup_m7f00_u16_z, svuint16_t, /* ** dup_m7f01_u16_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.h), #-32513 -** sel z0\.h, p0, \2, \1\.h +** sel z0\.h, p0, \2, z\1\.h ** | ** mov (z[0-9]+\.h), #-32513 -** mov (z[0-9]+)\.b, #0 -** sel z0\.h, p0, \3, \4\.h +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.h, p0, \3, z\4\.h ** ) ** ret */ @@ -916,13 +916,13 @@ TEST_UNIFORM_Z (dup_m7ffe_u16_z, svuint16_t, /* ** dup_m7fff_u16_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.h), #-32767 -** sel z0\.h, p0, \2, \1\.h +** sel z0\.h, p0, \2, z\1\.h ** | ** mov (z[0-9]+\.h), #-32767 -** mov (z[0-9]+)\.b, #0 -** sel z0\.h, p0, \3, \4\.h +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.h, p0, \3, z\4\.h ** ) ** ret */ @@ -941,7 +941,7 @@ TEST_UNIFORM_Z (dup_m8000_u16_z, svuint16_t, /* ** dup_0_u16_z: -** mov z0\.[bhsd], #0 +** mov(?:i\td0|\tz0.b), #0 ** ret */ TEST_UNIFORM_Z (dup_0_u16_z, svuint16_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u32.c index 4b7da13a456b8ca050764b2b75b4b12a93b24952..0abc58f56a4bd4e79a9b22eb4da81498d284e243 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u32.c @@ -604,13 +604,13 @@ TEST_UNIFORM_Z (dup_127_u32_z, svuint32_t, /* ** dup_128_u32_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.s), #128 -** sel z0\.s, p0, \2, \1\.s +** sel z0\.s, p0, \2, z\1\.s ** | ** mov (z[0-9]+\.s), #128 -** mov (z[0-9]+)\.b, #0 -** sel z0\.s, p0, \3, \4\.s +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.s, p0, \3, z\4\.s ** ) ** ret */ @@ -631,13 +631,13 @@ TEST_UNIFORM_Z (dup_253_u32_z, svuint32_t, /* ** dup_254_u32_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.s), #254 -** sel z0\.s, p0, \2, \1\.s +** sel z0\.s, p0, \2, z\1\.s ** | ** mov (z[0-9]+\.s), #254 -** mov (z[0-9]+)\.b, #0 -** sel z0\.s, p0, \3, \4\.s +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.s, p0, \3, z\4\.s ** ) ** ret */ @@ -648,13 +648,13 @@ TEST_UNIFORM_Z (dup_254_u32_z, svuint32_t, /* ** dup_255_u32_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.s), #255 -** sel z0\.s, p0, \2, \1\.s +** sel z0\.s, p0, \2, z\1\.s ** | ** mov (z[0-9]+\.s), #255 -** mov (z[0-9]+)\.b, #0 -** sel z0\.s, p0, \3, \4\.s +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.s, p0, \3, z\4\.s ** ) ** ret */ @@ -707,13 +707,13 @@ TEST_UNIFORM_Z (dup_7ffd_u32_z, svuint32_t, /* ** dup_7ffe_u32_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.s), #32766 -** sel z0\.s, p0, \2, \1\.s +** sel z0\.s, p0, \2, z\1\.s ** | ** mov (z[0-9]+\.s), #32766 -** mov (z[0-9]+)\.b, #0 -** sel z0\.s, p0, \3, \4\.s +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.s, p0, \3, z\4\.s ** ) ** ret */ @@ -724,13 +724,13 @@ TEST_UNIFORM_Z (dup_7ffe_u32_z, svuint32_t, /* ** dup_7fff_u32_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.s), #32767 -** sel z0\.s, p0, \2, \1\.s +** sel z0\.s, p0, \2, z\1\.s ** | ** mov (z[0-9]+\.s), #32767 -** mov (z[0-9]+)\.b, #0 -** sel z0\.s, p0, \3, \4\.s +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.s, p0, \3, z\4\.s ** ) ** ret */ @@ -759,13 +759,13 @@ TEST_UNIFORM_Z (dup_m128_u32_z, svuint32_t, /* ** dup_m129_u32_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.s), #-129 -** sel z0\.s, p0, \2, \1\.s +** sel z0\.s, p0, \2, z\1\.s ** | ** mov (z[0-9]+\.s), #-129 -** mov (z[0-9]+)\.b, #0 -** sel z0\.s, p0, \3, \4\.s +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.s, p0, \3, z\4\.s ** ) ** ret */ @@ -786,13 +786,13 @@ TEST_UNIFORM_Z (dup_m254_u32_z, svuint32_t, /* ** dup_m255_u32_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.s), #-255 -** sel z0\.s, p0, \2, \1\.s +** sel z0\.s, p0, \2, z\1\.s ** | ** mov (z[0-9]+\.s), #-255 -** mov (z[0-9]+)\.b, #0 -** sel z0\.s, p0, \3, \4\.s +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.s, p0, \3, z\4\.s ** ) ** ret */ @@ -812,13 +812,13 @@ TEST_UNIFORM_Z (dup_m256_u32_z, svuint32_t, /* ** dup_m257_u32_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.s), #-257 -** sel z0\.s, p0, \2, \1\.s +** sel z0\.s, p0, \2, z\1\.s ** | ** mov (z[0-9]+\.s), #-257 -** mov (z[0-9]+)\.b, #0 -** sel z0\.s, p0, \3, \4\.s +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.s, p0, \3, z\4\.s ** ) ** ret */ @@ -857,13 +857,13 @@ TEST_UNIFORM_Z (dup_m7f00_u32_z, svuint32_t, /* ** dup_m7f01_u32_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.s), #-32513 -** sel z0\.s, p0, \2, \1\.s +** sel z0\.s, p0, \2, z\1\.s ** | ** mov (z[0-9]+\.s), #-32513 -** mov (z[0-9]+)\.b, #0 -** sel z0\.s, p0, \3, \4\.s +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.s, p0, \3, z\4\.s ** ) ** ret */ @@ -884,13 +884,13 @@ TEST_UNIFORM_Z (dup_m7ffe_u32_z, svuint32_t, /* ** dup_m7fff_u32_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.s), #-32767 -** sel z0\.s, p0, \2, \1\.s +** sel z0\.s, p0, \2, z\1\.s ** | ** mov (z[0-9]+\.s), #-32767 -** mov (z[0-9]+)\.b, #0 -** sel z0\.s, p0, \3, \4\.s +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.s, p0, \3, z\4\.s ** ) ** ret */ @@ -909,7 +909,7 @@ TEST_UNIFORM_Z (dup_m8000_u32_z, svuint32_t, /* ** dup_0_u32_z: -** mov z0\.[bhsd], #0 +** mov(?:i\td0|\tz0.b), #0 ** ret */ TEST_UNIFORM_Z (dup_0_u32_z, svuint32_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u64.c index 4d64b40a90bc535dbd653e7b8ca05be1dd456ecd..011959708e27f6b78940085f6b21edd75540f60d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u64.c @@ -604,13 +604,13 @@ TEST_UNIFORM_Z (dup_127_u64_z, svuint64_t, /* ** dup_128_u64_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.d), #128 -** sel z0\.d, p0, \2, \1\.d +** sel z0\.d, p0, \2, z\1\.d ** | ** mov (z[0-9]+\.d), #128 -** mov (z[0-9]+)\.b, #0 -** sel z0\.d, p0, \3, \4\.d +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.d, p0, \3, z\4\.d ** ) ** ret */ @@ -631,13 +631,13 @@ TEST_UNIFORM_Z (dup_253_u64_z, svuint64_t, /* ** dup_254_u64_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.d), #254 -** sel z0\.d, p0, \2, \1\.d +** sel z0\.d, p0, \2, z\1\.d ** | ** mov (z[0-9]+\.d), #254 -** mov (z[0-9]+)\.b, #0 -** sel z0\.d, p0, \3, \4\.d +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.d, p0, \3, z\4\.d ** ) ** ret */ @@ -648,13 +648,13 @@ TEST_UNIFORM_Z (dup_254_u64_z, svuint64_t, /* ** dup_255_u64_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.d), #255 -** sel z0\.d, p0, \2, \1\.d +** sel z0\.d, p0, \2, z\1\.d ** | ** mov (z[0-9]+\.d), #255 -** mov (z[0-9]+)\.b, #0 -** sel z0\.d, p0, \3, \4\.d +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.d, p0, \3, z\4\.d ** ) ** ret */ @@ -707,13 +707,13 @@ TEST_UNIFORM_Z (dup_7ffd_u64_z, svuint64_t, /* ** dup_7ffe_u64_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.d), #32766 -** sel z0\.d, p0, \2, \1\.d +** sel z0\.d, p0, \2, z\1\.d ** | ** mov (z[0-9]+\.d), #32766 -** mov (z[0-9]+)\.b, #0 -** sel z0\.d, p0, \3, \4\.d +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.d, p0, \3, z\4\.d ** ) ** ret */ @@ -724,13 +724,13 @@ TEST_UNIFORM_Z (dup_7ffe_u64_z, svuint64_t, /* ** dup_7fff_u64_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.d), #32767 -** sel z0\.d, p0, \2, \1\.d +** sel z0\.d, p0, \2, z\1\.d ** | ** mov (z[0-9]+\.d), #32767 -** mov (z[0-9]+)\.b, #0 -** sel z0\.d, p0, \3, \4\.d +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.d, p0, \3, z\4\.d ** ) ** ret */ @@ -759,13 +759,13 @@ TEST_UNIFORM_Z (dup_m128_u64_z, svuint64_t, /* ** dup_m129_u64_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.d), #-129 -** sel z0\.d, p0, \2, \1\.d +** sel z0\.d, p0, \2, z\1\.d ** | ** mov (z[0-9]+\.d), #-129 -** mov (z[0-9]+)\.b, #0 -** sel z0\.d, p0, \3, \4\.d +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.d, p0, \3, z\4\.d ** ) ** ret */ @@ -786,13 +786,13 @@ TEST_UNIFORM_Z (dup_m254_u64_z, svuint64_t, /* ** dup_m255_u64_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.d), #-255 -** sel z0\.d, p0, \2, \1\.d +** sel z0\.d, p0, \2, z\1\.d ** | ** mov (z[0-9]+\.d), #-255 -** mov (z[0-9]+)\.b, #0 -** sel z0\.d, p0, \3, \4\.d +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.d, p0, \3, z\4\.d ** ) ** ret */ @@ -812,13 +812,13 @@ TEST_UNIFORM_Z (dup_m256_u64_z, svuint64_t, /* ** dup_m257_u64_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.d), #-257 -** sel z0\.d, p0, \2, \1\.d +** sel z0\.d, p0, \2, z\1\.d ** | ** mov (z[0-9]+\.d), #-257 -** mov (z[0-9]+)\.b, #0 -** sel z0\.d, p0, \3, \4\.d +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.d, p0, \3, z\4\.d ** ) ** ret */ @@ -857,13 +857,13 @@ TEST_UNIFORM_Z (dup_m7f00_u64_z, svuint64_t, /* ** dup_m7f01_u64_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.d), #-32513 -** sel z0\.d, p0, \2, \1\.d +** sel z0\.d, p0, \2, z\1\.d ** | ** mov (z[0-9]+\.d), #-32513 -** mov (z[0-9]+)\.b, #0 -** sel z0\.d, p0, \3, \4\.d +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.d, p0, \3, z\4\.d ** ) ** ret */ @@ -884,13 +884,13 @@ TEST_UNIFORM_Z (dup_m7ffe_u64_z, svuint64_t, /* ** dup_m7fff_u64_z: ** ( -** mov (z[0-9]+)\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** mov (z[0-9]+\.d), #-32767 -** sel z0\.d, p0, \2, \1\.d +** sel z0\.d, p0, \2, z\1\.d ** | ** mov (z[0-9]+\.d), #-32767 -** mov (z[0-9]+)\.b, #0 -** sel z0\.d, p0, \3, \4\.d +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sel z0\.d, p0, \3, z\4\.d ** ) ** ret */ @@ -909,7 +909,7 @@ TEST_UNIFORM_Z (dup_m8000_u64_z, svuint64_t, /* ** dup_0_u64_z: -** mov z0\.[bhsd], #0 +** mov(?:i\td0|\tz0.b), #0 ** ret */ TEST_UNIFORM_Z (dup_0_u64_z, svuint64_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u8.c index 1bb4cc1bd794ff9a36d52d44bbfcb723e78c01df..7094c3028ee4b2b9ae64e3f95599ac84f64a44f7 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u8.c @@ -275,7 +275,7 @@ TEST_UNIFORM_Z (dup_m128_u8_z, svuint8_t, /* ** dup_0_u8_z: -** mov z0\.[bhsd], #0 +** mov(?:i\td0|\tz0.b), #0 ** ret */ TEST_UNIFORM_Z (dup_0_u8_z, svuint8_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/const_fold_div_1.c b/gcc/testsuite/gcc.target/aarch64/sve/const_fold_div_1.c index 92e0005c0fee325928b000ef5547446fcd1bf442..c33be445a0d5c7158bea046f7eb84b08a27a735a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/const_fold_div_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/const_fold_div_1.c @@ -15,7 +15,7 @@ svint64_t s64_x_pg (svbool_t pg) /* ** s64_x_pg_0: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_x_pg_0 (svbool_t pg) @@ -25,7 +25,7 @@ svint64_t s64_x_pg_0 (svbool_t pg) /* ** s64_x_pg_by0: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_x_pg_by0 (svbool_t pg) @@ -45,7 +45,7 @@ svint64_t s64_z_pg (svbool_t pg) /* ** s64_z_pg_0: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_z_pg_0 (svbool_t pg) @@ -55,7 +55,7 @@ svint64_t s64_z_pg_0 (svbool_t pg) /* ** s64_z_pg_by0: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_z_pg_by0 (svbool_t pg) @@ -117,7 +117,7 @@ svint64_t s64_x_pg_n (svbool_t pg) /* ** s64_x_pg_n_s64_0: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_x_pg_n_s64_0 (svbool_t pg) @@ -127,7 +127,7 @@ svint64_t s64_x_pg_n_s64_0 (svbool_t pg) /* ** s64_x_pg_n_s64_by0: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_x_pg_n_s64_by0 (svbool_t pg) @@ -147,7 +147,7 @@ svint64_t s64_z_pg_n (svbool_t pg) /* ** s64_z_pg_n_s64_0: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_z_pg_n_s64_0 (svbool_t pg) @@ -157,7 +157,7 @@ svint64_t s64_z_pg_n_s64_0 (svbool_t pg) /* ** s64_z_pg_n_s64_by0: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_z_pg_n_s64_by0 (svbool_t pg) @@ -209,7 +209,7 @@ svint64_t s64_m_ptrue_n () /* ** s32_m_ptrue_dupq: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint32_t s32_m_ptrue_dupq () diff --git a/gcc/testsuite/gcc.target/aarch64/sve/const_fold_mul_1.c b/gcc/testsuite/gcc.target/aarch64/sve/const_fold_mul_1.c index 2a00cab5a79df8ae4e73462d86f567a7675b0d4e..423021096b00bda50c9f4bbf21140f7582196c81 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/const_fold_mul_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/const_fold_mul_1.c @@ -15,7 +15,7 @@ svint64_t s64_x_pg (svbool_t pg) /* ** s64_x_pg_0: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_x_pg_0 (svbool_t pg) @@ -35,7 +35,7 @@ svint64_t s64_z_pg (svbool_t pg) /* ** s64_z_pg_0: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_z_pg_0 (svbool_t pg) @@ -97,7 +97,7 @@ svint64_t s64_x_pg_n (svbool_t pg) /* ** s64_x_pg_n_s64_0: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_x_pg_n_s64_0 (svbool_t pg) @@ -117,7 +117,7 @@ svint64_t s64_z_pg_n (svbool_t pg) /* ** s64_z_pg_n_s64_0: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_z_pg_n_s64_0 (svbool_t pg) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/dup_imm_1.c b/gcc/testsuite/gcc.target/aarch64/sve/dup_imm_1.c index 3b8854ebc3169565ef3f585969c89935f14d1e87..663e988871c88f60c8ab6f47c495e9089112a118 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/dup_imm_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/dup_imm_1.c @@ -99,7 +99,7 @@ DEF_SET_IMM (int32_t, -32763, imm_m32763) /* { dg-final { scan-assembler {\tmov\tz[0-9]+\.b, #-1\n} } } */ -/* { dg-final { scan-assembler {\tmov\tz[0-9]+\.b, #0\n} } } */ +/* { dg-final { scan-assembler {\tmov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0\n} } } */ /* { dg-final { scan-assembler {\tmov\tz[0-9]+\.b, #1\n} } } */ /* { dg-final { scan-assembler {\tmov\tz[0-9]+\.h, #1\n} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/fdup_1.c b/gcc/testsuite/gcc.target/aarch64/sve/fdup_1.c index c13efd86919466f193581d14c6a86c0f227a9648..51a5e392b48c74e3f0865307ba082a1aaed25d41 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/fdup_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/fdup_1.c @@ -47,8 +47,6 @@ DEF_SET_IMM_FP (0x1.1fp-4, imm1fpm4) /* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.s, #3.1e\+1\n} 1 } } */ /* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.s, #2.421875e-1\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.s, #0\n} 1 } } */ - /* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.d,} 7 } } */ /* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.d, #1.0e\+0\n} 1 } } */ @@ -59,4 +57,4 @@ DEF_SET_IMM_FP (0x1.1fp-4, imm1fpm4) /* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.d, #3.1e\+1\n} 1 } } */ /* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.d, #2.421875e-1\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, #0\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tmov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/fold_div_zero.c b/gcc/testsuite/gcc.target/aarch64/sve/fold_div_zero.c index 0dcd018cadc8d35b23a796900d821415530ff7b4..9d5b36309ebb88fa1b5d1ba8c74f5106cd46f29c 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/fold_div_zero.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/fold_div_zero.c @@ -5,7 +5,7 @@ /* ** s64_x_pg_op1: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_x_pg_op1 (svbool_t pg, svint64_t op2) @@ -15,7 +15,7 @@ svint64_t s64_x_pg_op1 (svbool_t pg, svint64_t op2) /* ** s64_z_pg_op1: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_z_pg_op1 (svbool_t pg, svint64_t op2) @@ -25,7 +25,7 @@ svint64_t s64_z_pg_op1 (svbool_t pg, svint64_t op2) /* ** s64_m_pg_op1: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_m_pg_op1 (svbool_t pg, svint64_t op2) @@ -35,7 +35,7 @@ svint64_t s64_m_pg_op1 (svbool_t pg, svint64_t op2) /* ** s64_x_ptrue_op1: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_x_ptrue_op1 (svint64_t op2) @@ -45,7 +45,7 @@ svint64_t s64_x_ptrue_op1 (svint64_t op2) /* ** s64_z_ptrue_op1: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_z_ptrue_op1 (svint64_t op2) @@ -55,7 +55,7 @@ svint64_t s64_z_ptrue_op1 (svint64_t op2) /* ** s64_m_ptrue_op1: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_m_ptrue_op1 (svint64_t op2) @@ -65,7 +65,7 @@ svint64_t s64_m_ptrue_op1 (svint64_t op2) /* ** s64_x_pg_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_x_pg_op2 (svbool_t pg, svint64_t op1) @@ -75,7 +75,7 @@ svint64_t s64_x_pg_op2 (svbool_t pg, svint64_t op1) /* ** s64_z_pg_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_z_pg_op2 (svbool_t pg, svint64_t op1) @@ -85,8 +85,8 @@ svint64_t s64_z_pg_op2 (svbool_t pg, svint64_t op1) /* ** s64_m_pg_op2: -** mov (z[0-9]+)\.b, #0 -** sdiv (z[0-9]\.d), p[0-7]/m, \2, \1\.d +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sdiv (z[0-9]\.d), p[0-7]/m, \2, z\1\.d ** ret */ svint64_t s64_m_pg_op2 (svbool_t pg, svint64_t op1) @@ -96,7 +96,7 @@ svint64_t s64_m_pg_op2 (svbool_t pg, svint64_t op1) /* ** s64_x_ptrue_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_x_ptrue_op2 (svint64_t op1) @@ -106,7 +106,7 @@ svint64_t s64_x_ptrue_op2 (svint64_t op1) /* ** s64_z_ptrue_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_z_ptrue_op2 (svint64_t op1) @@ -116,7 +116,7 @@ svint64_t s64_z_ptrue_op2 (svint64_t op1) /* ** s64_m_ptrue_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_m_ptrue_op2 (svint64_t op1) @@ -126,7 +126,7 @@ svint64_t s64_m_ptrue_op2 (svint64_t op1) /* ** s64_n_x_pg_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_n_x_pg_op2 (svbool_t pg, svint64_t op1) @@ -136,7 +136,7 @@ svint64_t s64_n_x_pg_op2 (svbool_t pg, svint64_t op1) /* ** s64_n_z_pg_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_n_z_pg_op2 (svbool_t pg, svint64_t op1) @@ -146,8 +146,8 @@ svint64_t s64_n_z_pg_op2 (svbool_t pg, svint64_t op1) /* ** s64_n_m_pg_op2: -** mov (z[0-9]+)\.b, #0 -** sdiv (z[0-9]+\.d), p[0-7]/m, \2, \1\.d +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** sdiv (z[0-9]+\.d), p[0-7]/m, \2, z\1\.d ** ret */ svint64_t s64_n_m_pg_op2 (svbool_t pg, svint64_t op1) @@ -157,7 +157,7 @@ svint64_t s64_n_m_pg_op2 (svbool_t pg, svint64_t op1) /* ** s64_n_x_ptrue_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_n_x_ptrue_op2 (svint64_t op1) @@ -167,7 +167,7 @@ svint64_t s64_n_x_ptrue_op2 (svint64_t op1) /* ** s64_n_z_ptrue_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_n_z_ptrue_op2 (svint64_t op1) @@ -177,7 +177,7 @@ svint64_t s64_n_z_ptrue_op2 (svint64_t op1) /* ** s64_n_m_ptrue_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_n_m_ptrue_op2 (svint64_t op1) @@ -187,7 +187,7 @@ svint64_t s64_n_m_ptrue_op2 (svint64_t op1) /* ** u64_x_pg_op1: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svuint64_t u64_x_pg_op1 (svbool_t pg, svuint64_t op2) @@ -197,7 +197,7 @@ svuint64_t u64_x_pg_op1 (svbool_t pg, svuint64_t op2) /* ** u64_z_pg_op1: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svuint64_t u64_z_pg_op1 (svbool_t pg, svuint64_t op2) @@ -207,7 +207,7 @@ svuint64_t u64_z_pg_op1 (svbool_t pg, svuint64_t op2) /* ** u64_m_pg_op1: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svuint64_t u64_m_pg_op1 (svbool_t pg, svuint64_t op2) @@ -217,7 +217,7 @@ svuint64_t u64_m_pg_op1 (svbool_t pg, svuint64_t op2) /* ** u64_x_ptrue_op1: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svuint64_t u64_x_ptrue_op1 (svuint64_t op2) @@ -227,7 +227,7 @@ svuint64_t u64_x_ptrue_op1 (svuint64_t op2) /* ** u64_z_ptrue_op1: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svuint64_t u64_z_ptrue_op1 (svuint64_t op2) @@ -237,7 +237,7 @@ svuint64_t u64_z_ptrue_op1 (svuint64_t op2) /* ** u64_m_ptrue_op1: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svuint64_t u64_m_ptrue_op1 (svuint64_t op2) @@ -247,7 +247,7 @@ svuint64_t u64_m_ptrue_op1 (svuint64_t op2) /* ** u64_x_pg_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svuint64_t u64_x_pg_op2 (svbool_t pg, svuint64_t op1) @@ -257,7 +257,7 @@ svuint64_t u64_x_pg_op2 (svbool_t pg, svuint64_t op1) /* ** u64_z_pg_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svuint64_t u64_z_pg_op2 (svbool_t pg, svuint64_t op1) @@ -267,8 +267,8 @@ svuint64_t u64_z_pg_op2 (svbool_t pg, svuint64_t op1) /* ** u64_m_pg_op2: -** mov (z[0-9]+)\.b, #0 -** udiv (z[0-9]+\.d), p[0-7]/m, \2, \1\.d +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** udiv (z[0-9]+\.d), p[0-7]/m, \2, z\1\.d ** ret */ svuint64_t u64_m_pg_op2 (svbool_t pg, svuint64_t op1) @@ -278,7 +278,7 @@ svuint64_t u64_m_pg_op2 (svbool_t pg, svuint64_t op1) /* ** u64_x_ptrue_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svuint64_t u64_x_ptrue_op2 (svuint64_t op1) @@ -288,7 +288,7 @@ svuint64_t u64_x_ptrue_op2 (svuint64_t op1) /* ** u64_z_ptrue_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svuint64_t u64_z_ptrue_op2 (svuint64_t op1) @@ -298,7 +298,7 @@ svuint64_t u64_z_ptrue_op2 (svuint64_t op1) /* ** u64_m_ptrue_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svuint64_t u64_m_ptrue_op2 (svuint64_t op1) @@ -308,7 +308,7 @@ svuint64_t u64_m_ptrue_op2 (svuint64_t op1) /* ** u64_n_x_pg_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svuint64_t u64_n_x_pg_op2 (svbool_t pg, svuint64_t op1) @@ -318,7 +318,7 @@ svuint64_t u64_n_x_pg_op2 (svbool_t pg, svuint64_t op1) /* ** u64_n_z_pg_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svuint64_t u64_n_z_pg_op2 (svbool_t pg, svuint64_t op1) @@ -328,8 +328,8 @@ svuint64_t u64_n_z_pg_op2 (svbool_t pg, svuint64_t op1) /* ** u64_n_m_pg_op2: -** mov (z[0-9]+)\.b, #0 -** udiv (z[0-9]+\.d), p[0-7]/m, \2, \1\.d +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 +** udiv (z[0-9]+\.d), p[0-7]/m, \2, z\1\.d ** ret */ svuint64_t u64_n_m_pg_op2 (svbool_t pg, svuint64_t op1) @@ -339,7 +339,7 @@ svuint64_t u64_n_m_pg_op2 (svbool_t pg, svuint64_t op1) /* ** u64_n_x_ptrue_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svuint64_t u64_n_x_ptrue_op2 (svuint64_t op1) @@ -349,7 +349,7 @@ svuint64_t u64_n_x_ptrue_op2 (svuint64_t op1) /* ** u64_n_z_ptrue_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svuint64_t u64_n_z_ptrue_op2 (svuint64_t op1) @@ -359,7 +359,7 @@ svuint64_t u64_n_z_ptrue_op2 (svuint64_t op1) /* ** u64_n_m_ptrue_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svuint64_t u64_n_m_ptrue_op2 (svuint64_t op1) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/fold_mul_zero.c b/gcc/testsuite/gcc.target/aarch64/sve/fold_mul_zero.c index a5674fd4c2fc30606684c1c92b823425b4e139fc..abb4917d3f766dfea8a281977d1cc5fee4a0ea3e 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/fold_mul_zero.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/fold_mul_zero.c @@ -5,7 +5,7 @@ /* ** s64_x_pg_op1: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_x_pg_op1 (svbool_t pg, svint64_t op2) @@ -15,7 +15,7 @@ svint64_t s64_x_pg_op1 (svbool_t pg, svint64_t op2) /* ** s64_z_pg_op1: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_z_pg_op1 (svbool_t pg, svint64_t op2) @@ -25,7 +25,7 @@ svint64_t s64_z_pg_op1 (svbool_t pg, svint64_t op2) /* ** s64_m_pg_op1: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_m_pg_op1 (svbool_t pg, svint64_t op2) @@ -35,7 +35,7 @@ svint64_t s64_m_pg_op1 (svbool_t pg, svint64_t op2) /* ** s64_x_ptrue_op1: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_x_ptrue_op1 (svint64_t op2) @@ -45,7 +45,7 @@ svint64_t s64_x_ptrue_op1 (svint64_t op2) /* ** s64_z_ptrue_op1: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_z_ptrue_op1 (svint64_t op2) @@ -55,7 +55,7 @@ svint64_t s64_z_ptrue_op1 (svint64_t op2) /* ** s64_m_ptrue_op1: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_m_ptrue_op1 (svint64_t op2) @@ -65,7 +65,7 @@ svint64_t s64_m_ptrue_op1 (svint64_t op2) /* ** s64_x_pg_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_x_pg_op2 (svbool_t pg, svint64_t op1) @@ -75,7 +75,7 @@ svint64_t s64_x_pg_op2 (svbool_t pg, svint64_t op1) /* ** s64_z_pg_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_z_pg_op2 (svbool_t pg, svint64_t op1) @@ -95,7 +95,7 @@ svint64_t s64_m_pg_op2 (svbool_t pg, svint64_t op1) /* ** s64_x_ptrue_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_x_ptrue_op2 (svint64_t op1) @@ -105,7 +105,7 @@ svint64_t s64_x_ptrue_op2 (svint64_t op1) /* ** s64_z_ptrue_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_z_ptrue_op2 (svint64_t op1) @@ -115,7 +115,7 @@ svint64_t s64_z_ptrue_op2 (svint64_t op1) /* ** s64_m_ptrue_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_m_ptrue_op2 (svint64_t op1) @@ -125,7 +125,7 @@ svint64_t s64_m_ptrue_op2 (svint64_t op1) /* ** s64_n_x_pg_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_n_x_pg_op2 (svbool_t pg, svint64_t op1) @@ -135,7 +135,7 @@ svint64_t s64_n_x_pg_op2 (svbool_t pg, svint64_t op1) /* ** s64_n_z_pg_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_n_z_pg_op2 (svbool_t pg, svint64_t op1) @@ -155,7 +155,7 @@ svint64_t s64_n_m_pg_op2 (svbool_t pg, svint64_t op1) /* ** s64_n_x_ptrue_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_n_x_ptrue_op2 (svint64_t op1) @@ -165,7 +165,7 @@ svint64_t s64_n_x_ptrue_op2 (svint64_t op1) /* ** s64_n_z_ptrue_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_n_z_ptrue_op2 (svint64_t op1) @@ -175,7 +175,7 @@ svint64_t s64_n_z_ptrue_op2 (svint64_t op1) /* ** s64_n_m_ptrue_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svint64_t s64_n_m_ptrue_op2 (svint64_t op1) @@ -185,7 +185,7 @@ svint64_t s64_n_m_ptrue_op2 (svint64_t op1) /* ** u64_x_pg_op1: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svuint64_t u64_x_pg_op1 (svbool_t pg, svuint64_t op2) @@ -195,7 +195,7 @@ svuint64_t u64_x_pg_op1 (svbool_t pg, svuint64_t op2) /* ** u64_z_pg_op1: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svuint64_t u64_z_pg_op1 (svbool_t pg, svuint64_t op2) @@ -205,7 +205,7 @@ svuint64_t u64_z_pg_op1 (svbool_t pg, svuint64_t op2) /* ** u64_m_pg_op1: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svuint64_t u64_m_pg_op1 (svbool_t pg, svuint64_t op2) @@ -215,7 +215,7 @@ svuint64_t u64_m_pg_op1 (svbool_t pg, svuint64_t op2) /* ** u64_x_ptrue_op1: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svuint64_t u64_x_ptrue_op1 (svuint64_t op2) @@ -225,7 +225,7 @@ svuint64_t u64_x_ptrue_op1 (svuint64_t op2) /* ** u64_z_ptrue_op1: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svuint64_t u64_z_ptrue_op1 (svuint64_t op2) @@ -235,7 +235,7 @@ svuint64_t u64_z_ptrue_op1 (svuint64_t op2) /* ** u64_m_ptrue_op1: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svuint64_t u64_m_ptrue_op1 (svuint64_t op2) @@ -245,7 +245,7 @@ svuint64_t u64_m_ptrue_op1 (svuint64_t op2) /* ** u64_x_pg_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svuint64_t u64_x_pg_op2 (svbool_t pg, svuint64_t op1) @@ -255,7 +255,7 @@ svuint64_t u64_x_pg_op2 (svbool_t pg, svuint64_t op1) /* ** u64_z_pg_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svuint64_t u64_z_pg_op2 (svbool_t pg, svuint64_t op1) @@ -275,7 +275,7 @@ svuint64_t u64_m_pg_op2 (svbool_t pg, svuint64_t op1) /* ** u64_x_ptrue_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svuint64_t u64_x_ptrue_op2 (svuint64_t op1) @@ -285,7 +285,7 @@ svuint64_t u64_x_ptrue_op2 (svuint64_t op1) /* ** u64_z_ptrue_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svuint64_t u64_z_ptrue_op2 (svuint64_t op1) @@ -295,7 +295,7 @@ svuint64_t u64_z_ptrue_op2 (svuint64_t op1) /* ** u64_m_ptrue_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svuint64_t u64_m_ptrue_op2 (svuint64_t op1) @@ -305,7 +305,7 @@ svuint64_t u64_m_ptrue_op2 (svuint64_t op1) /* ** u64_n_x_pg_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svuint64_t u64_n_x_pg_op2 (svbool_t pg, svuint64_t op1) @@ -315,7 +315,7 @@ svuint64_t u64_n_x_pg_op2 (svbool_t pg, svuint64_t op1) /* ** u64_n_z_pg_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svuint64_t u64_n_z_pg_op2 (svbool_t pg, svuint64_t op1) @@ -335,7 +335,7 @@ svuint64_t u64_n_m_pg_op2 (svbool_t pg, svuint64_t op1) /* ** u64_n_x_ptrue_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svuint64_t u64_n_x_ptrue_op2 (svuint64_t op1) @@ -345,7 +345,7 @@ svuint64_t u64_n_x_ptrue_op2 (svuint64_t op1) /* ** u64_n_z_ptrue_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svuint64_t u64_n_z_ptrue_op2 (svuint64_t op1) @@ -355,7 +355,7 @@ svuint64_t u64_n_z_ptrue_op2 (svuint64_t op1) /* ** u64_n_m_ptrue_op2: -** mov z[0-9]+\.b, #0 +** mov(?:i\td|\tz)([0-9]+)(?:\.[bhsd])?, #0 ** ret */ svuint64_t u64_n_m_ptrue_op2 (svuint64_t op1) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_2.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_2.c index 3ad4454f8b125beb4bcfd18f25c82d47662b8159..6cc1be01c9f39a24e1d132a58e829a6f2fe1ee17 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_2.c @@ -55,7 +55,7 @@ caller_int (int8_t *x0, int16_t *x1, int32_t *x2, int64_t *x3) svptrue_pat_b32 (SV_VL3)); } -/* { dg-final { scan-assembler {\tmov\tz0\.b, #0\n} } } */ +/* { dg-final { scan-assembler {\tmov(\tz0\.b|i\td0), #0\n} } } */ /* { dg-final { scan-assembler {\tmov\tz1\.h, #1\n} } } */ /* { dg-final { scan-assembler {\tmov\tz2\.s, #2\n} } } */ /* { dg-final { scan-assembler {\tmov\tz3\.d, #3\n} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_3.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_3.c index 56896c93b527dd4b3eeb11de02cc78522704e648..86d820415fdd0a7b6e100b8bb4e64a06d2881734 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_3.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_3.c @@ -55,7 +55,7 @@ caller_uint (uint8_t *x0, uint16_t *x1, uint32_t *x2, uint64_t *x3) svptrue_pat_b32 (SV_VL3)); } -/* { dg-final { scan-assembler {\tmov\tz0\.b, #0\n} } } */ +/* { dg-final { scan-assembler {\tmov(\tz0\.b|i\td0), #0\n} } } */ /* { dg-final { scan-assembler {\tmov\tz1\.h, #1\n} } } */ /* { dg-final { scan-assembler {\tmov\tz2\.s, #2\n} } } */ /* { dg-final { scan-assembler {\tmov\tz3\.d, #3\n} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_4.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_4.c index 7213c8695c15db091acc583dffef8c6d76c33c33..5b6120d6f41b71c4936c7bbf48622568cf8ad4f9 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_4.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_4.c @@ -55,7 +55,7 @@ caller_float (float16_t *x0, float16_t *x1, float32_t *x2, float64_t *x3) svptrue_pat_b32 (SV_VL3)); } -/* { dg-final { scan-assembler {\tmov\tz0\.[bhsd], #0\n} } } */ +/* { dg-final { scan-assembler {\tmov(\tz0\.[bhsd]|i\td0), #0\n} } } */ /* { dg-final { scan-assembler {\tfmov\tz1\.h, #1\.0} } } */ /* { dg-final { scan-assembler {\tfmov\tz2\.s, #2\.0} } } */ /* { dg-final { scan-assembler {\tfmov\tz3\.d, #3\.0} } } */ diff --git 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server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Hi All, This patch extends our immediate SIMD generation cases to support generating integer immediates using floating point operation if the integer immediate maps to an exact FP value. As an example: uint32x4_t f1() { return vdupq_n_u32(0x3f800000); } currently generates: f1: adrp x0, .LC0 ldr q0, [x0, #:lo12:.LC0] ret i.e. a load, but with this change: f1: fmov v0.4s, 1.0e+0 ret Such immediates are common in e.g. our Math routines in glibc because they are created to extract or mark part of an FP immediate as masks. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master? Thanks, Tamar gcc/ChangeLog: gcc/ChangeLog: * config/aarch64/aarch64.cc (aarch64_sve_valid_immediate, aarch64_simd_valid_immediate): Refactor accepting modes and values. (aarch64_float_const_representable_p): Refactor and extract FP checks into ... (aarch64_real_float_const_representable_p): ...This. (aarch64_advsimd_valid_immediate): Use it. gcc/testsuite/ChangeLog: * gcc.target/aarch64/const_create_using_fmov.c: New test. --- -- diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 102680a0efca1ce928e6945033c01cfb68a65152..9142a1eb319c9d596eaa8ab723c5abea60818438 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -22895,19 +22895,19 @@ aarch64_advsimd_valid_immediate_hs (unsigned int val32, return false; } -/* Return true if replicating VAL64 is a valid immediate for the +/* Return true if replicating VAL64 with mode MODE is a valid immediate for the Advanced SIMD operation described by WHICH. If INFO is nonnull, use it to describe valid immediates. */ static bool aarch64_advsimd_valid_immediate (unsigned HOST_WIDE_INT val64, + scalar_int_mode mode, simd_immediate_info *info, enum simd_immediate_check which) { unsigned int val32 = val64 & 0xffffffff; - unsigned int val16 = val64 & 0xffff; unsigned int val8 = val64 & 0xff; - if (val32 == (val64 >> 32)) + if (mode != DImode) { if ((which & AARCH64_CHECK_ORR) != 0 && aarch64_advsimd_valid_immediate_hs (val32, info, which, @@ -22919,10 +22919,9 @@ aarch64_advsimd_valid_immediate (unsigned HOST_WIDE_INT val64, simd_immediate_info::MVN)) return true; + /* Try using a replicated byte. */ - if (which == AARCH64_CHECK_MOV - && val16 == (val32 >> 16) - && val8 == (val16 >> 8)) + if (which == AARCH64_CHECK_MOV && mode == QImode) { if (info) *info = simd_immediate_info (QImode, val8); @@ -22950,28 +22949,14 @@ aarch64_advsimd_valid_immediate (unsigned HOST_WIDE_INT val64, return false; } -/* Return true if replicating VAL64 gives a valid immediate for an SVE MOV +/* Return true if replicating IVAL with MODE gives a valid immediate for an SVE MOV instruction. If INFO is nonnull, use it to describe valid immediates. */ static bool -aarch64_sve_valid_immediate (unsigned HOST_WIDE_INT val64, +aarch64_sve_valid_immediate (unsigned HOST_WIDE_INT ival, scalar_int_mode mode, simd_immediate_info *info) { - scalar_int_mode mode = DImode; - unsigned int val32 = val64 & 0xffffffff; - if (val32 == (val64 >> 32)) - { - mode = SImode; - unsigned int val16 = val32 & 0xffff; - if (val16 == (val32 >> 16)) - { - mode = HImode; - unsigned int val8 = val16 & 0xff; - if (val8 == (val16 >> 8)) - mode = QImode; - } - } - HOST_WIDE_INT val = trunc_int_for_mode (val64, mode); + HOST_WIDE_INT val = trunc_int_for_mode (ival, mode); if (IN_RANGE (val, -0x80, 0x7f)) { /* DUP with no shift. */ @@ -22986,7 +22971,7 @@ aarch64_sve_valid_immediate (unsigned HOST_WIDE_INT val64, *info = simd_immediate_info (mode, val); return true; } - if (aarch64_bitmask_imm (val64, mode)) + if (aarch64_bitmask_imm (ival, mode)) { /* DUPM. */ if (info) @@ -23067,6 +23052,91 @@ aarch64_sve_pred_valid_immediate (rtx x, simd_immediate_info *info) return false; } +/* We can only represent floating point constants which will fit in + "quarter-precision" values. These values are characterised by + a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given + by: + + (-1)^s * (n/16) * 2^r + + Where: + 's' is the sign bit. + 'n' is an integer in the range 16 <= n <= 31. + 'r' is an integer in the range -3 <= r <= 4. + + Return true iff R represents a vale encodable into an AArch64 floating point + move instruction as an immediate. Othewise false. */ + +static bool +aarch64_real_float_const_representable_p (REAL_VALUE_TYPE r) +{ + /* This represents our current view of how many bits + make up the mantissa. */ + int point_pos = 2 * HOST_BITS_PER_WIDE_INT - 1; + int exponent; + unsigned HOST_WIDE_INT mantissa, mask; + REAL_VALUE_TYPE m; + bool fail = false; + + /* We cannot represent infinities, NaNs or +/-zero. We won't + know if we have +zero until we analyse the mantissa, but we + can reject the other invalid values. */ + if (REAL_VALUE_ISINF (r) || REAL_VALUE_ISNAN (r) + || REAL_VALUE_MINUS_ZERO (r)) + return false; + + /* Extract exponent. */ + r = real_value_abs (&r); + exponent = REAL_EXP (&r); + + /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the + highest (sign) bit, with a fixed binary point at bit point_pos. + m1 holds the low part of the mantissa, m2 the high part. + WARNING: If we ever have a representation using more than 2 * H_W_I - 1 + bits for the mantissa, this can fail (low bits will be lost). */ + real_ldexp (&m, &r, point_pos - exponent); + wide_int w = real_to_integer (&m, &fail, HOST_BITS_PER_WIDE_INT * 2); + + /* If the low part of the mantissa has bits set we cannot represent + the value. */ + if (fail || w.ulow () != 0) + return false; + + /* We have rejected the lower HOST_WIDE_INT, so update our + understanding of how many bits lie in the mantissa and + look only at the high HOST_WIDE_INT. */ + mantissa = w.elt (1); + point_pos -= HOST_BITS_PER_WIDE_INT; + + /* We can only represent values with a mantissa of the form 1.xxxx. */ + mask = ((unsigned HOST_WIDE_INT)1 << (point_pos - 5)) - 1; + if ((mantissa & mask) != 0) + return false; + + /* Having filtered unrepresentable values, we may now remove all + but the highest 5 bits. */ + mantissa >>= point_pos - 5; + + /* We cannot represent the value 0.0, so reject it. This is handled + elsewhere. */ + if (mantissa == 0) + return false; + + /* Then, as bit 4 is always set, we can mask it off, leaving + the mantissa in the range [0, 15]. */ + mantissa &= ~(1 << 4); + gcc_assert (mantissa <= 15); + + /* GCC internally does not use IEEE754-like encoding (where normalized + significands are in the range [1, 2). GCC uses [0.5, 1) (see real.cc). + Our mantissa values are shifted 4 places to the left relative to + normalized IEEE754 so we must modify the exponent returned by REAL_EXP + by 5 places to correct for GCC's representation. */ + exponent = 5 - exponent; + + return (exponent >= 0 && exponent <= 7); +} + /* Return true if OP is a valid SIMD immediate for the operation described by WHICH. If INFO is nonnull, use it to describe valid immediates. */ @@ -23120,20 +23190,6 @@ aarch64_simd_valid_immediate (rtx op, simd_immediate_info *info, else return false; - scalar_float_mode elt_float_mode; - if (n_elts == 1 - && is_a (elt_mode, &elt_float_mode)) - { - rtx elt = CONST_VECTOR_ENCODED_ELT (op, 0); - if (aarch64_float_const_zero_rtx_p (elt) - || aarch64_float_const_representable_p (elt)) - { - if (info) - *info = simd_immediate_info (elt_float_mode, elt); - return true; - } - } - /* If all elements in an SVE vector have the same value, we have a free choice between using the element mode and using the container mode. Using the element mode means that unused parts of the vector are @@ -23195,10 +23251,57 @@ aarch64_simd_valid_immediate (rtx op, simd_immediate_info *info, val64 |= ((unsigned HOST_WIDE_INT) bytes[i % nbytes] << (i * BITS_PER_UNIT)); + /* Try encoding the integer immediate as a floating point value if it's an exact + value. */ + scalar_float_mode fmode = DFmode; + scalar_int_mode imode = DImode; + unsigned HOST_WIDE_INT ival = val64; + unsigned int val32 = val64 & 0xffffffff; + if (val32 == (val64 >> 32)) + { + fmode = SFmode; + imode = SImode; + ival = val32; + unsigned int val16 = val32 & 0xffff; + if (val16 == (val32 >> 16)) + { + fmode = HFmode; + imode = HImode; + ival = val16; + unsigned int val8 = val16 & 0xff; + if (val8 == (val16 >> 8)) + { + imode = QImode; + ival = val8; + } + } + } + + if (which == AARCH64_CHECK_MOV + && imode != QImode + && (imode != HImode || TARGET_FP_F16INST)) + { + long int as_long_ints[2]; + as_long_ints[0] = ival & 0xFFFFFFFF; + as_long_ints[1] = (ival >> 32) & 0xFFFFFFFF; + + REAL_VALUE_TYPE r; + real_from_target (&r, as_long_ints, fmode); + if (aarch64_real_float_const_representable_p (r)) + { + if (info) + { + rtx float_val = const_double_from_real_value (r, fmode); + *info = simd_immediate_info (fmode, float_val); + } + return true; + } + } + if (vec_flags & VEC_SVE_DATA) - return aarch64_sve_valid_immediate (val64, info); + return aarch64_sve_valid_immediate (ival, imode, info); else - return aarch64_advsimd_valid_immediate (val64, info, which); + return aarch64_advsimd_valid_immediate (val64, imode, info, which); } /* Check whether X is a VEC_SERIES-like constant that starts at 0 and @@ -25201,106 +25304,32 @@ aarch64_c_mode_for_suffix (char suffix) return VOIDmode; } -/* We can only represent floating point constants which will fit in - "quarter-precision" values. These values are characterised by - a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given - by: - - (-1)^s * (n/16) * 2^r - - Where: - 's' is the sign bit. - 'n' is an integer in the range 16 <= n <= 31. - 'r' is an integer in the range -3 <= r <= 4. */ - -/* Return true iff X can be represented by a quarter-precision +/* Return true iff X with mode MODE can be represented by a quarter-precision floating point immediate operand X. Note, we cannot represent 0.0. */ + bool aarch64_float_const_representable_p (rtx x) { - /* This represents our current view of how many bits - make up the mantissa. */ - int point_pos = 2 * HOST_BITS_PER_WIDE_INT - 1; - int exponent; - unsigned HOST_WIDE_INT mantissa, mask; - REAL_VALUE_TYPE r, m; - bool fail; - x = unwrap_const_vec_duplicate (x); + machine_mode mode = GET_MODE (x); if (!CONST_DOUBLE_P (x)) return false; - if (GET_MODE (x) == VOIDmode - || (GET_MODE (x) == HFmode && !TARGET_FP_F16INST)) + if (mode == HFmode && !TARGET_FP_F16INST) return false; - r = *CONST_DOUBLE_REAL_VALUE (x); - - /* We cannot represent infinities, NaNs or +/-zero. We won't - know if we have +zero until we analyse the mantissa, but we - can reject the other invalid values. */ - if (REAL_VALUE_ISINF (r) || REAL_VALUE_ISNAN (r) - || REAL_VALUE_MINUS_ZERO (r)) - return false; + REAL_VALUE_TYPE r = *CONST_DOUBLE_REAL_VALUE (x); /* For BFmode, only handle 0.0. */ - if (GET_MODE (x) == BFmode) + if (mode == BFmode) return real_iszero (&r, false); - /* Extract exponent. */ - r = real_value_abs (&r); - exponent = REAL_EXP (&r); - - /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the - highest (sign) bit, with a fixed binary point at bit point_pos. - m1 holds the low part of the mantissa, m2 the high part. - WARNING: If we ever have a representation using more than 2 * H_W_I - 1 - bits for the mantissa, this can fail (low bits will be lost). */ - real_ldexp (&m, &r, point_pos - exponent); - wide_int w = real_to_integer (&m, &fail, HOST_BITS_PER_WIDE_INT * 2); - - /* If the low part of the mantissa has bits set we cannot represent - the value. */ - if (w.ulow () != 0) - return false; - /* We have rejected the lower HOST_WIDE_INT, so update our - understanding of how many bits lie in the mantissa and - look only at the high HOST_WIDE_INT. */ - mantissa = w.elt (1); - point_pos -= HOST_BITS_PER_WIDE_INT; - - /* We can only represent values with a mantissa of the form 1.xxxx. */ - mask = ((unsigned HOST_WIDE_INT)1 << (point_pos - 5)) - 1; - if ((mantissa & mask) != 0) - return false; - - /* Having filtered unrepresentable values, we may now remove all - but the highest 5 bits. */ - mantissa >>= point_pos - 5; - - /* We cannot represent the value 0.0, so reject it. This is handled - elsewhere. */ - if (mantissa == 0) - return false; - - /* Then, as bit 4 is always set, we can mask it off, leaving - the mantissa in the range [0, 15]. */ - mantissa &= ~(1 << 4); - gcc_assert (mantissa <= 15); - - /* GCC internally does not use IEEE754-like encoding (where normalized - significands are in the range [1, 2). GCC uses [0.5, 1) (see real.cc). - Our mantissa values are shifted 4 places to the left relative to - normalized IEEE754 so we must modify the exponent returned by REAL_EXP - by 5 places to correct for GCC's representation. */ - exponent = 5 - exponent; - - return (exponent >= 0 && exponent <= 7); + return aarch64_real_float_const_representable_p (r); } -/* Returns the string with the instruction for AdvSIMD MOVI, MVNI, ORR or BIC - immediate with a CONST_VECTOR of MODE and WIDTH. WHICH selects whether to - output MOVI/MVNI, ORR or BIC immediate. */ +/* Returns the string with the instruction for AdvSIMD MOVI, MVNI, ORR, BIC or + FMOV immediate with a CONST_VECTOR of MODE and WIDTH. WHICH selects whether + to output MOVI/MVNI, ORR or BIC immediate. */ char* aarch64_output_simd_mov_immediate (rtx const_vector, unsigned width, enum simd_immediate_check which) diff --git a/gcc/testsuite/gcc.target/aarch64/const_create_using_fmov.c b/gcc/testsuite/gcc.target/aarch64/const_create_using_fmov.c new file mode 100644 index 0000000000000000000000000000000000000000..e080afed8aa3578660027979335bfc859ca6bc91 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/const_create_using_fmov.c @@ -0,0 +1,87 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv9-a -Ofast" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#include + +/* +** g: +** fmov v0\.4s, 1\.0e\+0 +** ret +*/ +float32x4_t g(){ + return vdupq_n_f32(1); +} + +/* +** h: +** fmov v0\.4s, 1\.0e\+0 +** ret +*/ +uint32x4_t h() { + return vreinterpretq_u32_f32(g()); +} + +/* +** f1: +** fmov v0\.4s, 1\.0e\+0 +** ret +*/ +uint32x4_t f1() { + return vdupq_n_u32(0x3f800000); +} + +/* +** f2: +** fmov v0\.4s, 1\.5e\+0 +** ret +*/ +uint32x4_t f2() { + return vdupq_n_u32(0x3FC00000); +} + +/* +** f3: +** fmov v0\.4s, 1\.25e\+0 +** ret +*/ +uint32x4_t f3() { + return vdupq_n_u32(0x3FA00000); +} + +/* +** f4: +** fmov v0\.2d, 1\.0e\+0 +** ret +*/ +uint64x2_t f4() { + return vdupq_n_u64(0x3FF0000000000000); +} + +/* +** fn4: +** fmov v0\.2d, -1\.0e\+0 +** ret +*/ +uint64x2_t fn4() { + return vdupq_n_u64(0xBFF0000000000000); +} + +/* +** f5: +** fmov v0\.8h, 1\.5e\+0 +** ret +*/ +uint16x8_t f5() { + return vdupq_n_u16(0x3E00); +} + +/* +** f6: +** adrp x0, \.LC0 +** ldr q0, \[x0, #:lo12:\.LC0\] +** ret +*/ +uint32x4_t f6() { + return vdupq_n_u32(0x4f800000); +} From patchwork Mon Oct 14 10:54:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tamar Christina X-Patchwork-Id: 1996805 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256 header.s=selector1 header.b=WiI0Ip0n; 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SIMD fmov 0 to clear SVE registers when not in SVE streaming mode. As the Neoverse Software Optimization guides indicate SVE mov #0 is not a zero cost move. When In streaming mode we continue to use SVE's mov to clear the registers. Tests have already been updated. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master? Thanks, Tamar gcc/ChangeLog: * config/aarch64/aarch64.cc (aarch64_output_sve_mov_immediate): Use fmov for SVE zeros. --- -- diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 9142a1eb319c9d596eaa8ab723c5abea60818438..a9d8f9fbeddd0f4269c1671f8d1b504c68ef3910 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -25515,8 +25515,11 @@ aarch64_output_sve_mov_immediate (rtx const_vector) } } - snprintf (templ, sizeof (templ), "mov\t%%0.%c, #" HOST_WIDE_INT_PRINT_DEC, - element_char, INTVAL (info.u.mov.value)); + if (info.u.mov.value == const0_rtx && TARGET_NON_STREAMING) + snprintf (templ, sizeof (templ), "movi\t%%d0, #0"); + else + snprintf (templ, sizeof (templ), "mov\t%%0.%c, #" HOST_WIDE_INT_PRINT_DEC, + element_char, INTVAL (info.u.mov.value)); return templ; }