From patchwork Mon Oct 14 10:18:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yangyu Chen X-Patchwork-Id: 1996778 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4XRtVv6VRCz1xsc for ; Mon, 14 Oct 2024 21:19:00 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id EBF67385AC1B for ; Mon, 14 Oct 2024 10:18:53 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) by sourceware.org (Postfix) with ESMTPS id DFDDA3857000 for ; Mon, 14 Oct 2024 10:18:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DFDDA3857000 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=isrc.iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=isrc.iscas.ac.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org DFDDA3857000 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=159.226.251.84 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1728901112; cv=none; b=acnvZ5sMIn/ehk5m/hLben69m+9xb4BlTglXjdU+LhhlQGPrIlMtL2TOGfUgPRSdhcIV2FCklUvaeJBpQUbwFOxqIxd755e7AszsCqe0HHEmYEijtmXoiUQ63UlPKE/MSX2QzGLUa2Jwyw05AEM6Ym3hiAvLJOVsUQe/Wqfi0yo= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1728901112; c=relaxed/simple; bh=pK3Olo9XQe519qpQ4fwsIGkc/pIeKUv32hi6lih5YjY=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=UN1dEAKEiX9I+fv1EUGDoOhjLLbUMwArsKh3GXy+jPbmCDoR/dA5uFXPPohU5USOV/JqcMcGXeTRdo/G/7GIdJLcfuHX7fyzn42+2cgqKYVM+tdJ6dBTvc6WQIedC/m6hgVgvBH1WrX+wd8lCxnnepUJbdWDGTz5v6OS/W7K1I0= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from cyy-pc.lan (unknown [120.41.211.70]) by APP-05 (Coremail) with SMTP id zQCowABnTmXg7wxn7ixeBw--.40789S2; Mon, 14 Oct 2024 18:18:16 +0800 (CST) From: Yangyu Chen To: gcc-patches@gcc.gnu.org Cc: Kito Cheng , Palmer Dabbelt , Jiawei , Jeff Law , Yangyu Chen Subject: [PATCH] RISC-V: Fix feature_bits.c failed to compile on non-Linux targets Date: Mon, 14 Oct 2024 18:18:07 +0800 Message-ID: <20241014101807.2800011-1-chenyangyu@isrc.iscas.ac.cn> X-Mailer: git-send-email 2.45.2 MIME-Version: 1.0 X-CM-TRANSID: zQCowABnTmXg7wxn7ixeBw--.40789S2 X-Coremail-Antispam: 1UD129KBjvJXoWxGF4UCF4fArWrWrW5uFy3urg_yoW5GrW3p3 9av34jyr18Jr1xuas3try8Xw4rJr9Yka1fAr4qk345CF1ayrW3WrnrKas5Z34DArW5Zr43 uF4UKr1UC39rAaDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUkG14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26r1j6r1xM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r1j 6r4UM28EF7xvwVC2z280aVAFwI0_Jr0_Gr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r4j6r 4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0 I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r 4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY1x0262kKe7AKxVWU AVWUtwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14 v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw1lIxkG c2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI 0_Jr0_Gr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4U MIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUSNtxUUU UU= X-Originating-IP: [120.41.211.70] X-CM-SenderInfo: xfkh055dqj53w6lv2u4olvutnvoduhdfq/ X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org The feature_bits.c file failed to compile on non-Linux targets because we forgot to remove the __riscv_vendor_feature_bits.vendorID set when target is not Linux. This commit fixed this and also has several improvements including: - Initialize all data to zero when syscall is not supported. - Add detailed comments on processing implied extensions. Fixes: ca44eb7f6a33 ("RISC-V: Implement __init_riscv_feature_bits, __riscv_feature_bits, and __riscv_vendor_feature_bits") libgcc/ChangeLog: * config/riscv/feature_bits.c (__init_riscv_features_bits_linux): Remove __riscv_vendor_feature_bits.vendorID set when target is not Linux, and initialize all data to zero when syscall is not supported. Signed-off-by: Yangyu Chen --- libgcc/config/riscv/feature_bits.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/libgcc/config/riscv/feature_bits.c b/libgcc/config/riscv/feature_bits.c index 9bdbc466fee..44f8eeee4e7 100644 --- a/libgcc/config/riscv/feature_bits.c +++ b/libgcc/config/riscv/feature_bits.c @@ -262,7 +262,15 @@ static void __init_riscv_features_bits_linux () 0, 0); if (res) - return; + { + /* When syscall is not supported, just initialize that into all zeros. */ + __riscv_feature_bits.length = 0; + __riscv_vendor_feature_bits.length = 0; + __riscv_cpu_model.mvendorid = 0; + __riscv_cpu_model.marchid = 0; + __riscv_cpu_model.mimpid = 0; + return; + } const struct riscv_hwprobe hwprobe_mvendorid = hwprobes[0]; @@ -290,9 +298,12 @@ static void __init_riscv_features_bits_linux () } const struct riscv_hwprobe hwprobe_ima_ext = hwprobes[4]; - /* Every time we add new extensions, we should check if previous extensions - imply the new extension and set the corresponding bit. */ + imply the new extension and set the corresponding bit. + We don't need to handle cases where: + 1. The new extension implies a previous extension (e.g., Zve32f -> F). + 2. The extensions imply some other extensions appear in the same release + version of Linux Kernel (e.g., Zbc - > Zbkc). */ if (hwprobe_ima_ext.value & RISCV_HWPROBE_IMA_FD) { @@ -397,7 +408,7 @@ __init_riscv_feature_bits () #ifdef __linux __init_riscv_features_bits_linux (); #else - /* Unsupported, just initlizaed that into all zeros. */ + /* Unsupported, just initialize that into all zeros. */ __riscv_feature_bits.length = 0; __riscv_vendor_feature_bits.length = 0; __riscv_cpu_model.mvendorid = 0;