From patchwork Fri Sep 20 07:02:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1987671 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=kZDXICov; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X93JQ28MFz1xrD for ; Fri, 20 Sep 2024 17:03:34 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 38F7D89348; Fri, 20 Sep 2024 09:03:21 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="kZDXICov"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 0F5DF89335; Fri, 20 Sep 2024 09:03:20 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, SPF_HELO_NONE,SPF_PASS,UPPERCASE_50_75 autolearn=no autolearn_force=no version=3.4.2 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 2F2DD8933C for ; Fri, 20 Sep 2024 09:03:16 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=tien.fong.chee@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1726815797; x=1758351797; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=V0K+8DKMJWLz1B5xkysKlVH5C0vxTgThFS4bCGiyxiE=; b=kZDXICovyb/+GOnu9RvztdgynC543fjiW+FDJ65pEx6pWEcfut0/a5Wg ri+pV5zwZ5nteMFuEVQf342/YphKkUZvtCuSVjZF0148wpiFar+oLxypv BBBjwMnqVOCVGaDyQjetG1FjK+KYqPQVC+3yrh57qjdQsN7An5oKmbq7H 0mf/3eKTDhiB/PoGjeDfGDaCUY6PIVINp+ZLhH8cNl4/hIfVsiyENoWTD +9opfesCMAtULyUaF40aNLarIWfagSlQ+Xh28mY8BsHRT0D4ZP4UNWwCO RvDfvJ5maYyMlAe71XWbV5KF5bZSm00DPOUqK8K8PfXHeVHTiUCZmpJJI A==; X-CSE-ConnectionGUID: vzEZ/NLxRyurppJu9vNUeQ== X-CSE-MsgGUID: 6Fv1beYuTSO/vJ8wCkH43A== X-IronPort-AV: E=McAfee;i="6700,10204,11200"; a="25961018" X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="25961018" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2024 00:03:15 -0700 X-CSE-ConnectionGUID: 5U682xAvTKOBwgk9ejYMSw== X-CSE-MsgGUID: +w/oDUxzT4mWHgnDk/ik3w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="70235015" Received: from pglc00502.png.intel.com ([10.221.239.194]) by orviesa009.jf.intel.com with ESMTP; 20 Sep 2024 00:03:13 -0700 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Cc: Marek Vasut , Simon Goldschmidt , Meng Tingting , Yuslaimi Alif Zakuan , Hea Kok Kiang , Tien Fong Chee Subject: [PATCH v1 01/20] arm: socfpga: agilex5: Add new system manager base addresses Date: Fri, 20 Sep 2024 15:02:23 +0800 Message-Id: <20240920070242.20884-2-tien.fong.chee@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240920070242.20884-1-tien.fong.chee@intel.com> References: <20240920070242.20884-1-tien.fong.chee@intel.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Tien Fong Chee Initial creation of new system manager base addresses for Agilex5. Signed-off-by: Tien Fong Chee --- .../include/mach/system_manager_soc64.h | 129 +++++++++++------- 1 file changed, 83 insertions(+), 46 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index a8009664fee..b1ef4a70641 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2019-2021 Intel Corporation + * Copyright (C) 2019-2024 Intel Corporation */ #ifndef _SYSTEM_MANAGER_SOC64_H_ @@ -11,22 +11,43 @@ void sysmgr_pinmux_init(void); void populate_sysmgr_fpgaintf_module(void); void populate_sysmgr_pinmux(void); -#define SYSMGR_SOC64_WDDBG 0x08 -#define SYSMGR_SOC64_DMA 0x20 -#define SYSMGR_SOC64_DMA_PERIPH 0x24 -#define SYSMGR_SOC64_SDMMC 0x28 -#define SYSMGR_SOC64_SDMMC_L3MASTER 0x2c -#define SYSMGR_SOC64_EMAC_GLOBAL 0x40 -#define SYSMGR_SOC64_EMAC0 0x44 -#define SYSMGR_SOC64_EMAC1 0x48 -#define SYSMGR_SOC64_EMAC2 0x4c -#define SYSMGR_SOC64_EMAC0_ACE 0x50 -#define SYSMGR_SOC64_EMAC1_ACE 0x54 -#define SYSMGR_SOC64_EMAC2_ACE 0x58 +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define SYSMGR_SOC64_SILICONID_1 0x00 +#define SYSMGR_SOC64_SILICONID_2 0x04 +#define SYSMGR_SOC64_MPU_STATUS 0x10 +#define SYSMGR_SOC64_COMBOPHY_DFISEL 0xfc +#define SYSMGR_SOC64_COMBOPHY_DFISEL_SDMMC 0x1 +#define SYSMGR_SOC64_NANDGRP_L3MASTER 0x34 +#define SYSMGR_SOC64_USB0_L3MASTER 0x38 +#define SYSMGR_SOC64_USB1_L3MASTER 0x3c +#define SYSMGR_SOC64_DMAC0_L3_MASTER 0x74 +#define SYSMGR_SOC64_ETR_L3_MASTER 0x78 +#define SYSMGR_SOC64_DMAC1_L3_MASTER 0x7C +#define SYSMGR_SOC64_SEC_CTRL_SLT 0x80 +#define SYSMGR_SOC64_OSC_TRIM 0x84 +#define SYSMGR_SOC64_DMAC0_CTRL_STATUS_REG 0x88 +#define SYSMGR_SOC64_DMAC1_CTRL_STATUS_REG 0x8C +#define SYSMGR_SOC64_ECC_INTMASK_VALUE 0x90 +#define SYSMGR_SOC64_ECC_INTMASK_SET 0x94 +#define SYSMGR_SOC64_ECC_INTMASK_CLR 0x98 +#define SYSMGR_SOC64_ECC_INTMASK_SERR 0x9C +#define SYSMGR_SOC64_ECC_INTMASK_DERR 0xA0 +#define SYSMGR_SOC64_MPFE_CONFIG 0x228 +#define SYSMGR_SOC64_BOOT_SCRATCH_POR0 0x258 +#define SYSMGR_SOC64_BOOT_SCRATCH_POR1 0x25C +#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK GENMASK(31, 0) +#define ALT_SYSMGR_SCRATCH_REG_3_DDR_RESET_TYPE_MASK GENMASK(31, 29) +#define ALT_SYSMGR_SCRATCH_REG_3_DDR_RESET_TYPE_SHIFT 29 +#define ALT_SYSMGR_SCRATCH_REG_3_DDR_PORT_INFO_MASK BIT(27) +#define ALT_SYSMGR_SCRATCH_REG_3_DDR_EMIF_INFO_MASK BIT(28) +#define ALT_SYSMGR_SCRATCH_REG_3_DDR_PORT_EMIF_INFO_MASK GENMASK(28, 27) +#define ALT_SYSMGR_SCRATCH_REG_3_DDR_DBE_MASK BIT(1) +#define ALT_SYSMGR_SCRATCH_REG_3_OCRAM_DBE_MASK BIT(0) +#define ALT_SYSMGR_SCRATCH_REG_POR_0_DDR_PROGRESS_MASK BIT(0) +#define ALT_SYSMGR_SCRATCH_REG_POR_1_REVA_WORKAROUND_USER_MODE_MASK BIT(0) +#define ALT_SYSMGR_SCRATCH_REG_POR_1_REVA_WORKAROUND_MASK BIT(1) +#else #define SYSMGR_SOC64_NAND_AXUSER 0x5c -#define SYSMGR_SOC64_FPGAINTF_EN1 0x68 -#define SYSMGR_SOC64_FPGAINTF_EN2 0x6c -#define SYSMGR_SOC64_FPGAINTF_EN3 0x70 #define SYSMGR_SOC64_DMA_L3MASTER 0x74 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) #define SYSMGR_SOC64_DDR_MODE 0xb8 @@ -34,39 +55,56 @@ void populate_sysmgr_pinmux(void); #define SYSMGR_SOC64_HMC_CLK 0xb4 #define SYSMGR_SOC64_IO_PA_CTRL 0xb8 #endif -#define SYSMGR_SOC64_NOC_TIMEOUT 0xc0 -#define SYSMGR_SOC64_NOC_IDLEREQ_SET 0xc4 -#define SYSMGR_SOC64_NOC_IDLEREQ_CLR 0xc8 -#define SYSMGR_SOC64_NOC_IDLEREQ_VAL 0xcc -#define SYSMGR_SOC64_NOC_IDLEACK 0xd0 -#define SYSMGR_SOC64_NOC_IDLESTATUS 0xd4 -#define SYSMGR_SOC64_FPGA2SOC_CTRL 0xd8 -#define SYSMGR_SOC64_FPGA_CONFIG 0xdc #define SYSMGR_SOC64_IOCSRCLK_GATE 0xe0 #define SYSMGR_SOC64_GPO 0xe4 #define SYSMGR_SOC64_GPI 0xe8 #define SYSMGR_SOC64_MPU 0xf0 -/* - * Bits[31:28] reserved for N5X DDR retention, bits[27:0] reserved for SOC 64-bit - * storing qspi ref clock (kHz) - */ -#define SYSMGR_SOC64_BOOT_SCRATCH_COLD0 0x200 -/* store osc1 clock freq */ -#define SYSMGR_SOC64_BOOT_SCRATCH_COLD1 0x204 -/* store fpga clock freq */ -#define SYSMGR_SOC64_BOOT_SCRATCH_COLD2 0x208 -/* reserved for customer use */ -#define SYSMGR_SOC64_BOOT_SCRATCH_COLD3 0x20c -/* store PSCI_CPU_ON value */ -#define SYSMGR_SOC64_BOOT_SCRATCH_COLD4 0x210 -/* store PSCI_CPU_ON value */ -#define SYSMGR_SOC64_BOOT_SCRATCH_COLD5 0x214 -/* store VBAR_EL3 value */ -#define SYSMGR_SOC64_BOOT_SCRATCH_COLD6 0x218 -/* store VBAR_EL3 value */ -#define SYSMGR_SOC64_BOOT_SCRATCH_COLD7 0x21c -#define SYSMGR_SOC64_BOOT_SCRATCH_COLD8 0x220 -#define SYSMGR_SOC64_BOOT_SCRATCH_COLD9 0x224 +#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK GENMASK(27, 0) +#endif /*CONFIG_TARGET_SOCFPGA_AGILEX5*/ + +#define SYSMGR_SOC64_DMA 0x20 +#define SYSMGR_SOC64_DMA_PERIPH 0x24 +#define SYSMGR_SOC64_WDDBG 0x08 +#define SYSMGR_SOC64_SDMMC 0x28 +#define SYSMGR_SOC64_SDMMC_L3MASTER 0x2C +#define SYSMGR_SOC64_FPGAINTF_EN1 0x68 +#define SYSMGR_SOC64_FPGAINTF_EN2 0x6C +#define SYSMGR_SOC64_FPGAINTF_EN3 0x70 +#define SYSMGR_SOC64_NOC_TIMEOUT 0xC0 +#define SYSMGR_SOC64_NOC_IDLEREQ_SET 0xC4 +#define SYSMGR_SOC64_NOC_IDLEREQ_CLR 0xC8 +#define SYSMGR_SOC64_NOC_IDLEREQ_VAL 0xCC +#define SYSMGR_SOC64_NOC_IDLEACK 0xd0 +#define SYSMGR_SOC64_NOC_IDLESTATUS 0xD4 +#define SYSMGR_SOC64_FPGA2SOC_CTRL 0xD8 +#define SYSMGR_SOC64_FPGA_CONFIG 0xDC + +#define SYSMGR_SOC64_TSN_GLOBAL 0x40 +#define SYSMGR_SOC64_TSN_0 0x44 +#define SYSMGR_SOC64_TSN_1 0x48 +#define SYSMGR_SOC64_TSN_2 0x4C +#define SYSMGR_SOC64_TSN_0_ACE 0x50 +#define SYSMGR_SOC64_TSN_1_ACE 0x54 +#define SYSMGR_SOC64_TSN_2_ACE 0x58 +#define SYSMGR_SOC64_EMAC_GLOBAL SYSMGR_SOC64_TSN_GLOBAL +#define SYSMGR_SOC64_EMAC0 SYSMGR_SOC64_TSN_0 +#define SYSMGR_SOC64_EMAC1 SYSMGR_SOC64_TSN_1 +#define SYSMGR_SOC64_EMAC2 SYSMGR_SOC64_TSN_2 +#define SYSMGR_SOC64_EMAC0_ACE SYSMGR_SOC64_TSN_0_ACE +#define SYSMGR_SOC64_EMAC1_ACE SYSMGR_SOC64_TSN_1_ACE +#define SYSMGR_SOC64_EMAC2_ACE SYSMGR_SOC64_TSN_2_ACE + +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD0 0x200 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD1 0x204 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD2 0x208 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD3 0x20C +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD4 0x210 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD5 0x214 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD6 0x218 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD7 0x21C +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD8 0x220 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD9 0x224 + #define SYSMGR_SOC64_PINSEL0 0x1000 #define SYSMGR_SOC64_IOCTRL0 0x1130 #define SYSMGR_SOC64_EMAC0_USEFPGA 0x1300 @@ -97,7 +135,6 @@ void populate_sysmgr_pinmux(void); * Bits[31:28] reserved for DM DDR retention, bits[27:0] reserved for SOC 64-bit * storing qspi ref clock (kHz) */ -#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK GENMASK(27, 0) #define ALT_SYSMGR_SCRATCH_REG_0_DDR_RETENTION_MASK BIT(31) #define ALT_SYSMGR_SCRATCH_REG_0_DDR_SHA_MASK BIT(30) #define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK (BIT(29) | BIT(28)) From patchwork Fri Sep 20 07:02:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1987672 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=Miqp+JY5; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X93Jd5Gw7z1xrD for ; Fri, 20 Sep 2024 17:03:45 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 95F528936B; Fri, 20 Sep 2024 09:03:21 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Miqp+JY5"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id B8FC589348; Fri, 20 Sep 2024 09:03:20 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 38AB489343 for ; Fri, 20 Sep 2024 09:03:17 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=tien.fong.chee@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1726815798; x=1758351798; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=opiSx0UvN3+41iap+8UAIyN3kgExvzrMuL2Ib/uA2T4=; b=Miqp+JY5+D8ihSnPLVgYMGcffu9jAENpNaXcbTK8cFBvr1NrAVvgsr/2 2HjkIlfiomY/TVYkdimZuBzF7AQoQ9ZNx4BMgSbn5lTnTQfvZ11tSbXZ+ 2o9efNATSreii3rXvYymbnZ4o6PjgMj3s4typHMNBWi9tvfkrVoIcER3L VSybCJBtN6dUGDXd3aL27UAaApGIlpGBGZ1CFmvXmKYSbDBY1ig22Behn IU7pV4wVnYvdXaSdylA2cGpU1BW13nuDT5kH/aLddDFtVTc4x9EIvfz6i TK87gg0WJNGliLuMe9Ci+u5QEx6o2/nhBFuCzr+rzu7wj318/w+6zgeSX Q==; X-CSE-ConnectionGUID: NGoPsydWQQizAaqsTPMtOg== X-CSE-MsgGUID: ljiE51OaRa6T89JIiQXGiQ== X-IronPort-AV: E=McAfee;i="6700,10204,11200"; a="25961026" X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="25961026" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2024 00:03:17 -0700 X-CSE-ConnectionGUID: fW2HxW5TScOElIF1rXoRWw== X-CSE-MsgGUID: 8S029NoCSWir72JO9NXsdg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="70235023" Received: from pglc00502.png.intel.com ([10.221.239.194]) by orviesa009.jf.intel.com with ESMTP; 20 Sep 2024 00:03:15 -0700 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Cc: Marek Vasut , Simon Goldschmidt , Meng Tingting , Yuslaimi Alif Zakuan , Hea Kok Kiang , Tien Fong Chee Subject: [PATCH v1 02/20] arm: socfpga: Add support for agilex5 clock manager Date: Fri, 20 Sep 2024 15:02:24 +0800 Message-Id: <20240920070242.20884-3-tien.fong.chee@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240920070242.20884-1-tien.fong.chee@intel.com> References: <20240920070242.20884-1-tien.fong.chee@intel.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Tien Fong Chee Adding mechanism to retrieve base address for Agilex5 Clock Mananger. Signed-off-by: Tien Fong Chee --- arch/arm/mach-socfpga/misc.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 495ba2a0d41..6cf2ee60038 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2012-2017 Altera Corporation + * Copyright (C) 2012-2024 Altera Corporation */ #include @@ -252,15 +252,19 @@ void socfpga_get_managers_addr(void) if (ret) hang(); -#ifdef CONFIG_TARGET_SOCFPGA_AGILEX - ret = socfpga_get_base_addr("intel,agilex-clkmgr", - &socfpga_clkmgr_base); -#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) - ret = socfpga_get_base_addr("intel,n5x-clkmgr", - &socfpga_clkmgr_base); -#else - ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base); -#endif + if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX)) + ret = socfpga_get_base_addr("intel,agilex-clkmgr", + &socfpga_clkmgr_base); + else if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)) + ret = socfpga_get_base_addr("intel,n5x-clkmgr", + &socfpga_clkmgr_base); + else if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)) + ret = socfpga_get_base_addr("intel,agilex5-clkmgr", + &socfpga_clkmgr_base); + else + ret = socfpga_get_base_addr("altr,clk-mgr", + &socfpga_clkmgr_base); + if (ret) hang(); } From patchwork Fri Sep 20 07:02:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1987673 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=cpVic82g; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X93Jw1S83z1xrD for ; Fri, 20 Sep 2024 17:04:00 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id F41878935D; Fri, 20 Sep 2024 09:03:23 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="cpVic82g"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id EB05089357; Fri, 20 Sep 2024 09:03:22 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 8FCA889335 for ; Fri, 20 Sep 2024 09:03:20 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=tien.fong.chee@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1726815801; x=1758351801; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6jEZJdZBfmJahnrvovtMiP40dOZAkk1vqYwRoIie+Yo=; b=cpVic82ggR0ZKde1ny0vAD1Mff/H1kMSOUuPLq/xOhqYQ95stutI9AkS Gpqw9VIrdRBZILGaisbFAh42ZEp9d5AJWhBxN0Yf3V4m0Jo46bVONRpLI XzWM+acDau++iGu1ynhNqIga0j21gK0WN5FcW+znzSn+YYzXiqXXYCcrq 35cQfk/OHKPYoNr6XV2HxLOgIWdR6VYvVqO3uNLjs4bwj95U/cpik1BC0 0oEpZ6tO4NMrThhwDfqIbfvDRhMc9mtivDXDqZLnFOAAfbPUogbvRhwb4 890MVbmTvRIRw7tSwfY7aLeif/qAUk8SrvQPiS8A5TF3OBQJ9fRjAytnI A==; X-CSE-ConnectionGUID: +elygl0WQv2oOLGGw8RrcA== X-CSE-MsgGUID: a8eq2SJVT2GQ/5f7Yn/1dA== X-IronPort-AV: E=McAfee;i="6700,10204,11200"; a="25961030" X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="25961030" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2024 00:03:19 -0700 X-CSE-ConnectionGUID: owzXq8XLT0WtP+ht7wKMCQ== X-CSE-MsgGUID: k9s8ujm7T3aoEJwCu3JrvQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="70235037" Received: from pglc00502.png.intel.com ([10.221.239.194]) by orviesa009.jf.intel.com with ESMTP; 20 Sep 2024 00:03:17 -0700 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Cc: Marek Vasut , Simon Goldschmidt , Meng Tingting , Yuslaimi Alif Zakuan , Hea Kok Kiang , Tien Fong Chee Subject: [PATCH v1 03/20] linker: Add SPL linker script for SoC64 devices Date: Fri, 20 Sep 2024 15:02:25 +0800 Message-Id: <20240920070242.20884-4-tien.fong.chee@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240920070242.20884-1-tien.fong.chee@intel.com> References: <20240920070242.20884-1-tien.fong.chee@intel.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Tien Fong Chee Add a new .data section for preserving the original state of the .data section of SoC64 SPL. This new .data section is required to make SPL reentrant after warm reset. Signed-off-by: Tien Fong Chee --- arch/arm/mach-socfpga/u-boot-spl-soc64.lds | 80 ++++++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 arch/arm/mach-socfpga/u-boot-spl-soc64.lds diff --git a/arch/arm/mach-socfpga/u-boot-spl-soc64.lds b/arch/arm/mach-socfpga/u-boot-spl-soc64.lds new file mode 100644 index 00000000000..91cf8dd3139 --- /dev/null +++ b/arch/arm/mach-socfpga/u-boot-spl-soc64.lds @@ -0,0 +1,80 @@ +/* + * (C) Copyright 2013 + * David Feng + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2010 + * Texas Instruments, + * Aneesh V + * + * Copyright (C) 2024 Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, + LENGTH = CONFIG_SPL_MAX_SIZE } +MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, + LENGTH = CONFIG_SPL_BSS_MAX_SIZE } + +OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64") +OUTPUT_ARCH(aarch64) +ENTRY(_start) +SECTIONS +{ + __image_copy_start = ADDR(.text); + .text : { + . = ALIGN(8); + CPUDIR/start.o (.text*) + *(.text*) + } >.sram + + .rodata : { + . = ALIGN(8); + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } >.sram + + .data : { + . = ALIGN(8); + /* Run time .data section starting at this location */ + __data_start = .; + *(.data*) + /* Run time .data section ending at this location */ + __data_end = .; + } >.sram + + . = ALIGN(8); + /* Preserve original .data section starting at this location */ + __preserve_data_start = .; + . = __preserve_data_start + (__data_end - __data_start); + /* Preserve original .data section ending at this location */ + __preserve_data_end = .; + + . = ALIGN(8); + __u_boot_list . : { + KEEP(*(SORT(__u_boot_list*))); + } >.sram + + . = ALIGN(8); + __image_copy_end = .; + + _end = .; + + _image_binary_end = .; + + .bss : { + __bss_start = .; + *(.bss*) + . = ALIGN(8); + __bss_end = .; + } >.sdram + + /DISCARD/ : { *(.dynsym) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} From patchwork Fri Sep 20 07:02:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1987674 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=P+fcHT/a; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X93KB5HzBz1xrD for ; Fri, 20 Sep 2024 17:04:14 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 68AA48937F; Fri, 20 Sep 2024 09:03:26 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="P+fcHT/a"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 369CC8937D; Fri, 20 Sep 2024 09:03:25 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id A349F89376 for ; Fri, 20 Sep 2024 09:03:21 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=tien.fong.chee@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1726815802; x=1758351802; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qj+U5BQj6yA04kHSFQib2wiFK6B/20WHcmnIdSGVbiw=; b=P+fcHT/apO3JNT8m62DlgNCZoESXwHkthIbMB2Tvmds3GnSJHi3EVp2s P3pJxnNT3b9pRWWU7xPNhVyBxdgkZmXkrH74n7kpGJCZBKyWyYaJ+ZO7p yH2KyQmRKhqiMZxxgAlxOUFgOOFOq3YrV5MObAP3KQRv81mCnFxz8Kxhd iGhhwwGae0l9FFyX7LORry/aQKkP2WCWsxazxMwy9ASI841rSBArpBSmm JoqDendxOS6dHfnutMYWmgHGxUm4GQdADRTnVDuyMwpb4B6e2OH/4x6DG 4RE72NcAVgcqwDTwS4nOw+2AibOgcyDLoXvzMIN+RQWuv+mN1k3Bz9bBJ g==; X-CSE-ConnectionGUID: UZwGAd/6R9SD9Rg40MCQHw== X-CSE-MsgGUID: F/UvmlZ5SH+Rdzd/aLj7Eg== X-IronPort-AV: E=McAfee;i="6700,10204,11200"; a="25961034" X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="25961034" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2024 00:03:22 -0700 X-CSE-ConnectionGUID: De53QyphQxGCjdYd5qwB4w== X-CSE-MsgGUID: L8ghjm57TrG8heFBZ0ThAA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="70235051" Received: from pglc00502.png.intel.com ([10.221.239.194]) by orviesa009.jf.intel.com with ESMTP; 20 Sep 2024 00:03:19 -0700 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Cc: Marek Vasut , Simon Goldschmidt , Meng Tingting , Yuslaimi Alif Zakuan , Hea Kok Kiang , Tien Fong Chee Subject: [PATCH v1 04/20] arm: socfpga: agilex5: Add low level initialization Date: Fri, 20 Sep 2024 15:02:26 +0800 Message-Id: <20240920070242.20884-5-tien.fong.chee@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240920070242.20884-1-tien.fong.chee@intel.com> References: <20240920070242.20884-1-tien.fong.chee@intel.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Tien Fong Chee Create new low level initialization for Agile5 due to the new ARM core composition and warm reset behavior. Signed-off-by: Tien Fong Chee --- arch/arm/mach-socfpga/Makefile | 1 + .../include/mach/reset_manager_soc64.h | 12 +++- arch/arm/mach-socfpga/lowlevel_init_agilex5.S | 57 +++++++++++++++++++ 3 files changed, 68 insertions(+), 2 deletions(-) create mode 100644 arch/arm/mach-socfpga/lowlevel_init_agilex5.S diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 67c6a8dfec5..53c91d1d2a5 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -58,6 +58,7 @@ endif ifdef CONFIG_TARGET_SOCFPGA_AGILEX5 obj-y += clock_manager_agilex5.o +obj-y += lowlevel_init_agilex5.o obj-y += mailbox_s10.o obj-y += misc_soc64.o obj-y += mmu-arm64_s10.o diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h index c8bb727aa2b..d373ec0dc70 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h @@ -1,15 +1,17 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2016-2019 Intel Corporation + * Copyright (C) 2016-2024 Intel Corporation */ #ifndef _RESET_MANAGER_SOC64_H_ #define _RESET_MANAGER_SOC64_H_ +#ifndef __ASSEMBLY__ void reset_deassert_peripherals_handoff(void); int cpu_has_been_warmreset(void); void print_reset_info(void); void socfpga_bridges_reset(int enable); +#endif #define RSTMGR_SOC64_STATUS 0x00 #define RSTMGR_SOC64_MPUMODRST 0x20 @@ -23,14 +25,20 @@ void socfpga_bridges_reset(int enable); #define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x00000004 /* SDM, Watchdogs and MPU warm reset mask */ -#define RSTMGR_STAT_SDMWARMRST BIT(1) +#define RSTMGR_STAT_SDMWARMRST 0x2 #define RSTMGR_STAT_MPU0RST_BITPOS 8 #define RSTMGR_STAT_L4WD0RST_BITPOS 16 +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define RSTMGR_STAT_L4WD0RST_BIT 0x1F0000 +#define RSTMGR_L4WD_MPU_WARMRESET_MASK (RSTMGR_STAT_SDMWARMRST | \ + RSTMGR_STAT_L4WD0RST_BIT) +#else #define RSTMGR_L4WD_MPU_WARMRESET_MASK (RSTMGR_STAT_SDMWARMRST | \ GENMASK(RSTMGR_STAT_MPU0RST_BITPOS + 3, \ RSTMGR_STAT_MPU0RST_BITPOS) | \ GENMASK(RSTMGR_STAT_L4WD0RST_BITPOS + 3, \ RSTMGR_STAT_L4WD0RST_BITPOS)) +#endif /* * SocFPGA Stratix10 reset IDs, bank mapping is as follows: diff --git a/arch/arm/mach-socfpga/lowlevel_init_agilex5.S b/arch/arm/mach-socfpga/lowlevel_init_agilex5.S new file mode 100644 index 00000000000..27430577719 --- /dev/null +++ b/arch/arm/mach-socfpga/lowlevel_init_agilex5.S @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2024 Intel Corporation. All rights reserved + */ + +#include +#include +#include +#include +#include + +ENTRY(lowlevel_init) + mov x29, lr /* Save LR */ + + /* Enable Async */ + msr daifclr, #4 + +#ifdef CONFIG_SPL_BUILD + branch_if_slave x0, 3f + + /* Check rstmgr.stat for warm reset status */ + ldr w1, =SOCFPGA_RSTMGR_ADDRESS + ldr w0, [x1] + /* Check whether any L4 watchdogs or SDM had triggered warm reset */ + ldr x2, =RSTMGR_L4WD_MPU_WARMRESET_MASK + ands x0, x0, x2 + /* + * If current Reset Manager's status is warm reset just reload the + * .data section by copying the data from data preserve section. + * Otherwise, copy the .data section to the data preserve section to + * keep an original copy of .data section. This ensure SPL is + * reentrant after warm reset. + */ + b.ne reload_data_section + /* Copy from .data to preserved .data to backup the SPL state */ + ldr x0, =__data_start + ldr x1, =__preserve_data_start + ldr x2, =__preserve_data_end + b copy_loop +reload_data_section: + /* Copy from preserved .data to .data to restore the SPL state */ + ldr x0, =__preserve_data_start + ldr x1, =__data_start + ldr x2, =__data_end +copy_loop: + ldr w3, [x0] + add x0, x0, #4 + str w3, [x1] + add x1, x1, #4 + cmp x1, x2 + b.ne copy_loop +3: +#endif + + mov lr, x29 /* Restore LR */ + ret +ENDPROC(lowlevel_init) From patchwork Fri Sep 20 07:02:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1987675 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=NFTrq/Oe; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X93KS2vbwz1xrD for ; Fri, 20 Sep 2024 17:04:28 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id C1AB48937E; Fri, 20 Sep 2024 09:03:28 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="NFTrq/Oe"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 1FBE28938A; Fri, 20 Sep 2024 09:03:27 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id C623B89335 for ; Fri, 20 Sep 2024 09:03:23 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=tien.fong.chee@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1726815804; x=1758351804; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gf4bBmZUGtDXpOrhYeWL7FZzs7pJghG8QD0l6bony/s=; b=NFTrq/Oe65Y4Gc0f4gcu0tgbHKhCrsD2/ta1RSj4/HPchpbOLzl4HwOB BmQ49r0Rto9E8OyhCUW5RZ3NM9JqbZonNzQ6LwKvRFPmbxMvrDgqmqiuJ u16dSjnBYIMKZXfrlN8W7DrPNXEwxmbnX8qIW/ttkCnA48gzrmzZSBjMs 47eXN1nMqmQfthvyT9S006HS/r511NU4OF0sM6vmkTEhSRqJUj9kT9yyu MZc8TSOLh1Bgt7sQyylQZ/wP4qwbQsN0HeWKFiU8W+rGx7H6vjF+zKMyN 1vYAlWzgPsHUKzPNy2tt1C6L6gCiGqeGUpLAe+wVchD2oIhKxBzEIHt3i w==; X-CSE-ConnectionGUID: ETMd/TcKScmuAmk2z/u+bQ== X-CSE-MsgGUID: F7zv8aNpR0W9Ik9Jfn2MlQ== X-IronPort-AV: E=McAfee;i="6700,10204,11200"; a="25961037" X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="25961037" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2024 00:03:24 -0700 X-CSE-ConnectionGUID: 9D0tFcBjTTKv2fujHQsyKw== X-CSE-MsgGUID: 5VXm2NqOTWajx6yQ3WDBwg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="70235062" Received: from pglc00502.png.intel.com ([10.221.239.194]) by orviesa009.jf.intel.com with ESMTP; 20 Sep 2024 00:03:21 -0700 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Cc: Marek Vasut , Simon Goldschmidt , Meng Tingting , Yuslaimi Alif Zakuan , Hea Kok Kiang , Tien Fong Chee Subject: [PATCH v1 05/20] arm: socfpga: Add handoff data support for SoCFPGA Agilex5 device Date: Fri, 20 Sep 2024 15:02:27 +0800 Message-Id: <20240920070242.20884-6-tien.fong.chee@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240920070242.20884-1-tien.fong.chee@intel.com> References: <20240920070242.20884-1-tien.fong.chee@intel.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Tien Fong Chee Agilex5 supports both HPS handoff data and DDR handoff data. Existing HPS handoff functions are restructured to support both existing devices and Agilex5 device. Signed-off-by: Tien Fong Chee --- arch/arm/mach-socfpga/Makefile | 1 + arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 4 ++-- arch/arm/mach-socfpga/wrap_handoff_soc64.c | 10 ++++++++-- 3 files changed, 11 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 53c91d1d2a5..e0ada69dd5a 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -63,6 +63,7 @@ obj-y += mailbox_s10.o obj-y += misc_soc64.o obj-y += mmu-arm64_s10.o obj-y += reset_manager_s10.o +obj-y += wrap_handoff_soc64.o obj-y += wrap_pll_config_soc64.o endif diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h index d839f288411..918d25a1b61 100644 --- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h @@ -17,9 +17,9 @@ #define SOC64_HANDOFF_MAGIC_FPGA 0x46504741 #define SOC64_HANDOFF_MAGIC_DELAY 0x444C4159 #define SOC64_HANDOFF_MAGIC_CLOCK 0x434C4B53 +#define SOC64_HANDOFF_MAGIC_SDRAM 0x5344524d #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) #define SOC64_HANDOFF_MAGIC_PERI 0x50455249 -#define SOC64_HANDOFF_MAGIC_SDRAM 0x5344524d #else #define SOC64_HANDOFF_MAGIC_MISC 0x4D495343 #endif @@ -68,7 +68,7 @@ #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) #define SOC64_HANDOFF_PERI (SOC64_HANDOFF_BASE + 0x620) #define SOC64_HANDOFF_SDRAM (SOC64_HANDOFF_BASE + 0x634) -#define SOC64_HANDOFF_SDRAM_LEN 1 +#define SOC64_HANDOFF_SDRAM_LEN 5 #endif #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) diff --git a/arch/arm/mach-socfpga/wrap_handoff_soc64.c b/arch/arm/mach-socfpga/wrap_handoff_soc64.c index 92051d19b73..c8456c8dd6a 100644 --- a/arch/arm/mach-socfpga/wrap_handoff_soc64.c +++ b/arch/arm/mach-socfpga/wrap_handoff_soc64.c @@ -1,15 +1,16 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2020-2021 Intel Corporation + * Copyright (C) 2020-2024 Intel Corporation * */ +#include #include #include -#include #include "log.h" #ifndef __ASSEMBLY__ +#include enum endianness { LITTLE_ENDIAN = 0, BIG_ENDIAN, @@ -26,7 +27,12 @@ static enum endianness check_endianness(u32 handoff) case SOC64_HANDOFF_MAGIC_FPGA: case SOC64_HANDOFF_MAGIC_DELAY: case SOC64_HANDOFF_MAGIC_CLOCK: + case SOC64_HANDOFF_MAGIC_SDRAM: +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + case SOC64_HANDOFF_MAGIC_PERI: +#else case SOC64_HANDOFF_MAGIC_MISC: +#endif return BIG_ENDIAN; #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) case SOC64_HANDOFF_DDR_UMCTL2_MAGIC: From patchwork Fri Sep 20 07:02:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1987686 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=GiJBg9nq; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X93MF5nfjz1y1t for ; Fri, 20 Sep 2024 17:06:00 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id B754B893A1; Fri, 20 Sep 2024 09:03:48 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="GiJBg9nq"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id A203089335; Fri, 20 Sep 2024 09:03:46 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 00F59891A4 for ; Fri, 20 Sep 2024 09:03:25 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=tien.fong.chee@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1726815807; x=1758351807; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0oVevuWKR5esSpQxLz/5DYqQijhyfJ1Btmpsr35o/ss=; b=GiJBg9nqtroDsraWDZafdqNNUt+Ay4CCpordWJRI7Tr0w8C5ajOLN4fB 9ep/LdxPbZBVfPCm0FPxSgTsKDJkfb2RjTQOeYKcEe4MewaPd+d5aGc5M fw8zhmfz46yWruf5HN37tfXyFTmZVMR+bi2IJcgM0jVxOpX4YwPQxUiEe 3YV6VoIMh/Ml0vLa/AiTagA1iYfHK+fs346xy4QJJbqKl5J/R9oG37MUh ZHe7DO/mY3ECnAAutWcSZEnzsJR4UrLrxPGWX/yPC18AeRySJs94cDz9n GQUPuJhnf0fFO3ZTCdjNCoNFajkQbCiVKqmhtXBGlKR7tJiFHBtxmZ095 g==; X-CSE-ConnectionGUID: 2AXMzwajStWHJsLe7GIcFA== X-CSE-MsgGUID: enEH/0OlTuqVS9OQv4sEVA== X-IronPort-AV: E=McAfee;i="6700,10204,11200"; a="25961043" X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="25961043" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2024 00:03:26 -0700 X-CSE-ConnectionGUID: E0HV17rUSS6RiWJwKtGhkg== X-CSE-MsgGUID: Vhpsx5wCTy+Si3j4HVve4w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="70235079" Received: from pglc00502.png.intel.com ([10.221.239.194]) by orviesa009.jf.intel.com with ESMTP; 20 Sep 2024 00:03:24 -0700 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Cc: Marek Vasut , Simon Goldschmidt , Meng Tingting , Yuslaimi Alif Zakuan , Hea Kok Kiang , Tien Fong Chee Subject: [PATCH v1 06/20] arm: dts: agilex5: Add HPS cache coherency unit configuration settings Date: Fri, 20 Sep 2024 15:02:28 +0800 Message-Id: <20240920070242.20884-7-tien.fong.chee@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240920070242.20884-1-tien.fong.chee@intel.com> References: <20240920070242.20884-1-tien.fong.chee@intel.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Tien Fong Chee These configuration settings are required to enable cache maintenance and access between initiators and targets. Signed-off-by: Tien Fong Chee --- arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 209 +++++++++++++++++++++++ 1 file changed, 209 insertions(+) diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi index a8167e5c14a..ec42fd01a9c 100644 --- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi @@ -13,6 +13,215 @@ #size-cells = <2>; bootph-all; }; + + soc { + bootph-all; + + socfpga_ccu_config: socfpga-ccu-config { + compatible = "intel,socfpga-dtreg"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + /* DSU */ + i_ccu_caiu0@1c000000 { + reg = <0x1c000000 0x00001000>; + intel,offset-settings = + /* CAIUMIFSR */ + <0x000003c4 0x00000000 0x07070777>, + /* DII1_MPFEREGS */ + <0x00000414 0x00018000 0xffffffff>, + <0x00000418 0x00000000 0x000000ff>, + <0x00000410 0xc0e00200 0xc1f03e1f>, + /* DII2_GICREGS */ + <0x00000424 0x0001d000 0xffffffff>, + <0x00000428 0x00000000 0x000000ff>, + <0x00000420 0xc0800400 0xc1f03e1f>, + /* NCAIU0_LWSOC2FPGA */ + <0x00000444 0x00020000 0xffffffff>, + <0x00000448 0x00000000 0x000000ff>, + <0x00000440 0xc1100006 0xc1f03e1f>, + /* NCAIU0_SOC2FPGA_1G */ + <0x00000454 0x00040000 0xffffffff>, + <0x00000458 0x00000000 0x000000ff>, + <0x00000450 0xc1200006 0xc1f03e1f>, + /* DMI_SDRAM_2G */ + <0x00000464 0x00080000 0xffffffff>, + <0x00000468 0x00000000 0x000000ff>, + /* NCAIU0_SOC2FPGA_16G */ + <0x00000474 0x00400000 0xffffffff>, + <0x00000478 0x00000000 0x000000ff>, + <0x00000470 0xc1600006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000484 0x00800000 0xffffffff>, + <0x00000488 0x00000000 0x000000ff>, + /* NCAIU0_SOC2FPGA_256G */ + <0x00000494 0x04000000 0xffffffff>, + <0x00000498 0x00000000 0x000000ff>, + <0x00000490 0xc1a00006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a4 0x08000000 0xffffffff>, + <0x000004a8 0x00000000 0x000000ff>; + bootph-all; + }; + + /* FPGA2SOC */ + i_ccu_ncaiu0@1c001000 { + reg = <0x1c001000 0x00001000>; + intel,offset-settings = + /* NCAIU0MIFSR */ + <0x000003c4 0x00000000 0x07070777>, + /* PSS */ + <0x00000404 0x00010000 0xffffffff>, + <0x00000408 0x00000000 0x000000ff>, + <0x00000400 0xC0F00000 0xc1f03e1f>, + /* DII1_MPFEREGS */ + <0x00000414 0x00018000 0xffffffff>, + <0x00000418 0x00000000 0x000000ff>, + <0x00000410 0xc0e00200 0xc1f03e1f>, + /* NCAIU0_LWSOC2FPGA */ + <0x00000444 0x00020000 0xffffffff>, + <0x00000448 0x00000000 0x000000ff>, + <0x00000440 0xc1100006 0xc1f03e1f>, + /* NCAIU0_SOC2FPGA_1G */ + <0x00000454 0x00040000 0xffffffff>, + <0x00000458 0x00000000 0x000000ff>, + <0x00000450 0xc1200006 0xc1f03e1f>, + /* DMI_SDRAM_2G */ + <0x00000464 0x00080000 0xffffffff>, + <0x00000468 0x00000000 0x000000ff>, + /* NCAIU0_SOC2FPGA_16G */ + <0x00000474 0x00400000 0xffffffff>, + <0x00000478 0x00000000 0x000000ff>, + <0x00000470 0xc1600006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000484 0x00800000 0xffffffff>, + <0x00000488 0x00000000 0x000000ff>, + /* NCAIU0_SOC2FPGA_256G */ + <0x00000494 0x04000000 0xffffffff>, + <0x00000498 0x00000000 0x000000ff>, + <0x00000490 0xc1a00006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a4 0x08000000 0xffffffff>, + <0x000004a8 0x00000000 0x000000ff>; + bootph-all; + }; + + /* GIC_M */ + i_ccu_ncaiu1@1c002000 { + reg = <0x1c002000 0x00001000>; + intel,offset-settings = + /* NCAIU1MIFSR */ + <0x000003c4 0x00000000 0x07070777>, + /* DMI_SDRAM_2G */ + <0x00000464 0x00080000 0xffffffff>, + <0x00000468 0x00000000 0x000000ff>, + /* DMI_SDRAM_30G */ + <0x00000484 0x00800000 0xffffffff>, + <0x00000488 0x00000000 0x000000ff>, + /* DMI_SDRAM_480G */ + <0x000004a4 0x08000000 0xffffffff>, + <0x000004a8 0x00000000 0x000000ff>; + bootph-all; + }; + + /* SMMU */ + i_ccu_ncaiu2@1c003000 { + reg = <0x1c003000 0x00001000>; + intel,offset-settings = + /* NCAIU2MIFSR */ + <0x000003c4 0x00000000 0x07070777>, + /* DMI_SDRAM_2G */ + <0x00000464 0x00080000 0xffffffff>, + <0x00000468 0x00000000 0x000000ff>, + /* DMI_SDRAM_30G */ + <0x00000484 0x00800000 0xffffffff>, + <0x00000488 0x00000000 0x000000ff>, + /* DMI_SDRAM_480G */ + <0x000004a4 0x08000000 0xffffffff>, + <0x000004a8 0x00000000 0x000000ff>; + bootph-all; + }; + + /* PSS NOC */ + i_ccu_ncaiu3@1c004000 { + reg = <0x1c004000 0x00001000>; + intel,offset-settings = + /* NCAIU3MIFSR */ + <0x000003c4 0x00000000 0x07070777>, + /* DII1_MPFEREGS */ + <0x00000414 0x00018000 0xffffffff>, + <0x00000418 0x00000000 0x000000ff>, + <0x00000410 0xc0e00200 0xc1f03e1f>, + /* DMI_SDRAM_2G */ + <0x00000464 0x00080000 0xffffffff>, + <0x00000468 0x00000000 0x000000ff>, + /* DMI_SDRAM_30G */ + <0x00000484 0x00800000 0xffffffff>, + <0x00000488 0x00000000 0x000000ff>, + /* DMI_SDRAM_480G */ + <0x000004a4 0x08000000 0xffffffff>, + <0x000004a8 0x00000000 0x000000ff>; + bootph-all; + }; + + /* DCE0 */ + i_ccu_dce0@1c005000 { + reg = <0x1c005000 0x00001000>; + intel,offset-settings = + /* DCEUMIFSR0 */ + <0x000003c4 0x00000000 0x07070777>, + /* DMI_SDRAM_2G */ + <0x00000464 0x00080000 0xffffffff>, + <0x00000468 0x00000000 0x000000ff>, + /* DMI_SDRAM_30G */ + <0x00000484 0x00800000 0xffffffff>, + <0x00000488 0x00000000 0x000000ff>, + /* DMI_SDRAM_480G */ + <0x000004a4 0x08000000 0xffffffff>, + <0x000004a8 0x00000000 0x000000ff>; + bootph-all; + }; + + /* DCE1 */ + i_ccu_dce1@1c006000 { + reg = <0x1c006000 0x00001000>; + intel,offset-settings = + /* DCEUMIFSR1 */ + <0x000003c4 0x00000000 0x07070777>, + /* DMI_SDRAM_2G */ + <0x00000464 0x00080000 0xffffffff>, + <0x00000468 0x00000000 0x000000ff>, + /* DMI_SDRAM_30G */ + <0x00000484 0x00800000 0xffffffff>, + <0x00000488 0x00000000 0x000000ff>, + /* DMI_SDRAM_480G */ + <0x000004a4 0x08000000 0xffffffff>, + <0x000004a8 0x00000000 0x000000ff>; + bootph-all; + }; + + /* DMI0 */ + i_ccu_dmi0@1c007000 { + reg = <0x1c007000 0x00001000>; + intel,offset-settings = + /* DMIUSMCTCR */ + <0x00000300 0x00000001 0x00000003>, + <0x00000300 0x00000003 0x00000003>; + bootph-all; + }; + + /* DMI1 */ + i_ccu_dmi0@1c008000 { + reg = <0x1c008000 0x00001000>; + intel,offset-settings = + /* DMIUSMCTCR */ + <0x00000300 0x00000001 0x00000003>, + <0x00000300 0x00000003 0x00000003>; + bootph-all; + }; + }; + }; }; &clkmgr { From patchwork Fri Sep 20 07:02:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1987676 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=k2zqypKm; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X93Kk1xPVz1xrD for ; Fri, 20 Sep 2024 17:04:42 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 2616E8937C; Fri, 20 Sep 2024 09:03:33 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="k2zqypKm"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id BBD5B89357; Fri, 20 Sep 2024 09:03:31 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 4F3CC89323 for ; Fri, 20 Sep 2024 09:03:29 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=tien.fong.chee@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1726815810; x=1758351810; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3hN1zhziyS3oz2XWm3zf97DSkEU+iIVZRpej92AeylM=; b=k2zqypKmhX8laRvQSbrPmDZHTOatkcSux0KtGz7kgnDVBIeG0mAsgvg2 2IoW19yN7mefX7HRQ6UjpHhOBkzrwBoz4XZMW9J3Hlt0gRROluh601NPl dJBgmlT1fc72ZyGcoLEjwn8sKNss3WCqV8kr6/znKLFkXMMD9fcuHiK8B 8ksmGd1IwyvqtEYAG+eASoeXOX9FFOKcwxSbXsOWe84dmIpdE08ooWvGN AFpgWcn4GgWDBJlnGbLUNJYmD1IUaXUDNZqt1NGproeMn7tEzn6YM6qhn f3F9orTI1nqQ/hdne+eAuVp5psatiljIhz7UycUQd25nTLYM1ugEJQv+1 A==; X-CSE-ConnectionGUID: cGP3R1HJSkqZm7iTNm2RRw== X-CSE-MsgGUID: hTtMzKBIS+GlTiQjZJVaVw== X-IronPort-AV: E=McAfee;i="6700,10204,11200"; a="25961047" X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="25961047" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2024 00:03:28 -0700 X-CSE-ConnectionGUID: 8syEdc4SSs215D8nLAgKmw== X-CSE-MsgGUID: x7AYy92VQV2cxO0izFqhWQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="70235094" Received: from pglc00502.png.intel.com ([10.221.239.194]) by orviesa009.jf.intel.com with ESMTP; 20 Sep 2024 00:03:26 -0700 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Cc: Marek Vasut , Simon Goldschmidt , Meng Tingting , Yuslaimi Alif Zakuan , Hea Kok Kiang , Tien Fong Chee Subject: [PATCH v1 07/20] arm: dts: agilex5: Add firewall configure settings Date: Fri, 20 Sep 2024 15:02:29 +0800 Message-Id: <20240920070242.20884-8-tien.fong.chee@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240920070242.20884-1-tien.fong.chee@intel.com> References: <20240920070242.20884-1-tien.fong.chee@intel.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Tien Fong Chee These firewall configure settings are needed to disable firewall on respective hardware component so both secure and non-secure transactions are allowed. Signed-off-by: Tien Fong Chee --- arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 166 +++++++++++++++++++++++ 1 file changed, 166 insertions(+) diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi index ec42fd01a9c..bf30b3b8858 100644 --- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi @@ -221,6 +221,172 @@ bootph-all; }; }; + + socfpga_firewall_config: socfpga-firewall-config { + compatible = "intel,socfpga-dtreg"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + /* L4 peripherals firewall */ + noc_fw_l4_per@10d21000 { + reg = <0x10d21000 0x0000008c>; + intel,offset-settings = + /* NAND */ + <0x00000000 0x01010001 0x01010001>, + /* USB0 */ + <0x0000000c 0x01010001 0x01010001>, + /* USB1 */ + <0x00000010 0x01010001 0x01010001>, + /* SPI_MAIN0 */ + <0x0000001c 0x01010301 0x01010301>, + /* SPI_MAIN1 */ + <0x00000020 0x01010301 0x01010301>, + /* SPI_SECONDARY0 */ + <0x00000024 0x01010301 0x01010301>, + /* SPI_SECONDARY1 */ + <0x00000028 0x01010301 0x01010301>, + /* EMAC0 */ + <0x0000002c 0x01010001 0x01010001>, + /* EMAC1 */ + <0x00000030 0x01010001 0x01010001>, + /* EMAC2 */ + <0x00000034 0x01010001 0x01010001>, + /* SDMMC */ + <0x00000040 0x01010001 0x01010001>, + /* GPIO0 */ + <0x00000044 0x01010301 0x01010301>, + /* GPIO1 */ + <0x00000048 0x01010301 0x01010301>, + /* I2C0 */ + <0x00000050 0x01010301 0x01010301>, + /* I2C1 */ + <0x00000054 0x01010301 0x01010301>, + /* I2C2 */ + <0x00000058 0x01010301 0x01010301>, + /* I2C3 */ + <0x0000005c 0x01010301 0x01010301>, + /* I2C4 */ + <0x00000060 0x01010301 0x01010301>, + /* SP_TIMER0 */ + <0x00000064 0x01010301 0x01010301>, + /* SP_TIMER1 */ + <0x00000068 0x01010301 0x01010301>, + /* UART0 */ + <0x0000006c 0x01010301 0x01010301>, + /* UART1 */ + <0x00000070 0x01010301 0x01010301>, + /* I3C0 */ + <0x00000074 0x01010301 0x01010301>, + /* I3C1 */ + <0x00000078 0x01010301 0x01010301>, + /* DMA0 */ + <0x0000007c 0x01010001 0x01010001>, + /* DMA1 */ + <0x00000080 0x01010001 0x01010001>, + /* COMBO_PHY */ + <0x00000084 0x01010001 0x01010001>, + /* NAND_SDMA */ + <0x00000088 0x01010301 0x01010301>; + bootph-all; + }; + + /* L4 system firewall */ + noc_fw_l4_sys@10d21100 { + reg = <0x10d21100 0x00000098>; + intel,offset-settings = + /* DMA_ECC */ + <0x00000008 0x01010001 0x01010001>, + /* EMAC0RX_ECC */ + <0x0000000c 0x01010001 0x01010001>, + /* EMAC0TX_ECC */ + <0x00000010 0x01010001 0x01010001>, + /* EMAC1RX_ECC */ + <0x00000014 0x01010001 0x01010001>, + /* EMAC1TX_ECC */ + <0x00000018 0x01010001 0x01010001>, + /* EMAC2RX_ECC */ + <0x0000001c 0x01010001 0x01010001>, + /* EMAC2TX_ECC */ + <0x00000020 0x01010001 0x01010001>, + /* NAND_ECC */ + <0x0000002c 0x01010001 0x01010001>, + /* NAND_READ_ECC */ + <0x00000030 0x01010001 0x01010001>, + /* NAND_WRITE_ECC */ + <0x00000034 0x01010001 0x01010001>, + /* OCRAM_ECC */ + <0x00000038 0x01010001 0x01010001>, + /* SDMMC_ECC */ + <0x00000040 0x01010001 0x01010001>, + /* USB0_ECC */ + <0x00000044 0x01010001 0x01010001>, + /* USB1_CACHEECC */ + <0x00000048 0x01010001 0x01010001>, + /* CLOCK_MANAGER */ + <0x0000004c 0x01010001 0x01010001>, + /* IO_MANAGER */ + <0x00000054 0x01010001 0x01010001>, + /* RESET_MANAGER */ + <0x00000058 0x01010001 0x01010001>, + /* SYSTEM_MANAGER */ + <0x0000005c 0x01010001 0x01010001>, + /* OSC0_TIMER */ + <0x00000060 0x01010301 0x01010301>, + /* OSC1_TIMER0*/ + <0x00000064 0x01010301 0x01010301>, + /* WATCHDOG0 */ + <0x00000068 0x01010301 0x01010301>, + /* WATCHDOG1 */ + <0x0000006c 0x01010301 0x01010301>, + /* WATCHDOG2 */ + <0x00000070 0x01010301 0x01010301>, + /* WATCHDOG3 */ + <0x00000074 0x01010301 0x01010301>, + /* DAP */ + <0x00000078 0x03010001 0x03010001>, + /* WATCHDOG4 */ + <0x0000007c 0x01010301 0x01010301>, + /* POWER_MANAGER */ + <0x00000080 0x01010001 0x01010001>, + /* USB1_RXECC */ + <0x00000084 0x01010001 0x01010001>, + /* USB1_TXECC */ + <0x00000088 0x01010001 0x01010001>, + /* L4_NOC_PROBES */ + <0x00000090 0x01010001 0x01010001>, + /* L4_NOC_QOS */ + <0x00000094 0x01010001 0x01010001>; + bootph-all; + }; + + /* Light weight SoC2FPGA */ + noc_fw_lwsoc2fpga@10d21300 { + reg = <0x10d21300 0x0000004>; + intel,offset-settings = + /* LWSOC2FPGA_CSR */ + <0x00000000 0x0ffe0301 0x0ffe0301>; + bootph-all; + }; + + /* SoC2FPGA */ + noc_fw_soc2fpga@10d21200 { + reg = <0x10d21200 0x0000004>; + intel,offset-settings = + /* SOC2FPGA_CSR */ + <0x00000000 0x0ffe0301 0x0ffe0301>; + bootph-all; + }; + + /* TCU */ + noc_fw_tcu@10d21400 { + reg = <0x10d21400 0x0000004>; + intel,offset-settings = + /* TCU_CSR */ + <0x00000000 0x01010001 0x01010001>; + bootph-all; + }; + }; }; }; From patchwork Fri Sep 20 07:02:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1987677 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=AD8C8Hl4; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X93Kz5NC2z1xrD for ; Fri, 20 Sep 2024 17:04:55 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id A798C89343; Fri, 20 Sep 2024 09:03:34 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="AD8C8Hl4"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id C7AEF8937C; Fri, 20 Sep 2024 09:03:32 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 61F448937D for ; Fri, 20 Sep 2024 09:03:30 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=tien.fong.chee@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1726815811; x=1758351811; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+iqGUcGUEE4bBN7rZNa2VRI3Z8djVEa87CU7p+pt5JY=; b=AD8C8Hl4EkWz2+YsCeE6ueWDcKGWeMNzkH+RAVE+WriE+Op3von8cwZJ nEj3Gitbh7FQDdnMvt05U7Dg5tWzFC5QYuZAkpkEsBmvpYY4syG9QbekT DdvSRgyJeI70vXiBLcpPTVUMaFg68J2umUQyZBkeDqGCM6PI2kZFFFYUy I1E4bguC8CxZV6EYr6SueRRovS9cN2ivODEtthRTEsEA/WOqsp0O67RP5 iEQJYxon4YR61bVkDjM2Y3XLppt27BeIiG5M/k2ppWplx9+AYPElPy3fY i3aSPrhBa73+t7y3Td9ppadU13aXvBUudZ6ZMDey4HuqoPhpSvw8FS16X A==; X-CSE-ConnectionGUID: UAYhITowRQmmfT3FeNMpYQ== X-CSE-MsgGUID: gCu4iCFLQl6kavIPNKsszw== X-IronPort-AV: E=McAfee;i="6700,10204,11200"; a="25961052" X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="25961052" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2024 00:03:30 -0700 X-CSE-ConnectionGUID: 0CrfNNrSRdSSieiEBRBvGQ== X-CSE-MsgGUID: BukKmHiiRneoFAecEEIctw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="70235114" Received: from pglc00502.png.intel.com ([10.221.239.194]) by orviesa009.jf.intel.com with ESMTP; 20 Sep 2024 00:03:28 -0700 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Cc: Marek Vasut , Simon Goldschmidt , Meng Tingting , Yuslaimi Alif Zakuan , Hea Kok Kiang , Tien Fong Chee Subject: [PATCH v1 08/20] arm: dts: agilex5: Enable XGMAC Date: Fri, 20 Sep 2024 15:02:30 +0800 Message-Id: <20240920070242.20884-9-tien.fong.chee@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240920070242.20884-1-tien.fong.chee@intel.com> References: <20240920070242.20884-1-tien.fong.chee@intel.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Tien Fong Chee Enable XGMAC for SoCFPGA Agilex5 devkit. Signed-off-by: Tien Fong Chee --- .../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi index 9eb21d65428..75ab05031bc 100644 --- a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi @@ -122,3 +122,36 @@ bootph-all; }; +&gmac0 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&emac0_phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwxgmac-mdio"; + emac0_phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&emac2_phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwxgmac-mdio"; + emac2_phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; From patchwork Fri Sep 20 07:02:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1987679 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=UAzzjXTa; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X93LF5SM3z1y2j for ; Fri, 20 Sep 2024 17:05:09 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 3161489387; Fri, 20 Sep 2024 09:03:36 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="UAzzjXTa"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 3D4F68938C; Fri, 20 Sep 2024 09:03:35 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id C2E2989357 for ; Fri, 20 Sep 2024 09:03:32 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=tien.fong.chee@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1726815813; x=1758351813; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3Kx9xynE0bKh0Xuiqj2UFjj2/BmZ7FW5HMaQmtxUcKQ=; b=UAzzjXTaRlsn4y6b9M1MZg2MhYK7U54Pi+QxKMyGq8tuRu7W8Mfm9IRo tA3VVwevu2Krx7a/07VXsNNGQcYd6OUJVt+UQE5/VB53EkfgOL395P2DX 3g4BZlqZRiLautriLG9PoSel3mBIsoaFEk1u1+edhdvNUr49wahN9mHCc EgKe57VzskGqI8SRqy42JbXfj0Ql92Qq528yBRRURtYGy7ETJZjWmlM2I 4O4Vs6CHcMGef1OzuTLvb0Qb2nSTU+2p5AYdz9w9hQTWhSveoooc2UFJy VK/nUwmsQy/tUg+6vIsHxEEVWSeCBbrQm9r8rWI7+ohQ0RhO+xmxIOUtb A==; X-CSE-ConnectionGUID: 4VKV4bJBSP6OIEUv24Ailw== X-CSE-MsgGUID: V+OrjJRRQYyBVV7REDHGRg== X-IronPort-AV: E=McAfee;i="6700,10204,11200"; a="25961057" X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="25961057" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2024 00:03:32 -0700 X-CSE-ConnectionGUID: wKaQqltxSzaGQu5/GV47qg== X-CSE-MsgGUID: Xtv+Bf+FRjijM92uufUFQQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="70235126" Received: from pglc00502.png.intel.com ([10.221.239.194]) by orviesa009.jf.intel.com with ESMTP; 20 Sep 2024 00:03:30 -0700 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Cc: Marek Vasut , Simon Goldschmidt , Meng Tingting , Yuslaimi Alif Zakuan , Hea Kok Kiang , Tien Fong Chee Subject: [PATCH v1 09/20] sysreset: Add reset support to SoCFPGA Agilex5 device Date: Fri, 20 Sep 2024 15:02:31 +0800 Message-Id: <20240920070242.20884-10-tien.fong.chee@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240920070242.20884-1-tien.fong.chee@intel.com> References: <20240920070242.20884-1-tien.fong.chee@intel.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Tien Fong Chee The reset driver can support both cold reset and warm reset with SMCC to ATF. Signed-off-by: Tien Fong Chee --- arch/arm/Kconfig | 1 + drivers/sysreset/Kconfig | 7 +++ drivers/sysreset/Makefile | 1 + drivers/sysreset/sysreset_socfpga_agilex5.c | 47 +++++++++++++++++++++ 4 files changed, 56 insertions(+) create mode 100644 drivers/sysreset/sysreset_socfpga_agilex5.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ba0359fed5a..8e9a39e7d23 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1123,6 +1123,7 @@ config ARCH_SOCFPGA select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5 && \ TARGET_SOCFPGA_SOC64 + select SYSRESET_SOCFPGA_AGILEX5 if TARGET_SOCFPGA_AGILEX5 imply CMD_DM imply CMD_MTDPARTS imply CRC32_VERIFY diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index 121194e4418..8dc1e7fec58 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -156,6 +156,13 @@ config SYSRESET_SOCFPGA_SOC64 This enables the system reset driver support for Intel SOCFPGA SoC64 SoCs. +config SYSRESET_SOCFPGA_AGILEX5 + bool "Enable support for Intel SOCFPGA AGILEX5 device" + depends on ARCH_SOCFPGA && TARGET_SOCFPGA_AGILEX5 + help + This enables the system reset driver support for Intel SOCFPGA + AGILEX5 device. + config SYSRESET_TEGRA bool "Tegra PMC system reset driver" depends on ARCH_TEGRA diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile index a6a0584585c..c090db48af4 100644 --- a/drivers/sysreset/Makefile +++ b/drivers/sysreset/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o obj-$(CONFIG_SYSRESET_SBI) += sysreset_sbi.o obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o obj-$(CONFIG_SYSRESET_SOCFPGA_SOC64) += sysreset_socfpga_soc64.o +obj-$(CONFIG_SYSRESET_SOCFPGA_AGILEX5) += sysreset_socfpga_agilex5.o obj-$(CONFIG_SYSRESET_TEGRA) += sysreset_tegra.o obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o obj-$(CONFIG_$(SPL_TPL_)SYSRESET_TPS65910) += sysreset_tps65910.o diff --git a/drivers/sysreset/sysreset_socfpga_agilex5.c b/drivers/sysreset/sysreset_socfpga_agilex5.c new file mode 100644 index 00000000000..3cb7849ec88 --- /dev/null +++ b/drivers/sysreset/sysreset_socfpga_agilex5.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Intel Corporation + * + */ + +#include +#include +#include +#include +#include +#include +#include + +static int socfpga_sysreset_request(struct udevice *dev, + enum sysreset_t type) +{ +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) + const char *reset = env_get("reset"); + + if (reset && !strcmp(reset, "warm")) { + /* Ensure content in dcache is flushed to system memory */ + flush_dcache_all(); + + /* request a warm reset */ + puts("Do warm reset now...\n"); + + /* doing architecture system reset */ + psci_system_reset2(0, 0); + } else { + puts("Issuing cold reset REBOOT_HPS\n"); + psci_system_reset(); + } +#endif + + return -EINPROGRESS; +} + +static struct sysreset_ops socfpga_sysreset = { + .request = socfpga_sysreset_request, +}; + +U_BOOT_DRIVER(sysreset_socfpga) = { + .id = UCLASS_SYSRESET, + .name = "socfpga_sysreset", + .ops = &socfpga_sysreset, +}; From patchwork Fri Sep 20 07:02:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1987684 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=Ydra71Eb; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X93Ll3dYsz1y1t for ; Fri, 20 Sep 2024 17:05:35 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 0296889335; Fri, 20 Sep 2024 09:03:47 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Ydra71Eb"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 687C589357; Fri, 20 Sep 2024 09:03:44 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id C334F8937B for ; Fri, 20 Sep 2024 09:03:34 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=tien.fong.chee@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1726815815; x=1758351815; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8Fkc+LC652OlNLLIAj65gculo9hnLmfHHMof5OCtiJE=; b=Ydra71Ebt8YfsdwR+xsSE4merT5GuNYT4zaKVG2LlP+mpveLReQgxvKK VWRQ+hLWdZhL6P+85KcyB/rTbRAOj/KTmIPzIBN+vN2AZ4KS4LSPSHQnU ohN5QR+vuhEwXC9N16+97G3+WrYKqC8aibMAn+2SeH+kcpiLp+db0OcF0 Xp161/VEOdtg6dVZvEtHToOTuoDtNuihZ1T8g728VIeD2XdEa58bd/6w7 7HikqnJ1u8OLX0XBdgx02vW1EHKPpi7QsX2VX5LXUvAsRss+WIHNsQqGH tFRQ2PzzxYHcyoUecGmslXZdy9ODj8sKZtFtMlQrfDP1ysbSLVT2u9BDA w==; X-CSE-ConnectionGUID: sbmepBVNR9GVER0lvs78cA== X-CSE-MsgGUID: VXft35PJSOyYBOeKhIw5VA== X-IronPort-AV: E=McAfee;i="6700,10204,11200"; a="25961061" X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="25961061" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2024 00:03:35 -0700 X-CSE-ConnectionGUID: IX135KbcRGW7snQE3oPsZQ== X-CSE-MsgGUID: WGwNCN8PR5uRzd8tgbW9+w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="70235137" Received: from pglc00502.png.intel.com ([10.221.239.194]) by orviesa009.jf.intel.com with ESMTP; 20 Sep 2024 00:03:32 -0700 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Cc: Marek Vasut , Simon Goldschmidt , Meng Tingting , Yuslaimi Alif Zakuan , Hea Kok Kiang , Tien Fong Chee Subject: [PATCH v1 10/20] arm: socfpga: agilex5: Enable cache flush for system memory cache in CCU Date: Fri, 20 Sep 2024 15:02:32 +0800 Message-Id: <20240920070242.20884-11-tien.fong.chee@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240920070242.20884-1-tien.fong.chee@intel.com> References: <20240920070242.20884-1-tien.fong.chee@intel.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Tien Fong Chee set/way instructions "dc cisw" ehich is used by the "dcache flush" command only flushing CPU data caches from L1 -> L2 -> L3 to system memory cache in cache coherency unit, hence this patch enables data flush from system memory cache of CCU into DDR memory. Signed-off-by: Tien Fong Chee --- arch/arm/mach-socfpga/Makefile | 1 + arch/arm/mach-socfpga/ccu_ncore3.c | 64 ++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+) create mode 100644 arch/arm/mach-socfpga/ccu_ncore3.c diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index e0ada69dd5a..32b3e7a57e2 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -65,6 +65,7 @@ obj-y += mmu-arm64_s10.o obj-y += reset_manager_s10.o obj-y += wrap_handoff_soc64.o obj-y += wrap_pll_config_soc64.o +obj-y += ccu_ncore3.o endif ifdef CONFIG_TARGET_SOCFPGA_N5X diff --git a/arch/arm/mach-socfpga/ccu_ncore3.c b/arch/arm/mach-socfpga/ccu_ncore3.c new file mode 100644 index 00000000000..18667131eb9 --- /dev/null +++ b/arch/arm/mach-socfpga/ccu_ncore3.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Intel Corporation + * + */ +#include +#include +#include + +#define CCU_DMI0_DMIUSMCTCR SOCFPGA_CCU_ADDRESS + 0x7300 +#define CCU_DMI0_DMIUSMCMCR SOCFPGA_CCU_ADDRESS + 0x7340 +#define CCU_DMI0_DMIUSMCMAR SOCFPGA_CCU_ADDRESS + 0x7344 +#define CCU_DMI0_DMIUSMCMCR_MNTOP GENMASK(3, 0) +#define MAX_DISTRIBUTED_MEM_INTERFACE 2 +#define FLUSH_ALL_ENTRIES 0x4 +#define CCU_DMI0_DMIUSMCMCR_ARRAY_ID GENMASK(21, 16) +#define ARRAY_ID_TAG 0x0 +#define ARRAY_ID_DATA 0x1 +#define CACHE_OPERATION_DONE BIT(0) +#define TIMEOUT_200MS 200 + +int __asm_flush_l3_dcache(void) +{ + int i; + int ret = 0; + + /* Flushing all entries in CCU system memory cache */ + for (i = 0; i < MAX_DISTRIBUTED_MEM_INTERFACE; i++) { + /* + * Skipping if the system memory cache is not enabled for + * particular DMI + */ + if (!readl((uintptr_t)(CCU_DMI0_DMIUSMCTCR + (i * 0x1000)))) + continue; + + writel(FIELD_PREP(CCU_DMI0_DMIUSMCMCR_MNTOP, FLUSH_ALL_ENTRIES) | + FIELD_PREP(CCU_DMI0_DMIUSMCMCR_ARRAY_ID, ARRAY_ID_TAG), + (uintptr_t)(CCU_DMI0_DMIUSMCMCR + (i * 0x1000))); + + /* Wait for cache maintenance operation done */ + ret = wait_for_bit_le32((const void *)(uintptr_t)(CCU_DMI0_DMIUSMCMAR + + (i * 0x1000)), CACHE_OPERATION_DONE, false, TIMEOUT_200MS, + false); + if (ret) { + debug("%s: Timeout while waiting for flushing tag in DMI%d done\n", + __func__, i); + return ret; + } + + writel(FIELD_PREP(CCU_DMI0_DMIUSMCMCR_MNTOP, FLUSH_ALL_ENTRIES) | + FIELD_PREP(CCU_DMI0_DMIUSMCMCR_ARRAY_ID, ARRAY_ID_DATA), + (uintptr_t)(CCU_DMI0_DMIUSMCMCR + (i * 0x1000))); + + /* Wait for cache maintenance operation done */ + ret = wait_for_bit_le32((const void *)(uintptr_t)(CCU_DMI0_DMIUSMCMAR + + (i * 0x1000)), CACHE_OPERATION_DONE, false, TIMEOUT_200MS, + false); + if (ret) + debug("%s: Timeout waiting for flushing data in DMI%d done\n", + __func__, i); + } + + return ret; +} From patchwork Fri Sep 20 07:02:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1987682 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=F+/jJwBP; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X93LV0ztPz1y31 for ; Fri, 20 Sep 2024 17:05:22 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 8CB7089357; Fri, 20 Sep 2024 09:03:44 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="F+/jJwBP"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 6F6B689391; Fri, 20 Sep 2024 09:03:43 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 1BB1189398 for ; Fri, 20 Sep 2024 09:03:37 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=tien.fong.chee@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1726815819; x=1758351819; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=uuqAwsohccYWza6uga4J7ZGK9u6uHq6zwMVSh8rlnuE=; b=F+/jJwBPTXSRBuyC8NemK6sqX+Axm/i3TVSOVpzMIaJ8ZndW05yVcHa9 QWoG4gBKWwjhrlP8UVYJb7TAtcq5i7+zEIh9oo1dWIIJ/YIf/7t2M/2X5 EzVhmoCMHNUhCVU8fQwfrOViNr+LAOki59DmdLxR4V0rNa9stq46TixR6 ElUdGo0cf4cRVqfbLZNNALqHEJUT7q4U2TzgS+6jCrmNzIeT/zS+ItEbF 8+nHFt33WnxVrwDRAF6vYctlJqI8MyuqJtuSN7Q9EeHENwLjDe55SF/fQ mRKTJSbj76DBz1gTRRGF1ggJ8rGSBSBFjaOUxgvC7RpP7Djdc587f0sm8 A==; X-CSE-ConnectionGUID: UtR3rbSsQSW3aYWNSQzWjA== X-CSE-MsgGUID: 7hX+7IOCSrSV3/rbJH4/Tw== X-IronPort-AV: E=McAfee;i="6700,10204,11200"; a="25961067" X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="25961067" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2024 00:03:37 -0700 X-CSE-ConnectionGUID: uRBULuiORC+jUspAswoKiw== X-CSE-MsgGUID: UJyBzes5QcequSa8VBagfw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="70235158" Received: from pglc00502.png.intel.com ([10.221.239.194]) by orviesa009.jf.intel.com with ESMTP; 20 Sep 2024 00:03:34 -0700 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Cc: Marek Vasut , Simon Goldschmidt , Meng Tingting , Yuslaimi Alif Zakuan , Hea Kok Kiang , Tien Fong Chee Subject: [PATCH v1 11/20] arm: socfpga: agilex5: Add SMMU initialization Date: Fri, 20 Sep 2024 15:02:33 +0800 Message-Id: <20240920070242.20884-12-tien.fong.chee@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240920070242.20884-1-tien.fong.chee@intel.com> References: <20240920070242.20884-1-tien.fong.chee@intel.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Tien Fong Chee Allow non-secure accesses only with SMMU peripherals. This would protect the content in DDR secure region from accidentally modified by SMMU peripherals. Signed-off-by: Tien Fong Chee --- arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 34 ++++++++++++++++++++++++ arch/arm/mach-socfpga/spl_soc64.c | 17 +++++++++++- 2 files changed, 50 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi index bf30b3b8858..9baf2cbc525 100644 --- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi @@ -387,6 +387,40 @@ bootph-all; }; }; + + socfpga_smmu_secure_config: socfpga-smmu-secure-config { + compatible = "intel,socfpga-dtreg"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + /* System manager */ + i_sys_mgt_sysmgr_csr@10d12000 { + reg = <0x10d12000 0x00000500>; + intel,offset-settings = + /* dma_tbu_stream_ctrl_reg_0_dma0 */ + <0x0000017c 0x00000000 0x0000003f>, + /* dma_tbu_stream_ctrl_reg_0_dma1 */ + <0x00000180 0x00000000 0x0000003f>, + /* sdm_tbu_stream_ctrl_reg_1_sdm */ + <0x00000184 0x00000000 0x0000003f>, + /* io_tbu_stream_ctrl_reg_2_usb2 */ + <0x00000188 0x00000000 0x0000003f>, + /* io_tbu_stream_ctrl_reg_2_sdmmc */ + <0x00000190 0x00000000 0x0000003f>, + /* io_tbu_stream_ctrl_reg_2_nand */ + <0x00000194 0x00000000 0x0000003f>, + /* io_tbu_stream_ctrl_reg_2_etr */ + <0x00000198 0x00000000 0x0000003f>, + /* tsn_tbu_stream_ctrl_reg_3_tsn0 */ + <0x0000019c 0x00000000 0x0000003f>, + /* tsn_tbu_stream_ctrl_reg_3_tsn1 */ + <0x000001a0 0x00000000 0x0000003f>, + /* tsn_tbu_stream_ctrl_reg_3_tsn2 */ + <0x000001a4 0x00000000 0x0000003f>; + bootph-all; + }; + }; }; }; diff --git a/arch/arm/mach-socfpga/spl_soc64.c b/arch/arm/mach-socfpga/spl_soc64.c index 4fe67ea0811..3bfe4bb9dd3 100644 --- a/arch/arm/mach-socfpga/spl_soc64.c +++ b/arch/arm/mach-socfpga/spl_soc64.c @@ -1,10 +1,12 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2020 Intel Corporation. All rights reserved + * Copyright (C) 2020-2024 Intel Corporation. All rights reserved * */ +#include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -22,3 +24,16 @@ u32 spl_boot_mode(const u32 boot_device) return MMCSD_MODE_RAW; } #endif + +/* board specific function prior loading SSBL / U-Boot */ +void spl_perform_fixups(struct spl_image_info *spl_image) +{ + int ret; + struct udevice *dev; + + ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-smmu-secure-config", &dev); + if (ret) { + printf("HPS SMMU secure settings init failed: %d\n", ret); + hang(); + } +} From patchwork Fri Sep 20 07:02:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1987685 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=mG+4IxEH; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X93M02W2rz1y1t for ; Fri, 20 Sep 2024 17:05:48 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 5C9658939A; Fri, 20 Sep 2024 09:03:47 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="mG+4IxEH"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 5CEDD89394; Fri, 20 Sep 2024 09:03:44 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id EB8C489357 for ; Fri, 20 Sep 2024 09:03:41 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=tien.fong.chee@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1726815822; x=1758351822; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VMxjvPDP15bgcOVs4blEaWXFcHbrmAXQkKQgVueFPEM=; b=mG+4IxEH432M22eIVLje7cIypKSykL6omWVxneurq0yJ/EWrRDbYOvCE eT8EH2nQep2S1pmb/SbIL5+Kl6TqPHBFujgPybpcAL0FIoemd1haHta5i nNUEtsqow4mpxedYrVwOio93yerh6MEIAbVBJC3xeALkbnMHpQ2Gauvin Lu00pymOn5LCJ2SZIN5OpeHKCIpL1dcK5EJcrrPnrU5eT5lBAcvqb1nUO DVMFZn7bptQa1ffoDw5H1ASaDrGeGcktQQmppqLqbJPDpYt+BRqBgHUee QupM2kcYcV+gRiu29iCdn/UgwGK1Oph/3XRw293vW/eBuzg5WwMfzv23i g==; X-CSE-ConnectionGUID: RISwr5fSQKm3JKgjrQfFiA== X-CSE-MsgGUID: gPgoEtLNRuyi5yoqzOFU4w== X-IronPort-AV: E=McAfee;i="6700,10204,11200"; a="25961072" X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="25961072" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2024 00:03:39 -0700 X-CSE-ConnectionGUID: o//TV7sPSwCAP8bUhd5A1A== X-CSE-MsgGUID: EH8EIMFBTty5I6uWA0m45A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="70235172" Received: from pglc00502.png.intel.com ([10.221.239.194]) by orviesa009.jf.intel.com with ESMTP; 20 Sep 2024 00:03:37 -0700 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Cc: Marek Vasut , Simon Goldschmidt , Meng Tingting , Yuslaimi Alif Zakuan , Hea Kok Kiang , Tien Fong Chee Subject: [PATCH v1 12/20] arm: socfpga: agilex5: Update CPU info Date: Fri, 20 Sep 2024 15:02:34 +0800 Message-Id: <20240920070242.20884-13-tien.fong.chee@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240920070242.20884-1-tien.fong.chee@intel.com> References: <20240920070242.20884-1-tien.fong.chee@intel.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Tien Fong Chee Update the print info per Agilex 5. Signed-off-by: Tien Fong Chee --- arch/arm/mach-socfpga/misc_soc64.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c index a6cc78454da..95e1c07e39f 100644 --- a/arch/arm/mach-socfpga/misc_soc64.c +++ b/arch/arm/mach-socfpga/misc_soc64.c @@ -45,7 +45,12 @@ static Altera_desc altera_fpga[] = { #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { - puts("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)\n"); + if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)) { + puts("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A55/A76)"); + puts("\n"); + } else { + puts("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)\n"); + } return 0; } From patchwork Fri Sep 20 07:02:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1987689 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=n4Mz/pph; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X93Mx1m7bz1y1t for ; Fri, 20 Sep 2024 17:06:37 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id F323F893AC; Fri, 20 Sep 2024 09:03:52 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="n4Mz/pph"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 1CDB1893A5; Fri, 20 Sep 2024 09:03:49 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id A0D2C89390 for ; Fri, 20 Sep 2024 09:03:42 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=tien.fong.chee@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1726815823; x=1758351823; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=eFef632lV/6w++PpMvECWwr7mE9Ep3UAwPOCUyRuyHc=; b=n4Mz/pphELp2/x6+/Jf5/7CajgW+R99CSUQ65fIMP4YYteyuDWuHHSMO UgXJtQXoUGRbVG/2mtDtC8qZdFnd7p2pipdrkz7fEKrq0iNgK4lVloJpg KtSgiiTeCz/4X8/ln62zCQd2wxWmBfbs5BAde4RZCFVvEzNtBGra/qJzc QLGmQNnqQGeBDOsQQtuygx9fqd/OmVLsiZuEr27GPe5i5A5YARnYpoIql qrAnXzJVRCMskY/47ivsgM1GAae+ZeMF8U8LKWlp1P0TkWlU+r5WFVfCy uWI4WH+FqeNQVxi8C/w5+36V6+2QAdrgk8rCgQod3t+DGtIlubTCU04/k w==; X-CSE-ConnectionGUID: O4wvN1z2QVmZ8M2n6IC+/Q== X-CSE-MsgGUID: k4G8sNSvQJ+WAaL6dLBlNw== X-IronPort-AV: E=McAfee;i="6700,10204,11200"; a="25961081" X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="25961081" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2024 00:03:41 -0700 X-CSE-ConnectionGUID: +WQ5RlXcQQScu72cn7hLuQ== X-CSE-MsgGUID: zkhQqpdMQ6aEXQUkGsLxAA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="70235204" Received: from pglc00502.png.intel.com ([10.221.239.194]) by orviesa009.jf.intel.com with ESMTP; 20 Sep 2024 00:03:39 -0700 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Cc: Marek Vasut , Simon Goldschmidt , Meng Tingting , Yuslaimi Alif Zakuan , Hea Kok Kiang , Tien Fong Chee Subject: [PATCH v1 13/20] arm: socfpga: Export board ID as U-Boot environment variable Date: Fri, 20 Sep 2024 15:02:35 +0800 Message-Id: <20240920070242.20884-14-tien.fong.chee@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240920070242.20884-1-tien.fong.chee@intel.com> References: <20240920070242.20884-1-tien.fong.chee@intel.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Tien Fong Chee Board ID is exported as environment variable for use to boot Linux with FIT configuration. Signed-off-by: Tien Fong Chee --- arch/arm/mach-socfpga/include/mach/misc.h | 1 + arch/arm/mach-socfpga/misc_soc64.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index 8460acb00d9..e62bea017b0 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -52,5 +52,6 @@ void set_regular_boot(unsigned int status); void socfpga_pl310_clear(void); void socfpga_get_managers_addr(void); int qspi_flash_software_reset(void); +u8 socfpga_get_board_id(void); #endif /* _SOCFPGA_MISC_H_ */ diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c index 95e1c07e39f..e34c54518a3 100644 --- a/arch/arm/mach-socfpga/misc_soc64.c +++ b/arch/arm/mach-socfpga/misc_soc64.c @@ -60,10 +60,15 @@ int print_cpuinfo(void) int arch_misc_init(void) { char qspi_string[13]; + char id[3]; sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz()); env_set("qspi_clock", qspi_string); + /* Export board_id as environment variable */ + sprintf(id, "%u", socfpga_get_board_id()); + env_set("board_id", id); + return 0; } #endif From patchwork Fri Sep 20 07:02:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1987688 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=Ils8l6Am; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X93Mj1Zb9z1y1t for ; Fri, 20 Sep 2024 17:06:25 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 83F88893B3; Fri, 20 Sep 2024 09:03:52 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Ils8l6Am"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id E9D52893A4; Fri, 20 Sep 2024 09:03:48 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 92AFB89391 for ; Fri, 20 Sep 2024 09:03:43 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=tien.fong.chee@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1726815824; x=1758351824; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=D013z8FWmJPvOnvaG82jSMXNAXKh3OHHToPv17LCfXM=; b=Ils8l6AmV7ddxoqyNA9Ae8pOih4jP+Hm1cyUMxW39eRaAINeW4GJa0op hR9o2iinrXYkoYK7UcspicRoSUv5AZq/4UIk0JdyFsIPmcnsN2xNe2qt4 zRoyllFuMd7fuYK6IxHzSGbyXhqCczNpHgnilQfEH75IVQPEJZ0bdbSiU loVE4z5sYm2w3HHR29mZaawk4garbrFdeHBZjIxleWZaswsjLUjxc3Q45 T7taEeto3PXBIYjsdYGF1ITO+axCdYP6z6TebN4eaxh7muvC112QTn28r v8byR4jOseTRk41MXi3B30dHJ3HWwzHNwtjy7UBYTmktoJBzV/cLfncGW w==; X-CSE-ConnectionGUID: Oi/waYTIS6OfsGo1iZXEzw== X-CSE-MsgGUID: rdK6duFJRRutUHJ9GAZUbw== X-IronPort-AV: E=McAfee;i="6700,10204,11200"; a="25961086" X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="25961086" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2024 00:03:43 -0700 X-CSE-ConnectionGUID: rKz4UdBlSlGkta/RhWbBcg== X-CSE-MsgGUID: 7zNdzsQHRHyOPnWJRZlXMQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="70235221" Received: from pglc00502.png.intel.com ([10.221.239.194]) by orviesa009.jf.intel.com with ESMTP; 20 Sep 2024 00:03:41 -0700 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Cc: Marek Vasut , Simon Goldschmidt , Meng Tingting , Yuslaimi Alif Zakuan , Hea Kok Kiang , Tien Fong Chee Subject: [PATCH v1 14/20] configs: agilex5: Add configuration for malloc pool Date: Fri, 20 Sep 2024 15:02:36 +0800 Message-Id: <20240920070242.20884-15-tien.fong.chee@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240920070242.20884-1-tien.fong.chee@intel.com> References: <20240920070242.20884-1-tien.fong.chee@intel.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Tien Fong Chee Adding configuration for SPL malloc pool. Signed-off-by: Tien Fong Chee --- configs/socfpga_agilex5_defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig index dc1cef3754e..81bbe967dcf 100644 --- a/configs/socfpga_agilex5_defconfig +++ b/configs/socfpga_agilex5_defconfig @@ -29,6 +29,10 @@ CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 initrd=0x90000000 root=/dev/ram0 rw init=/sbin/init ramdisk_size=10000000 earlycon panic=-1 nosmp kvm-arm.mode=nvhe" CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xbfa00000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x500000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_CACHE=y From patchwork Fri Sep 20 07:02:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1987687 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=HSwc+mb3; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X93MT4X0jz1y1t for ; Fri, 20 Sep 2024 17:06:13 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 1FB9389398; Fri, 20 Sep 2024 09:03:49 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="HSwc+mb3"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 667F3893A0; Fri, 20 Sep 2024 09:03:48 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 0C69289394 for ; Fri, 20 Sep 2024 09:03:45 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=tien.fong.chee@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1726815827; x=1758351827; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BCBe+N5WRh5SmVzCtd/poysuRUMIbYh8AH6JpKtCzEM=; b=HSwc+mb37UggA4K0sCAPc8BHIc6YmoTDJIX/62/doH3fZTO87dzBHKwR L+1+NvOTFIcsSmgHbng4/UQrAYbzqS9HdQopKCWILAIRlf1huyzFrsiiR 1ASmyn0HDgNp4dVcZ96np18O4SvFJwtD1VWl5PT3MNZnunYKNmJZSup0C H8X2b+FSCWfvD9YY1Wi3pcyGiAHMDKVDsCu3fdsWoD5pbWODVSIi8TR+T oO3a6YgCUL2vNezeQ0HtIgtlPuFIWvPpLhdyul3iPbT04RGXTROXitRrL BTDdig0Pp8vfwKiKYyypSmrkiX82NuGk+KctGY6FdfGkaQZ3ud9+zV8i9 w==; X-CSE-ConnectionGUID: EL+iePQFRAeWXLTpiofBIw== X-CSE-MsgGUID: xpRECENWREyoCm3wL8tupw== X-IronPort-AV: E=McAfee;i="6700,10204,11200"; a="25961096" X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="25961096" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2024 00:03:46 -0700 X-CSE-ConnectionGUID: G7f9pX2uTE6RQ7eC/tBapg== X-CSE-MsgGUID: NWInAH4bRQmnKL+lLFmRLQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="70235242" Received: from pglc00502.png.intel.com ([10.221.239.194]) by orviesa009.jf.intel.com with ESMTP; 20 Sep 2024 00:03:43 -0700 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Cc: Marek Vasut , Simon Goldschmidt , Meng Tingting , Yuslaimi Alif Zakuan , Hea Kok Kiang , Tien Fong Chee , Mahesh Rao Subject: [PATCH v1 15/20] arm: socfpga: smc: Add memory coherency support to mailbox command Date: Fri, 20 Sep 2024 15:02:37 +0800 Message-Id: <20240920070242.20884-16-tien.fong.chee@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240920070242.20884-1-tien.fong.chee@intel.com> References: <20240920070242.20884-1-tien.fong.chee@intel.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Tien Fong Chee As cache is enabled in U-Boot and disabled in ATF(BL31). We need to perform cache flush of buffers that are shared between U-Boot and ATF using secure monitor calls. Signed-off-by: Mahesh Rao Signed-off-by: Tien Fong Chee --- arch/arm/mach-socfpga/smc_api.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-socfpga/smc_api.c b/arch/arm/mach-socfpga/smc_api.c index ebaa0b8fa17..dac888c399f 100644 --- a/arch/arm/mach-socfpga/smc_api.c +++ b/arch/arm/mach-socfpga/smc_api.c @@ -1,9 +1,10 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2020 Intel Corporation + * Copyright (C) 2020-2024 Intel Corporation * */ +#include #include #include #include @@ -40,10 +41,16 @@ int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len, args[2] = len; args[3] = urgent; args[4] = (u64)resp_buf; - if (resp_buf_len) + + if (arg && len > 0) + flush_dcache_range((u64)arg, (u64)arg + len); + + if (resp_buf && resp_buf_len && *resp_buf_len > 0) { args[5] = *resp_buf_len; - else + flush_dcache_range((u64)resp_buf, (u64)resp_buf + *resp_buf_len); + } else { args[5] = 0; + } ret = invoke_smc(INTEL_SIP_SMC_MBOX_SEND_CMD, args, ARRAY_SIZE(args), resp, ARRAY_SIZE(resp)); From patchwork Fri Sep 20 07:02:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1987690 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=B+gAKqMN; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X93NC4g7jz1y1t for ; Fri, 20 Sep 2024 17:06:51 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 62FCC893B8; Fri, 20 Sep 2024 09:03:54 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="B+gAKqMN"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id BB53D893A9; Fri, 20 Sep 2024 09:03:52 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 78F9089323 for ; Fri, 20 Sep 2024 09:03:48 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=tien.fong.chee@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1726815829; x=1758351829; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ah+CHHDr29uPMrqE9LmnZNxx76hvxySACSE84a2KwE0=; b=B+gAKqMNqeqHkq62RMhf8ZRl4yT0b5iMEgb12OYLbuzg8fKJ4pL0ub+9 EfghaQ4hjIFNkB7qE5ennfFdp/veh8UCyfH7bgVY2YEkKvHgWCNMsX3/m EiOIQyo0xnkr6qoZvnycgbj0C+peplrTt8HlmfAIYU7f9/0cLRyi3u5E7 28HgNTVqAh3aFSskbZd/vZswcfcipZMatbC3E2l0rMsH9UakfdO+cH0i7 oGn1lNhQNnRwZYh9vxBzceALuTZl7RdOG/lSK+yAgiZqrvfxAYfeUqYRm j0ECHqXvL5ntrgvrqBjfF8xzhbzQrEsOhJgWZrQqye3G62PQ/qZOgQYa5 Q==; X-CSE-ConnectionGUID: 2Ec2NBsYSiK/ePpgT2iuTQ== X-CSE-MsgGUID: rtz7LDogRqiF6HOCTjBJkQ== X-IronPort-AV: E=McAfee;i="6700,10204,11200"; a="25961106" X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="25961106" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2024 00:03:48 -0700 X-CSE-ConnectionGUID: ix8JhReWSU2TIkQHUsg6eg== X-CSE-MsgGUID: nSFhGDX3QAy7HtB9eJ3f1Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="70235258" Received: from pglc00502.png.intel.com ([10.221.239.194]) by orviesa009.jf.intel.com with ESMTP; 20 Sep 2024 00:03:46 -0700 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Cc: Marek Vasut , Simon Goldschmidt , Meng Tingting , Yuslaimi Alif Zakuan , Hea Kok Kiang Subject: [PATCH v1 16/20] ddr: altera: Add DDR driver for Agilex5 series Date: Fri, 20 Sep 2024 15:02:38 +0800 Message-Id: <20240920070242.20884-17-tien.fong.chee@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240920070242.20884-1-tien.fong.chee@intel.com> References: <20240920070242.20884-1-tien.fong.chee@intel.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Tingting Meng Adding DDR driver support for Agilex5 series. Signed-off-by: Tingting Meng --- MAINTAINERS | 2 + arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 251 +++++++ arch/arm/dts/socfpga_agilex5.dtsi | 7 + arch/arm/mach-socfpga/include/mach/firewall.h | 23 +- drivers/ddr/altera/Makefile | 1 + drivers/ddr/altera/iossm_mailbox.c | 613 ++++++++++++++++++ drivers/ddr/altera/iossm_mailbox.h | 186 ++++++ drivers/ddr/altera/sdram_agilex5.c | 377 +++++++++++ drivers/ddr/altera/sdram_soc64.c | 78 ++- drivers/ddr/altera/sdram_soc64.h | 32 +- 10 files changed, 1547 insertions(+), 23 deletions(-) create mode 100644 drivers/ddr/altera/iossm_mailbox.c create mode 100644 drivers/ddr/altera/iossm_mailbox.h create mode 100644 drivers/ddr/altera/sdram_agilex5.c diff --git a/MAINTAINERS b/MAINTAINERS index 2050ae24df8..1837d283b2f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -146,8 +146,10 @@ ARM ALTERA SOCFPGA M: Marek Vasut M: Simon Goldschmidt M: Tien Fong Chee +M: Tingting Meng S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-socfpga.git +F: drivers/ddr/altera/ F: arch/arm/mach-socfpga/ F: drivers/sysreset/sysreset_socfpga* diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi index 9baf2cbc525..1209a8da4b9 100644 --- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi @@ -388,6 +388,230 @@ }; }; + socfpga_ccu_ddr_interleaving_off: socfpga-ccu-ddr-interleaving-off { + compatible = "intel,socfpga-dtreg"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + /* DSU */ + i_ccu_caiu0@1c000000 { + reg = <0x1c000000 0x00001000>; + intel,offset-settings = + /* CAIUAMIGR */ + <0x000003c0 0x00000003 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81300006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81700006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81b00006 0xc1f03e1f>; + bootph-all; + }; + + /* FPGA2SOC */ + i_ccu_ncaiu0@1c001000 { + reg = <0x1c001000 0x00001000>; + intel,offset-settings = + /* NCAIU0AMIGR */ + <0x000003c0 0x00000003 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81300006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81700006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81b00006 0xc1f03e1f>; + bootph-all; + }; + + /* GIC_M */ + i_ccu_ncaiu1@1c002000 { + reg = <0x1c002000 0x00001000>; + intel,offset-settings = + /* NCAIU1AMIGR */ + <0x000003c0 0x00000003 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81300006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81700006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81b00006 0xc1f03e1f>; + bootph-all; + }; + + /* SMMU */ + i_ccu_ncaiu2@1c003000 { + reg = <0x1c003000 0x00001000>; + intel,offset-settings = + /* NCAIU2AMIGR */ + <0x000003c0 0x00000003 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81300006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81700006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81b00006 0xc1f03e1f>; + bootph-all; + }; + + /* PSS NOC */ + i_ccu_ncaiu3@1c004000 { + reg = <0x1c004000 0x00001000>; + intel,offset-settings = + /* NCAIU3AMIGR */ + <0x000003c0 0x00000003 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81300006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81700006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81b00006 0xc1f03e1f>; + bootph-all; + }; + + /* DCE0 */ + i_ccu_dce0@1c005000 { + reg = <0x1c005000 0x00001000>; + intel,offset-settings = + /* DCEUAMIGR0 */ + <0x000003c0 0x00000003 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81300006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81700006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81b00006 0xc1f03e1f>; + bootph-all; + }; + + /* DCE1 */ + i_ccu_dce1@1c006000 { + reg = <0x1c006000 0x00001000>; + intel,offset-settings = + /* DCEUAMIGR1 */ + <0x000003c0 0x00000003 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81300006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81700006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81b00006 0xc1f03e1f>; + bootph-all; + }; + }; + + socfpga_ccu_ddr_interleaving_on: socfpga-ccu-ddr-interleaving-on { + compatible = "intel,socfpga-dtreg"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + /* DSU */ + i_ccu_caiu0@1c000000 { + reg = <0x1c000000 0x00001000>; + intel,offset-settings = + /* CAIUAMIGR */ + <0x000003c0 0x00000001 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81200006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81600006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81a00006 0xc1f03e1f>; + bootph-all; + }; + + /* FPGA2SOC */ + i_ccu_ncaiu0@1c001000 { + reg = <0x1c001000 0x00001000>; + intel,offset-settings = + /* NCAIU0AMIGR */ + <0x000003c0 0x00000001 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81200006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81600006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81a00006 0xc1f03e1f>; + bootph-all; + }; + + /* GIC_M */ + i_ccu_ncaiu1@1c002000 { + reg = <0x1c002000 0x00001000>; + intel,offset-settings = + /* NCAIU1AMIGR */ + <0x000003c0 0x00000001 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81200006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81600006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81a00006 0xc1f03e1f>; + bootph-all; + }; + + /* SMMU */ + i_ccu_ncaiu2@1c003000 { + reg = <0x1c003000 0x00001000>; + intel,offset-settings = + /* NCAIU2AMIGR */ + <0x000003c0 0x00000001 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81200006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81600006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81a00006 0xc1f03e1f>; + bootph-all; + }; + + /* PSS NOC */ + i_ccu_ncaiu3@1c004000 { + reg = <0x1c004000 0x00001000>; + intel,offset-settings = + /* NCAIU3AMIGR */ + <0x000003c0 0x00000001 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81200006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81600006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81a00006 0xc1f03e1f>; + bootph-all; + }; + + /* DCE0 */ + i_ccu_dce0@1c005000 { + reg = <0x1c005000 0x00001000>; + intel,offset-settings = + /* DCEUAMIGR0 */ + <0x000003c0 0x00000001 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81200006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81600006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81a00006 0xc1f03e1f>; + bootph-all; + }; + + /* DCE1 */ + i_ccu_dce1@1c006000 { + reg = <0x1c006000 0x00001000>; + intel,offset-settings = + /* DCEUAMIGR1 */ + <0x000003c0 0x00000001 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81200006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81600006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81a00006 0xc1f03e1f>; + bootph-all; + }; + }; + socfpga_smmu_secure_config: socfpga-smmu-secure-config { compatible = "intel,socfpga-dtreg"; #address-cells = <1>; @@ -421,6 +645,26 @@ bootph-all; }; }; + + socfpga_noc_fw_mpfe_csr: socfpga-noc-fw-mpfe-csr { + compatible = "intel,socfpga-dtreg"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + /* noc fw mpfe csr */ + i_noc_fw_mpfe_csr@18000d00 { + reg = <0x18000d00 0x00000100>; + intel,offset-settings = + /* mpfe scr io96b0 reg*/ + <0x00000000 0x00000001 0x00010101>, + /* mpfe scr io96b1 reg*/ + <0x00000004 0x00000001 0x00010101>, + /* mpfe scr noc csr*/ + <0x00000008 0x00000001 0x00010101>; + bootph-all; + }; + }; }; }; @@ -466,6 +710,13 @@ bootph-all; }; +&sdr { + compatible = "intel,sdr-ctl-agilex5"; + reg = <0x18000000 0x400000>; + resets = <&rst DDRSCH_RESET>; + bootph-all; +}; + &sysmgr { compatible = "altr,sys-mgr", "syscon"; bootph-all; diff --git a/arch/arm/dts/socfpga_agilex5.dtsi b/arch/arm/dts/socfpga_agilex5.dtsi index 03b55040497..4f17d8fc21e 100644 --- a/arch/arm/dts/socfpga_agilex5.dtsi +++ b/arch/arm/dts/socfpga_agilex5.dtsi @@ -544,6 +544,13 @@ status = "disabled"; }; + sdr: sdr@18000000 { + compatible = "intel,sdr-ctl-agilex5"; + reg = <0x18000000 0x400000>; + resets = <&rst DDRSCH_RESET>; + bootph-all; + }; + /* QSPI address not available yet */ qspi: spi@108d2000 { compatible = "cdns,qspi-nor"; diff --git a/arch/arm/mach-socfpga/include/mach/firewall.h b/arch/arm/mach-socfpga/include/mach/firewall.h index 5cb7f23f8f0..9c3f3313af6 100644 --- a/arch/arm/mach-socfpga/include/mach/firewall.h +++ b/arch/arm/mach-socfpga/include/mach/firewall.h @@ -1,7 +1,6 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * Copyright (C) 2017-2019 Intel Corporation - * +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2017-2024 Intel Corporation */ #ifndef _FIREWALL_H_ @@ -126,11 +125,27 @@ struct socfpga_firwall_l4_sys { #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT 0x9c #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_FIELD 0xff +/* Firewall F2SDRAM DDR SCR registers */ +#define FW_F2SDRAM_DDR_SCR_EN 0x00 +#define FW_F2SDRAM_DDR_SCR_EN_SET 0x04 +#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_BASE 0x10 +#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_BASEEXT 0x14 +#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_LIMIT 0x18 +#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_LIMITEXT 0x1c + #define MPUREGION0_ENABLE BIT(0) #define NONMPUREGION0_ENABLE BIT(8) +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define FW_MPU_DDR_SCR_WRITEL(data, reg) \ + writel(data, SOCFPGA_FW_DDR_CCU_DMI0_ADDRESS + (reg)); \ + writel(data, SOCFPGA_FW_DDR_CCU_DMI1_ADDRESS + (reg)) +#define FW_F2SDRAM_DDR_SCR_WRITEL(data, reg) \ + writel(data, SOCFPGA_FW_TBU2NOC_ADDRESS + (reg)) +#else #define FW_MPU_DDR_SCR_WRITEL(data, reg) \ writel(data, SOCFPGA_FW_MPU_DDR_SCR_ADDRESS + (reg)) +#endif void firewall_setup(void); diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile index 9fa5d85a27e..117868b6d01 100644 --- a/drivers/ddr/altera/Makefile +++ b/drivers/ddr/altera/Makefile @@ -12,4 +12,5 @@ obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += sdram_soc64.o sdram_agilex.o obj-$(CONFIG_TARGET_SOCFPGA_N5X) += sdram_soc64.o sdram_n5x.o +obj-$(CONFIG_TARGET_SOCFPGA_AGILEX5) += sdram_soc64.o sdram_agilex5.o iossm_mailbox.o endif diff --git a/drivers/ddr/altera/iossm_mailbox.c b/drivers/ddr/altera/iossm_mailbox.c new file mode 100644 index 00000000000..5e76246dcca --- /dev/null +++ b/drivers/ddr/altera/iossm_mailbox.c @@ -0,0 +1,613 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Intel Corporation + */ + +#include +#include +#include +#include +#include +#include +#include "iossm_mailbox.h" + +#define ECC_INTSTATUS_SERR SOCFPGA_SYSMGR_ADDRESS + 0x9C +#define ECC_INISTATUS_DERR SOCFPGA_SYSMGR_ADDRESS + 0xA0 +#define ECC_UNCONRRECTABLE_ERROR_MASK \ + BIT(2) + BIT(3) + BIT(6) + BIT(10) + BIT(12) + BIT(13) +#define DDR_CSR_CLKGEN_LOCKED_IO96B0_MASK BIT(16) +#define DDR_CSR_CLKGEN_LOCKED_IO96B1_MASK BIT(17) + +#define IO96B_MB_REQ_SETUP(v, w, x, y, z) \ + usr_req.ip_type = v; \ + usr_req.ip_id = w; \ + usr_req.usr_cmd_type = x; \ + usr_req.usr_cmd_opcode = y; \ + usr_req.cmd_param[0] = z; \ + for (n = 1; n < NUM_CMD_PARAM; n++) \ + usr_req.cmd_param[n] = 0 +#define MAX_RETRY_COUNT 3 +#define NUM_CMD_RESPONSE_DATA 3 + +#define IO96B0_PLL_A_MASK BIT(0) +#define IO96B0_PLL_B_MASK BIT(1) +#define IO96B1_PLL_A_MASK BIT(2) +#define IO96B1_PLL_B_MASK BIT(3) + +/* supported DDR type list */ +static const char *ddr_type_list[7] = { + "DDR4", "DDR5", "DDR5_RDIMM", "LPDDR4", "LPDDR5", "QDRIV", "UNKNOWN" +}; + +static int is_ddr_csr_clkgen_locked(u8 io96b_pll) +{ + int ret = 0; + const char *pll_names[MAX_IO96B_SUPPORTED][2] = { + {"io96b_0 clkgenA", "io96b_0 clkgenB"}, + {"io96b_1 clkgenA", "io96b_1 clkgenB"} + }; + u32 masks[MAX_IO96B_SUPPORTED][2] = { + {IO96B0_PLL_A_MASK, IO96B0_PLL_B_MASK}, + {IO96B1_PLL_A_MASK, IO96B1_PLL_B_MASK} + }; + u32 lock_masks[MAX_IO96B_SUPPORTED] = { + DDR_CSR_CLKGEN_LOCKED_IO96B0_MASK, + DDR_CSR_CLKGEN_LOCKED_IO96B1_MASK + }; + + for (int i = 0; i < MAX_IO96B_SUPPORTED ; i++) { + /* Check for PLL_A */ + if (io96b_pll & masks[i][0]) { + ret = wait_for_bit_le32((const void *)(ECC_INTSTATUS_SERR), lock_masks[i], + true, TIMEOUT, false); + + if (ret) { + debug("%s: ddr csr %s locked is timeout\n", + __func__, pll_names[i][0]); + goto err; + } else { + debug("%s: ddr csr %s is successfully locked\n", + __func__, pll_names[i][0]); + } + } + + /* Check for PLL_B */ + if (io96b_pll & masks[i][1]) { + ret = wait_for_bit_le32((const void *)(ECC_INISTATUS_DERR), lock_masks[i], + true, TIMEOUT, false); + + if (ret) { + debug("%s: ddr csr %s locked is timeout\n", + __func__, pll_names[i][1]); + goto err; + } else { + debug("%s: ddr csr %s is successfully locked\n", + __func__, pll_names[i][1]); + } + } + } + +err: + return ret; +} + +/* + * Mailbox request function + * This function will send the request to IOSSM mailbox and wait for response return + * + * @io96b_csr_addr: CSR address for the target IO96B + * @req: Structure contain command request for IOSSM mailbox command + * @resp_data_len: User desire extra response data fields other than + * CMD_RESPONSE_DATA_SHORT field on CMD_RESPONSE_STATUS + * @resp: Structure contain responses returned from the requested IOSSM + * mailbox command + */ +int io96b_mb_req(phys_addr_t io96b_csr_addr, struct io96b_mb_req req, + u32 resp_data_len, struct io96b_mb_resp *resp) +{ + int i, ret; + u32 cmd_req; + + if (!resp) { + ret = -EINVAL; + goto err; + } + + /* Zero initialization for responses */ + resp->cmd_resp_status = 0; + + /* Ensure CMD_REQ is cleared before write any command request */ + ret = wait_for_bit_le32((const void *)(io96b_csr_addr + IOSSM_CMD_REQ_OFFSET), + GENMASK(31, 0), false, TIMEOUT, false); + if (ret) { + printf("%s: Timeout of waiting DDR mailbox ready to be functioned!\n", + __func__); + goto err; + } + + /* Write CMD_PARAM_* */ + for (i = 0; i < NUM_CMD_PARAM ; i++) { + switch (i) { + case 0: + if (req.cmd_param[0]) + writel(req.cmd_param[0], io96b_csr_addr + IOSSM_CMD_PARAM_0_OFFSET); + break; + case 1: + if (req.cmd_param[1]) + writel(req.cmd_param[1], io96b_csr_addr + IOSSM_CMD_PARAM_1_OFFSET); + break; + case 2: + if (req.cmd_param[2]) + writel(req.cmd_param[2], io96b_csr_addr + IOSSM_CMD_PARAM_2_OFFSET); + break; + case 3: + if (req.cmd_param[3]) + writel(req.cmd_param[3], io96b_csr_addr + IOSSM_CMD_PARAM_3_OFFSET); + break; + case 4: + if (req.cmd_param[4]) + writel(req.cmd_param[4], io96b_csr_addr + IOSSM_CMD_PARAM_4_OFFSET); + break; + case 5: + if (req.cmd_param[5]) + writel(req.cmd_param[5], io96b_csr_addr + IOSSM_CMD_PARAM_5_OFFSET); + break; + case 6: + if (req.cmd_param[6]) + writel(req.cmd_param[6], io96b_csr_addr + IOSSM_CMD_PARAM_6_OFFSET); + break; + default: + printf("%s: Invalid command parameter\n", __func__); + } + } + + /* Write CMD_REQ (IP_TYPE, IP_INSTANCE_ID, CMD_TYPE and CMD_OPCODE) */ + cmd_req = FIELD_PREP(CMD_TARGET_IP_TYPE_MASK, req.ip_type) | + FIELD_PREP(CMD_TARGET_IP_INSTANCE_ID_MASK, req.ip_id) | + FIELD_PREP(CMD_TYPE_MASK, req.usr_cmd_type) | + FIELD_PREP(CMD_OPCODE_MASK, req.usr_cmd_opcode); + writel(cmd_req, io96b_csr_addr + IOSSM_CMD_REQ_OFFSET); + + debug("%s: Write 0x%x to IOSSM_CMD_REQ_OFFSET 0x%llx\n", __func__, cmd_req, + io96b_csr_addr + IOSSM_CMD_REQ_OFFSET); + + /* Read CMD_RESPONSE_READY in CMD_RESPONSE_STATUS */ + ret = wait_for_bit_le32((const void *)(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET), + IOSSM_STATUS_COMMAND_RESPONSE_READY, true, TIMEOUT, false); + + /* read CMD_RESPONSE_STATUS */ + resp->cmd_resp_status = readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET); + + debug("%s: CMD_RESPONSE_STATUS 0x%llx: 0x%x\n", __func__, io96b_csr_addr + + IOSSM_CMD_RESPONSE_STATUS_OFFSET, resp->cmd_resp_status); + + if (ret) { + printf("%s: CMD_RESPONSE ERROR:\n", __func__); + + printf("%s: STATUS_GENERAL_ERROR: 0x%lx\n", __func__, + IOSSM_STATUS_GENERAL_ERROR(resp->cmd_resp_status)); + printf("%s: STATUS_CMD_RESPONSE_ERROR: 0x%lx\n", __func__, + IOSSM_STATUS_CMD_RESPONSE_ERROR(resp->cmd_resp_status)); + goto err; + } + + /* read CMD_RESPONSE_DATA_* */ + for (i = 0; i < resp_data_len; i++) { + switch (i) { + case 0: + resp->cmd_resp_data[i] = + readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_0_OFFSET); + + debug("%s: IOSSM_CMD_RESPONSE_DATA_0_OFFSET 0x%llx: 0x%x\n", __func__, + io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_0_OFFSET, + resp->cmd_resp_data[i]); + break; + case 1: + resp->cmd_resp_data[i] = + readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_1_OFFSET); + + debug("%s: IOSSM_CMD_RESPONSE_DATA_1_OFFSET 0x%llx: 0x%x\n", __func__, + io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_1_OFFSET, + resp->cmd_resp_data[i]); + break; + case 2: + resp->cmd_resp_data[i] = + readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_2_OFFSET); + + debug("%s: IOSSM_CMD_RESPONSE_DATA_2_OFFSET 0x%llx: 0x%x\n", __func__, + io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_2_OFFSET, + resp->cmd_resp_data[i]); + break; + default: + resp->cmd_resp_data[i] = 0; + printf("%s: Invalid response data\n", __func__); + } + } + + /* write CMD_RESPONSE_READY = 0 */ + clrbits_le32((u32 *)(uintptr_t)(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET), + IOSSM_STATUS_COMMAND_RESPONSE_READY); + + debug("%s: After clear CMD_RESPONSE_READY bit: 0x%llx: 0x%x\n", __func__, + io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET, + readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET)); + +err: + return ret; +} + +/* + * Initial function to be called to set memory interface IP type and instance ID + * IP type and instance ID need to be determined before sending mailbox command + */ +void io96b_mb_init(struct io96b_info *io96b_ctrl) +{ + struct io96b_mb_req usr_req; + struct io96b_mb_resp usr_resp; + u8 ip_type_ret, instance_id_ret; + int i, j, k, n, ret; + + debug("%s: num_instance %d\n", __func__, io96b_ctrl->num_instance); + + for (i = 0; i < io96b_ctrl->num_instance; i++) { + debug("%s: get memory interface IO96B %d\n", __func__, i); + + IO96B_MB_REQ_SETUP(0, 0, CMD_GET_SYS_INFO, GET_MEM_INTF_INFO, 0); + + /* Get memory interface IP type and instance ID (IP identifier) */ + ret = io96b_mb_req(io96b_ctrl->io96b[i].io96b_csr_addr, usr_req, 2, &usr_resp); + if (ret) { + printf("%s: get memory interface IO96B %d failed\n", __func__, i); + hang(); + } + + debug("%s: get response from memory interface IO96B %d\n", __func__, i); + + /* Retrieve number of memory interface(s) */ + io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface = + IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) & 0x3; + + debug("%s: IO96B %d: num_mem_interface: 0x%x\n", __func__, i, + io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface); + + /* Retrieve memory interface IP type and instance ID (IP identifier) */ + j = 0; + for (k = 0; k < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; k++) { + ip_type_ret = FIELD_GET(INTF_IP_TYPE_MASK, usr_resp.cmd_resp_data[k]); + instance_id_ret = FIELD_GET(INTF_INSTANCE_ID_MASK, + usr_resp.cmd_resp_data[k]); + + if (ip_type_ret) { + io96b_ctrl->io96b[i].mb_ctrl.ip_type[j] = ip_type_ret; + io96b_ctrl->io96b[i].mb_ctrl.ip_id[j] = instance_id_ret; + + debug("%s: IO96B %d mem_interface %d: ip_type_ret: 0x%x\n", + __func__, i, j, ip_type_ret); + debug("%s: IO96B %d mem_interface %d: instance_id_ret: 0x%x\n", + __func__, i, j, instance_id_ret); + + j++; + } + } + } +} + +int io96b_cal_status(phys_addr_t addr) +{ + u32 cal_success, cal_fail; + phys_addr_t status_addr = addr + IOSSM_STATUS_OFFSET; + u32 start = get_timer(0); + + do { + if (get_timer(start) > TIMEOUT_60000MS) { + printf("%s: SDRAM calibration for IO96B instance 0x%llx timeout!\n", + __func__, status_addr); + hang(); + } + + udelay(1); + schedule(); + + /* Polling until getting any calibration result */ + cal_success = readl(status_addr) & IOSSM_STATUS_CAL_SUCCESS; + cal_fail = readl(status_addr) & IOSSM_STATUS_CAL_FAIL; + } while (!cal_success && !cal_fail); + + debug("%s: Calibration for IO96B instance 0x%llx done at %ld msec!\n", + __func__, status_addr, get_timer(start)); + + if (cal_success && !cal_fail) + return 0; + else + return -EPERM; +} + +void init_mem_cal(struct io96b_info *io96b_ctrl) +{ + int count, i, ret; + + /* Initialize overall calibration status */ + io96b_ctrl->overall_cal_status = false; + + if (io96b_ctrl->ckgen_lock) { + ret = is_ddr_csr_clkgen_locked(io96b_ctrl->io96b_pll); + if (ret) { + printf("%s: iossm IO96B ckgena_lock is not locked\n", __func__); + hang(); + } + } + + /* Check initial calibration status for the assigned IO96B */ + count = 0; + for (i = 0; i < io96b_ctrl->num_instance; i++) { + ret = io96b_cal_status(io96b_ctrl->io96b[i].io96b_csr_addr); + if (ret) { + io96b_ctrl->io96b[i].cal_status = false; + + printf("%s: Initial DDR calibration IO96B_%d failed %d\n", __func__, + i, ret); + + hang(); + } + + io96b_ctrl->io96b[i].cal_status = true; + + printf("%s: Initial DDR calibration IO96B_%d succeed\n", __func__, i); + + count++; + } + + if (count == io96b_ctrl->num_instance) + io96b_ctrl->overall_cal_status = true; +} + +int get_mem_technology(struct io96b_info *io96b_ctrl) +{ + struct io96b_mb_req usr_req; + struct io96b_mb_resp usr_resp; + int i, j, n, ret = 0; + u8 ddr_type_ret; + + /* Initialize ddr type */ + io96b_ctrl->ddr_type = ddr_type_list[6]; + + /* Get and ensure all memory interface(s) same DDR type */ + for (i = 0; i < io96b_ctrl->num_instance; i++) { + for (j = 0; j < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; j++) { + IO96B_MB_REQ_SETUP(io96b_ctrl->io96b[i].mb_ctrl.ip_type[j], + io96b_ctrl->io96b[i].mb_ctrl.ip_id[j], + CMD_GET_MEM_INFO, GET_MEM_TECHNOLOGY, 0); + + ret = io96b_mb_req(io96b_ctrl->io96b[i].io96b_csr_addr, usr_req, + 0, &usr_resp); + + if (ret) + goto err; + + ddr_type_ret = + IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) + & GENMASK(2, 0); + + if (!strcmp(io96b_ctrl->ddr_type, "UNKNOWN")) + io96b_ctrl->ddr_type = ddr_type_list[ddr_type_ret]; + + if (ddr_type_list[ddr_type_ret] != io96b_ctrl->ddr_type) { + printf("%s: Mismatch DDR type on IO96B_%d\n", __func__, i); + + ret = -EINVAL; + goto err; + } + } + } + +err: + return ret; +} + +int get_mem_width_info(struct io96b_info *io96b_ctrl) +{ + struct io96b_mb_req usr_req; + struct io96b_mb_resp usr_resp; + int i, j, n, ret = 0; + u16 memory_size; + u16 total_memory_size = 0; + + /* Get all memory interface(s) total memory size on all instance(s) */ + for (i = 0; i < io96b_ctrl->num_instance; i++) { + memory_size = 0; + for (j = 0; j < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; j++) { + IO96B_MB_REQ_SETUP(io96b_ctrl->io96b[i].mb_ctrl.ip_type[j], + io96b_ctrl->io96b[i].mb_ctrl.ip_id[j], + CMD_GET_MEM_INFO, GET_MEM_WIDTH_INFO, 0); + + ret = io96b_mb_req(io96b_ctrl->io96b[i].io96b_csr_addr, usr_req, + 2, &usr_resp); + + if (ret) + goto err; + + memory_size = memory_size + + (usr_resp.cmd_resp_data[1] & GENMASK(7, 0)); + } + + if (!memory_size) { + printf("%s: Failed to get valid memory size\n", __func__); + ret = -EINVAL; + goto err; + } + + io96b_ctrl->io96b[i].size = memory_size; + + total_memory_size = total_memory_size + memory_size; + } + + if (!total_memory_size) { + printf("%s: Failed to get valid memory size\n", __func__); + ret = -EINVAL; + } + + io96b_ctrl->overall_size = total_memory_size; + +err: + return ret; +} + +int ecc_enable_status(struct io96b_info *io96b_ctrl) +{ + struct io96b_mb_req usr_req; + struct io96b_mb_resp usr_resp; + int i, j, n, ret = 0; + bool ecc_stat_set = false; + bool ecc_stat; + + /* Initialize ECC status */ + io96b_ctrl->ecc_status = false; + + /* Get and ensure all memory interface(s) same ECC status */ + for (i = 0; i < io96b_ctrl->num_instance; i++) { + for (j = 0; j < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; j++) { + IO96B_MB_REQ_SETUP(io96b_ctrl->io96b[i].mb_ctrl.ip_type[j], + io96b_ctrl->io96b[i].mb_ctrl.ip_id[j], + CMD_TRIG_CONTROLLER_OP, ECC_ENABLE_STATUS, 0); + + ret = io96b_mb_req(io96b_ctrl->io96b[i].io96b_csr_addr, + usr_req, 0, &usr_resp); + + if (ret) + goto err; + + ecc_stat = (IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) + & GENMASK(1, 0)) == 0 ? false : true; + + if (!ecc_stat_set) { + io96b_ctrl->ecc_status = ecc_stat; + ecc_stat_set = true; + } + + if (ecc_stat != io96b_ctrl->ecc_status) { + printf("%s: Mismatch DDR ECC status on IO96B_%d\n", __func__, i); + + ret = -EINVAL; + goto err; + } + } + } + + debug("%s: ECC enable status: %d\n", __func__, io96b_ctrl->ecc_status); + +err: + return ret; +} + +int ecc_interrupt_status(struct io96b_info *io96b_ctrl, bool *ecc_error_flag) +{ + struct io96b_mb_req usr_req; + struct io96b_mb_resp usr_resp; + int i, j, n, ret = 0; + u32 uncorrectable_error; + + for (i = 0; i < io96b_ctrl->num_instance; i++) { + for (j = 0; j < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; j++) { + IO96B_MB_REQ_SETUP(io96b_ctrl->io96b[i].mb_ctrl.ip_type[j], + io96b_ctrl->io96b[i].mb_ctrl.ip_id[j], + CMD_TRIG_CONTROLLER_OP, ECC_INTERRUPT_STATUS, 0); + + ret = io96b_mb_req(io96b_ctrl->io96b[i].io96b_csr_addr, + usr_req, 1, &usr_resp); + + if (ret) + goto err; + + uncorrectable_error = (usr_resp.cmd_resp_data[0]) & + (ECC_UNCONRRECTABLE_ERROR_MASK); + debug("%s: IO96B %d mem_interface %d: ECC error status:0x%08x\n", + __func__, i, j, uncorrectable_error); + + if (uncorrectable_error) { + *ecc_error_flag = true; + printf("DDR: ECC un-correctable error detected on IO96B_%d\n", + i); + goto err; + } + } + } + + *ecc_error_flag = false; + +err: + return ret; +} + +int bist_mem_init_start(struct io96b_info *io96b_ctrl) +{ + struct io96b_mb_req usr_req; + struct io96b_mb_resp usr_resp; + int i, j, n, ret = 0; + bool bist_start, bist_success; + u32 start; + + /* Full memory initialization BIST performed on all memory interface(s) */ + for (i = 0; i < io96b_ctrl->num_instance; i++) { + for (j = 0; j < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; j++) { + bist_start = false; + bist_success = false; + + /* Start memory initialization BIST on full memory address */ + IO96B_MB_REQ_SETUP(io96b_ctrl->io96b[i].mb_ctrl.ip_type[j], + io96b_ctrl->io96b[i].mb_ctrl.ip_id[j], + CMD_TRIG_CONTROLLER_OP, BIST_MEM_INIT_START, + BIST_FULL_MEM); + + ret = io96b_mb_req(io96b_ctrl->io96b[i].io96b_csr_addr, + usr_req, 0, &usr_resp); + if (ret) + goto err; + + bist_start = IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) + & BIT(0); + + if (!bist_start) { + printf("%s: Failed to initialize memory on IO96B_%d\n", __func__, + i); + printf("%s: BIST_MEM_INIT_START Error code 0x%lx\n", __func__, + IOSSM_STATUS_CMD_RESPONSE_ERROR(usr_resp.cmd_resp_status)); + + ret = -EINVAL; + goto err; + } + + /* Polling for the initiated memory initialization BIST status */ + start = get_timer(0); + while (!bist_success) { + IO96B_MB_REQ_SETUP(io96b_ctrl->io96b[i].mb_ctrl.ip_type[j], + io96b_ctrl->io96b[i].mb_ctrl.ip_id[j], + CMD_TRIG_CONTROLLER_OP, BIST_MEM_INIT_STATUS, 0); + + io96b_mb_req(io96b_ctrl->io96b[i].io96b_csr_addr, usr_req, 0, + &usr_resp); + + bist_success = + IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) + & BIT(0); + + if (!bist_success && (get_timer(start) > TIMEOUT)) { + printf("%s: Timeout initialize memory on IO96B_%d\n", + __func__, i); + printf("%s: BIST_MEM_INIT_STATUS Error code 0x%lx\n", + __func__, + IOSSM_STATUS_CMD_RESPONSE_ERROR(usr_resp.cmd_resp_status)); + + ret = -ETIMEDOUT; + goto err; + } + + udelay(1); + } + } + + debug("%s: Memory initialized successfully on IO96B_%d\n", __func__, i); + } + +err: + return ret; +} diff --git a/drivers/ddr/altera/iossm_mailbox.h b/drivers/ddr/altera/iossm_mailbox.h new file mode 100644 index 00000000000..49320f8211b --- /dev/null +++ b/drivers/ddr/altera/iossm_mailbox.h @@ -0,0 +1,186 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2024 Intel Corporation + */ + +#define TIMEOUT_120000MS 120000 +#define TIMEOUT_60000MS 60000 +#define TIMEOUT TIMEOUT_120000MS +#define IOSSM_STATUS_CAL_SUCCESS BIT(0) +#define IOSSM_STATUS_CAL_FAIL BIT(1) +#define IOSSM_STATUS_CAL_BUSY BIT(2) +#define IOSSM_STATUS_COMMAND_RESPONSE_READY BIT(0) +#define IOSSM_CMD_RESPONSE_STATUS_OFFSET 0x45C +#define IOSSM_CMD_RESPONSE_DATA_0_OFFSET 0x458 +#define IOSSM_CMD_RESPONSE_DATA_1_OFFSET 0x454 +#define IOSSM_CMD_RESPONSE_DATA_2_OFFSET 0x450 +#define IOSSM_CMD_REQ_OFFSET 0x43C +#define IOSSM_CMD_PARAM_0_OFFSET 0x438 +#define IOSSM_CMD_PARAM_1_OFFSET 0x434 +#define IOSSM_CMD_PARAM_2_OFFSET 0x430 +#define IOSSM_CMD_PARAM_3_OFFSET 0x42C +#define IOSSM_CMD_PARAM_4_OFFSET 0x428 +#define IOSSM_CMD_PARAM_5_OFFSET 0x424 +#define IOSSM_CMD_PARAM_6_OFFSET 0x420 +#define IOSSM_STATUS_OFFSET 0x400 +#define IOSSM_CMD_RESPONSE_DATA_SHORT_MASK GENMASK(31, 16) +#define IOSSM_CMD_RESPONSE_DATA_SHORT(n) FIELD_GET(IOSSM_CMD_RESPONSE_DATA_SHORT_MASK, n) +#define IOSSM_STATUS_CMD_RESPONSE_ERROR_MASK GENMASK(7, 5) +#define IOSSM_STATUS_CMD_RESPONSE_ERROR(n) FIELD_GET(IOSSM_STATUS_CMD_RESPONSE_ERROR_MASK, n) +#define IOSSM_STATUS_GENERAL_ERROR_MASK GENMASK(4, 1) +#define IOSSM_STATUS_GENERAL_ERROR(n) FIELD_GET(IOSSM_STATUS_GENERAL_ERROR_MASK, n) +#define MAX_IO96B_SUPPORTED 2 +#define NUM_CMD_RESPONSE_DATA 3 +#define NUM_CMD_PARAM 6 + +/* supported mailbox command type */ +enum iossm_mailbox_cmd_type { + CMD_NOP, + CMD_GET_SYS_INFO, + CMD_GET_MEM_INFO, + CMD_GET_MEM_CAL_INFO, + CMD_TRIG_CONTROLLER_OP, + CMD_TRIG_MEM_CAL_OP +}; + +/* supported mailbox command opcode */ +enum iossm_mailbox_cmd_opcode { + GET_MEM_INTF_INFO = 0x0001, + GET_MEM_TECHNOLOGY, + GET_MEMCLK_FREQ_KHZ, + GET_MEM_WIDTH_INFO, + ECC_ENABLE_SET = 0x0101, + ECC_ENABLE_STATUS, + ECC_INTERRUPT_STATUS, + ECC_INTERRUPT_ACK, + ECC_INTERRUPT_MASK, + ECC_WRITEBACK_ENABLE, + ECC_GET_SBE_INFO, + ECC_GET_DBE_INFO, + ECC_INJECT_ERROR, + ECC_SCRUB_IN_PROGRESS_STATUS = 0x0201, + ECC_SCRUB_MODE_0_START, + ECC_SCRUB_MODE_1_START, + BIST_STANDARD_MODE_START = 0x0301, + BIST_RESULTS_STATUS, + BIST_MEM_INIT_START, + BIST_MEM_INIT_STATUS, + BIST_SET_DATA_PATTERN_UPPER, + BIST_SET_DATA_PATTERN_LOWER, + TRIG_MEM_CAL = 0x000a, + GET_MEM_CAL_STATUS +}; + +/* response data of cmd opcode GET_MEM_INTF_INFO */ +#define INTF_IP_TYPE_MASK GENMASK(31, 29) +#define INTF_INSTANCE_ID_MASK GENMASK(28, 24) + +/* response data of cmd opcode GET_MEM_CAL_STATUS */ +#define INTF_UNUSED 0x0 +#define INTF_MEM_CAL_STATUS_SUCCESS 0x1 +#define INTF_MEM_CAL_STATUS_FAIL 0x2 +#define INTF_MEM_CAL_STATUS_ONGOING 0x4 + +/* cmd opcode BIST_MEM_INIT_START, BIST performed on full memory address range */ +#define BIST_FULL_MEM BIT(6) + +/* + * IOSSM mailbox required information + * + * @num_mem_interface: Number of memory interfaces instantiated + * @ip_type: IP type implemented on the IO96B + * @ip_instance_id: IP identifier for every IP instance implemented on the IO96B + */ +struct io96b_mb_ctrl { + u32 num_mem_interface; + u32 ip_type[2]; + u32 ip_id[2]; +}; + +/* CMD_REQ Register Definition */ +#define CMD_TARGET_IP_TYPE_MASK GENMASK(31, 29) +#define CMD_TARGET_IP_INSTANCE_ID_MASK GENMASK(28, 24) +#define CMD_TYPE_MASK GENMASK(23, 16) +#define CMD_OPCODE_MASK GENMASK(15, 0) + +/* + * IOSSM mailbox request + * @ip_type: IP type for the specified memory interface + * @ip_id: IP instance ID for the specified memory interface + * @usr_cmd_type: User desire IOSSM mailbox command type + * @usr_cmd_opcode: User desire IOSSM mailbox command opcode + * @cmd_param_*: Parameters (if applicable) for the requested IOSSM mailbox command + */ +struct io96b_mb_req { + u32 ip_type; + u32 ip_id; + u32 usr_cmd_type; + u32 usr_cmd_opcode; + u32 cmd_param[NUM_CMD_PARAM]; +}; + +/* + * IOSSM mailbox response outputs + * + * @cmd_resp_status: Command Interface status + * @cmd_resp_data_*: More spaces for command response + */ +struct io96b_mb_resp { + u32 cmd_resp_status; + u32 cmd_resp_data[NUM_CMD_RESPONSE_DATA]; +}; + +/* + * IO96B instance specific information + * + * @size: Memory size + * @io96b_csr_addr: IO96B instance CSR address + * @cal_status: IO96B instance calibration status + * @mb_ctrl: IOSSM mailbox required information + */ +struct io96b_instance { + u16 size; + phys_addr_t io96b_csr_addr; + bool cal_status; + struct io96b_mb_ctrl mb_ctrl; +}; + +/* + * Overall IO96B instance(s) information + * + * @num_instance: Number of instance(s) assigned to HPS + * @overall_cal_status: Overall calibration status for all IO96B instance(s) + * @ddr_type: DDR memory type + * @ecc_status: ECC enable status (false = disabled, true = enabled) + * @overall_size: Total DDR memory size + * @io96b[]: IO96B instance specific information + * @ckgen_lock: IO96B GEN PLL lock (false = not locked, true = locked) + * @num_port: Number of IO96B port. + * @io96b_pll: Selected IO96B PLL. Example bit 0: EMIF0 PLL A selected, + * bit 1: EMIF0 PLL B selected, bit 2 - EMIF1 PLL A selected, + * bit 3: EMIF1 PLL B selected + */ +struct io96b_info { + u8 num_instance; + bool overall_cal_status; + const char *ddr_type; + bool ecc_status; + u16 overall_size; + struct io96b_instance io96b[MAX_IO96B_SUPPORTED]; + bool ckgen_lock; + u8 num_port; + u8 io96b_pll; +}; + +int io96b_mb_req(phys_addr_t io96b_csr_addr, struct io96b_mb_req req, + u32 resp_data_len, struct io96b_mb_resp *resp); + +/* Supported IOSSM mailbox function */ +void io96b_mb_init(struct io96b_info *io96b_ctrl); +int io96b_cal_status(phys_addr_t addr); +void init_mem_cal(struct io96b_info *io96b_ctrl); +int get_mem_technology(struct io96b_info *io96b_ctrl); +int get_mem_width_info(struct io96b_info *io96b_ctrl); +int ecc_enable_status(struct io96b_info *io96b_ctrl); +int bist_mem_init_start(struct io96b_info *io96b_ctrl); +int ecc_interrupt_status(struct io96b_info *io96b_ctrl, bool *ecc_error_flag); diff --git a/drivers/ddr/altera/sdram_agilex5.c b/drivers/ddr/altera/sdram_agilex5.c new file mode 100644 index 00000000000..160b945b55f --- /dev/null +++ b/drivers/ddr/altera/sdram_agilex5.c @@ -0,0 +1,377 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Intel Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "iossm_mailbox.h" +#include "sdram_soc64.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* MPFE NOC registers */ +#define F2SDRAM_SIDEBAND_FLAGOUTSET0 0x50 +#define F2SDRAM_SIDEBAND_FLAGOUTSTATUS0 0x58 +#define SIDEBANDMGR_FLAGOUTSET0_REG SOCFPGA_F2SDRAM_MGR_ADDRESS +\ + F2SDRAM_SIDEBAND_FLAGOUTSET0 +#define SIDEBANDMGR_FLAGOUTSTATUS0_REG SOCFPGA_F2SDRAM_MGR_ADDRESS +\ + F2SDRAM_SIDEBAND_FLAGOUTSTATUS0 + +#define BOOT_SCRATCH_COLD3_REG (socfpga_get_sysmgr_addr() +\ + SYSMGR_SOC64_BOOT_SCRATCH_COLD3) + +#define PORT_EMIF_CONFIG_OFFSET 4 +#define EMIF_PLL_MASK GENMASK(19, 16) + +#define IO96B0_DUAL_PORT_MASK BIT(0) +#define IO96B0_DUAL_EMIF_MASK BIT(1) + +#define FIREWALL_MPFE_SCR_IO96B0_REG 0x18000d00 +#define FIREWALL_MPFE_SCR_IO96B1_REG 0x18000d04 +#define FIREWALL_MPFE_NOC_CSR_REG 0x18000d08 + +/* Reset type */ +enum reset_type { + POR_RESET, + WARM_RESET, + COLD_RESET, + NCONFIG, + JTAG_CONFIG, + RSU_RECONFIG +}; + +phys_addr_t io96b_csr_reg_addr[] = { + 0x18400000, /* IO96B_0 CSR registers address */ + 0x18800000 /* IO96B_1 CSR registers address */ +}; + +static enum reset_type get_reset_type(u32 reg) +{ + return FIELD_GET(ALT_SYSMGR_SCRATCH_REG_3_DDR_RESET_TYPE_MASK, reg); +} + +static void update_io96b_assigned_to_hps(bool dual_port_flag, bool dual_emif_flag) +{ + clrsetbits_le32(BOOT_SCRATCH_COLD3_REG, + ALT_SYSMGR_SCRATCH_REG_3_DDR_PORT_EMIF_INFO_MASK, + FIELD_PREP(ALT_SYSMGR_SCRATCH_REG_3_DDR_PORT_INFO_MASK, dual_port_flag) | + FIELD_PREP(ALT_SYSMGR_SCRATCH_REG_3_DDR_EMIF_INFO_MASK, dual_emif_flag)); + + debug("%s: update dual port dual emif info: 0x%x\n", __func__, + readl(BOOT_SCRATCH_COLD3_REG)); +} + +static void set_mpfe_config(void) +{ + /* Set mpfe_lite_intfcsel */ + setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_MPFE_CONFIG, BIT(2)); + + /* Set mpfe_lite_active */ + setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_MPFE_CONFIG, BIT(8)); + + debug("%s: mpfe_config: 0x%x\n", __func__, + readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_MPFE_CONFIG)); +} + +static bool is_ddr_init_hang(void) +{ + u32 reg = readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_POR0); + + debug("%s: 0x%x\n", __func__, reg); + + if (reg & ALT_SYSMGR_SCRATCH_REG_POR_0_DDR_PROGRESS_MASK) + return true; + + return false; +} + +static void ddr_init_inprogress(bool start) +{ + if (start) + setbits_le32(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_POR0, + ALT_SYSMGR_SCRATCH_REG_POR_0_DDR_PROGRESS_MASK); + else + clrbits_le32(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_POR0, + ALT_SYSMGR_SCRATCH_REG_POR_0_DDR_PROGRESS_MASK); +} + +static void populate_ddr_handoff(struct udevice *dev, struct io96b_info *io96b_ctrl) +{ + struct altera_sdram_plat *plat = dev_get_plat(dev); + int i; + u32 len = SOC64_HANDOFF_SDRAM_LEN; + u32 handoff_table[len]; + + /* Read handoff for DDR configuration */ + socfpga_handoff_read((void *)SOC64_HANDOFF_SDRAM, handoff_table, len); + + /* Read handoff - dual port */ + plat->dualport = FIELD_GET(IO96B0_DUAL_PORT_MASK, handoff_table[PORT_EMIF_CONFIG_OFFSET]); + debug("%s: dualport from handoff: 0x%x\n", __func__, plat->dualport); + + if (plat->dualport) + io96b_ctrl->num_port = 2; + else + io96b_ctrl->num_port = 1; + + /* Read handoff - dual EMIF */ + plat->dualemif = FIELD_GET(IO96B0_DUAL_EMIF_MASK, handoff_table[PORT_EMIF_CONFIG_OFFSET]); + debug("%s: dualemif from handoff: 0x%x\n", __func__, plat->dualemif); + + if (plat->dualemif) + io96b_ctrl->num_instance = 2; + else + io96b_ctrl->num_instance = 1; + + io96b_ctrl->io96b_pll = FIELD_GET(EMIF_PLL_MASK, + handoff_table[PORT_EMIF_CONFIG_OFFSET]); + debug("%s: io96b enabled pll from handoff: 0x%x\n", __func__, io96b_ctrl->io96b_pll); + + update_io96b_assigned_to_hps(plat->dualport, plat->dualemif); + + /* Assign IO96B CSR base address if it is valid */ + for (i = 0; i < io96b_ctrl->num_instance; i++) { + io96b_ctrl->io96b[i].io96b_csr_addr = io96b_csr_reg_addr[i]; + debug("%s: IO96B 0x%llx CSR enabled\n", __func__, + io96b_ctrl->io96b[i].io96b_csr_addr); + } +} + +static void config_mpfe_sideband_mgr(struct udevice *dev) +{ + struct altera_sdram_plat *plat = dev_get_plat(dev); + + /* Dual port setting */ + if (plat->dualport) + setbits_le32(SIDEBANDMGR_FLAGOUTSET0_REG, BIT(4)); + + /* Dual EMIF setting */ + if (plat->dualemif) { + set_mpfe_config(); + setbits_le32(SIDEBANDMGR_FLAGOUTSET0_REG, BIT(5)); + } + + debug("%s: SIDEBANDMGR_FLAGOUTSTATUS0: 0x%x\n", __func__, + readl(SIDEBANDMGR_FLAGOUTSTATUS0_REG)); +} + +static void config_ccu_mgr(struct udevice *dev) +{ + int ret = 0; + struct altera_sdram_plat *plat = dev_get_plat(dev); + + if (plat->dualport || plat->dualemif) { + debug("%s: config interleaving on ccu reg\n", __func__); + ret = uclass_get_device_by_name(UCLASS_NOP, + "socfpga-ccu-ddr-interleaving-on", &dev); + } else { + debug("%s: config interleaving off ccu reg\n", __func__); + ret = uclass_get_device_by_name(UCLASS_NOP, + "socfpga-ccu-ddr-interleaving-off", &dev); + } + + if (ret) { + printf("interleaving on/off ccu settings init failed: %d\n", ret); + hang(); + } +} + +static void config_firewall_mpfe_csr(struct udevice *dev) +{ + int ret = 0; + + debug("%s: config Firewall setting for MPFE CSR\n", __func__); + ret = uclass_get_device_by_name(UCLASS_NOP, + "socfpga-noc-fw-mpfe-csr", &dev); + + if (ret) { + printf("Firewall setting for MPFE CSR init failed: %d\n", ret); + hang(); + } +} + +static bool hps_ocram_dbe_status(void) +{ + u32 reg = readl(BOOT_SCRATCH_COLD3_REG); + + if (reg & ALT_SYSMGR_SCRATCH_REG_3_OCRAM_DBE_MASK) + return true; + + return false; +} + +int sdram_mmr_init_full(struct udevice *dev) +{ + int ret = 0; + phys_size_t hw_size; + struct bd_info bd = {0}; + struct altera_sdram_plat *plat = dev_get_plat(dev); + struct altera_sdram_priv *priv = dev_get_priv(dev); + struct io96b_info *io96b_ctrl = malloc(sizeof(*io96b_ctrl)); + + u32 reg = readl(BOOT_SCRATCH_COLD3_REG); + enum reset_type reset_t = get_reset_type(reg); + bool full_mem_init = false; + + /* DDR initialization progress status tracking */ + bool is_ddr_hang_be4_rst = is_ddr_init_hang(); + + debug("DDR: SDRAM init in progress ...\n"); + ddr_init_inprogress(true); + + debug("DDR: Address MPFE 0x%llx\n", plat->mpfe_base_addr); + + /* Populating DDR handoff data */ + debug("DDR: Checking SDRAM configuration in progress ...\n"); + populate_ddr_handoff(dev, io96b_ctrl); + + /* Configuring MPFE sideband manager registers - dual port & dual emif*/ + config_mpfe_sideband_mgr(dev); + + /* Configuring Interleave/Non-interleave ccu registers */ + config_ccu_mgr(dev); + + /* Configure if polling is needed for IO96B GEN PLL locked */ + io96b_ctrl->ckgen_lock = true; + + /* Ensure calibration status passing */ + init_mem_cal(io96b_ctrl); + + printf("DDR: Calibration success\n"); + + /* Initiate IOSSM mailbox */ + io96b_mb_init(io96b_ctrl); + + /* DDR type, DDR size and ECC status) */ + ret = get_mem_technology(io96b_ctrl); + if (ret) { + printf("DDR: Failed to get DDR type\n"); + + goto err; + } + + ret = get_mem_width_info(io96b_ctrl); + if (ret) { + printf("DDR: Failed to get DDR size\n"); + + goto err; + } + + hw_size = (phys_size_t)io96b_ctrl->overall_size * SZ_1G / SZ_8; + + /* Get bank configuration from devicetree */ + ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL, + (phys_size_t *)&gd->ram_size, &bd); + if (ret) { + puts("DDR: Failed to decode memory node\n"); + ret = -ENXIO; + + goto err; + } + + if (gd->ram_size != hw_size) { + printf("DDR: Warning: DRAM size from device tree (%lld MiB)\n", + gd->ram_size >> 20); + printf(" mismatch with hardware (%lld MiB).\n", + hw_size >> 20); + } + + if (gd->ram_size > hw_size) { + printf("DDR: Error: DRAM size from device tree is greater\n"); + printf(" than hardware size.\n"); + hang(); + } + + printf("%s: %lld MiB\n", io96b_ctrl->ddr_type, gd->ram_size >> 20); + + ret = ecc_enable_status(io96b_ctrl); + if (ret) { + printf("DDR: Failed to get ECC enabled status\n"); + + goto err; + } + + /* Is HPS cold or warm reset? If yes, Skip full memory initialization if ECC + * enabled to preserve memory content + */ + if (io96b_ctrl->ecc_status) { + bool ecc_error_flag; + + ret = ecc_interrupt_status(io96b_ctrl, &ecc_error_flag); + if (ret) { + printf("DDR: Failed to get ECC interrupt status\n"); + + goto err; + } + + if (ecc_error_flag) { + if (CONFIG_IS_ENABLED(WDT)) { + struct udevice *wdt; + + printf("DDR: ECC error recover start now\n"); + ret = uclass_first_device_err(UCLASS_WDT, &wdt); + if (ret) { + printf("DDR: Failed to trigger watchdog reset\n"); + hang(); + } + + wdt_expire_now(wdt, 0); + } + hang(); + } + + full_mem_init = hps_ocram_dbe_status() | is_ddr_hang_be4_rst; + if (full_mem_init || !(reset_t == WARM_RESET || reset_t == COLD_RESET)) { + ret = bist_mem_init_start(io96b_ctrl); + if (ret) { + printf("DDR: Failed to fully initialize DDR memory\n"); + + goto err; + } + } + + printf("SDRAM-ECC: Initialized success\n"); + } + + sdram_size_check(&bd); + printf("DDR: size check success\n"); + + sdram_set_firewall(&bd); + + /* Firewall setting for MPFE CSR */ + config_firewall_mpfe_csr(dev); + + printf("DDR: firewall init success\n"); + + priv->info.base = bd.bi_dram[0].start; + priv->info.size = gd->ram_size; + + /* Ending DDR driver initialization success tracking */ + ddr_init_inprogress(false); + + printf("DDR: init success\n"); + +err: + free(io96b_ctrl); + + return ret; +} diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c index 9e57c2ecfa4..ce286cc2e76 100644 --- a/drivers/ddr/altera/sdram_soc64.c +++ b/drivers/ddr/altera/sdram_soc64.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2016-2022 Intel Corporation - * + * Copyright (C) 2016-2024 Intel Corporation */ #include @@ -27,6 +26,7 @@ #define PGTABLE_OFF 0x4000 +#if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) u32 hmc_readl(struct altera_sdram_plat *plat, u32 reg) { return readl(plat->iomhc + reg); @@ -98,8 +98,9 @@ int emif_reset(struct altera_sdram_plat *plat) debug("DDR: %s triggered successly\n", __func__); return 0; } +#endif -#if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) +#if !(IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) || IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)) int poll_hmc_clock_status(void) { return wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() + @@ -251,7 +252,7 @@ phys_size_t sdram_calculate_size(struct altera_sdram_plat *plat) return size; } -void sdram_set_firewall(struct bd_info *bd) +static void sdram_set_firewall_non_f2sdram(struct bd_info *bd) { u32 i; phys_size_t value; @@ -287,7 +288,7 @@ void sdram_set_firewall(struct bd_info *bd) FW_MPU_DDR_SCR_NONMPUREGION0ADDR_BASEEXT + (i * 4 * sizeof(u32))); - /* Setting non-secure MPU limit and limit extexded */ + /* Setting non-secure MPU limit and limit extended */ value = bd->bi_dram[i].start + bd->bi_dram[i].size - 1; lower = lower_32_bits(value); @@ -300,7 +301,7 @@ void sdram_set_firewall(struct bd_info *bd) FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT + (i * 4 * sizeof(u32))); - /* Setting non-secure Non-MPU limit and limit extexded */ + /* Setting non-secure Non-MPU limit and limit extended */ FW_MPU_DDR_SCR_WRITEL(lower, FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT + (i * 4 * sizeof(u32))); @@ -313,6 +314,61 @@ void sdram_set_firewall(struct bd_info *bd) } } +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +static void sdram_set_firewall_f2sdram(struct bd_info *bd) +{ + u32 i, lower, upper; + phys_size_t value; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + if (!bd->bi_dram[i].size) + continue; + + value = bd->bi_dram[i].start; + + /* Keep first 1MB of SDRAM memory region as secure region when + * using ATF flow, where the ATF code is located. + */ + if (IS_ENABLED(CONFIG_SPL_ATF) && i == 0) + value += SZ_1M; + + /* Setting base and base extended */ + lower = lower_32_bits(value); + upper = upper_32_bits(value); + FW_F2SDRAM_DDR_SCR_WRITEL(lower, + FW_F2SDRAM_DDR_SCR_REGION0ADDR_BASE + + (i * 4 * sizeof(u32))); + FW_F2SDRAM_DDR_SCR_WRITEL(upper & 0xff, + FW_F2SDRAM_DDR_SCR_REGION0ADDR_BASEEXT + + (i * 4 * sizeof(u32))); + + /* Setting limit and limit extended */ + value = bd->bi_dram[i].start + bd->bi_dram[i].size - 1; + + lower = lower_32_bits(value); + upper = upper_32_bits(value); + + FW_F2SDRAM_DDR_SCR_WRITEL(lower, + FW_F2SDRAM_DDR_SCR_REGION0ADDR_LIMIT + + (i * 4 * sizeof(u32))); + FW_F2SDRAM_DDR_SCR_WRITEL(upper & 0xff, + FW_F2SDRAM_DDR_SCR_REGION0ADDR_LIMITEXT + + (i * 4 * sizeof(u32))); + + FW_F2SDRAM_DDR_SCR_WRITEL(BIT(i), FW_F2SDRAM_DDR_SCR_EN_SET); + } +} +#endif + +void sdram_set_firewall(struct bd_info *bd) +{ + sdram_set_firewall_non_f2sdram(bd); + +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + sdram_set_firewall_f2sdram(bd); +#endif +} + static int altera_sdram_of_to_plat(struct udevice *dev) { struct altera_sdram_plat *plat = dev_get_plat(dev); @@ -321,7 +377,12 @@ static int altera_sdram_of_to_plat(struct udevice *dev) /* These regs info are part of DDR handoff in bitstream */ #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) return 0; -#endif +#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + addr = dev_read_addr_index(dev, 0); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + plat->mpfe_base_addr = addr; +#else addr = dev_read_addr_index(dev, 0); if (addr == FDT_ADDR_T_NONE) @@ -337,7 +398,7 @@ static int altera_sdram_of_to_plat(struct udevice *dev) if (addr == FDT_ADDR_T_NONE) return -EINVAL; plat->hmc = (void __iomem *)addr; - +#endif return 0; } @@ -384,6 +445,7 @@ static const struct udevice_id altera_sdram_ids[] = { { .compatible = "altr,sdr-ctl-s10" }, { .compatible = "intel,sdr-ctl-agilex" }, { .compatible = "intel,sdr-ctl-n5x" }, + { .compatible = "intel,sdr-ctl-agilex5" }, { /* sentinel */ } }; diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h index 87a70a861ba..f75a1e47cc3 100644 --- a/drivers/ddr/altera/sdram_soc64.h +++ b/drivers/ddr/altera/sdram_soc64.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2017-2019 Intel Corporation + * Copyright (C) 2017-2024 Intel Corporation */ #ifndef _SDRAM_SOC64_H_ @@ -13,11 +13,19 @@ struct altera_sdram_priv { struct reset_ctl_bulk resets; }; +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +struct altera_sdram_plat { + fdt_addr_t mpfe_base_addr; + bool dualport; + bool dualemif; +}; +#else struct altera_sdram_plat { void __iomem *hmc; void __iomem *ddr_sch; void __iomem *iomhc; }; +#endif /* ECC HMC registers */ #define DDRIOCTRL 0x8 @@ -65,6 +73,8 @@ struct altera_sdram_plat { #define CTRLCFG0 0x28 #define CTRLCFG1 0x2c #define CTRLCFG3 0x34 +#define CTRLCFG5 0x3c +#define CTRLCFG6 0x40 #define DRAMTIMING0 0x50 #define CALTIMING0 0x7c #define CALTIMING1 0x80 @@ -79,7 +89,7 @@ struct altera_sdram_plat { #define NIOSRESERVED2 0x118 #define DRAMADDRW_CFG_COL_ADDR_WIDTH(x) \ - (((x) >> 0) & 0x1F) + ((x) & 0x1F) #define DRAMADDRW_CFG_ROW_ADDR_WIDTH(x) \ (((x) >> 5) & 0x1F) #define DRAMADDRW_CFG_BANK_ADDR_WIDTH(x) \ @@ -90,7 +100,7 @@ struct altera_sdram_plat { (((x) >> 16) & 0x7) #define CTRLCFG0_CFG_MEMTYPE(x) \ - (((x) >> 0) & 0xF) + ((x) & 0xF) #define CTRLCFG0_CFG_DIMM_TYPE(x) \ (((x) >> 4) & 0x7) #define CTRLCFG0_CFG_AC_POS(x) \ @@ -99,17 +109,17 @@ struct altera_sdram_plat { (((x) >> 9) & 0x1F) #define CTRLCFG1_CFG_DBC3_BURST_LEN(x) \ - (((x) >> 0) & 0x1F) + ((x) & 0x1F) #define CTRLCFG1_CFG_ADDR_ORDER(x) \ (((x) >> 5) & 0x3) #define CTRLCFG1_CFG_CTRL_EN_ECC(x) \ (((x) >> 7) & 0x1) #define DRAMTIMING0_CFG_TCL(x) \ - (((x) >> 0) & 0x7F) + ((x) & 0x7F) #define CALTIMING0_CFG_ACT_TO_RDWR(x) \ - (((x) >> 0) & 0x3F) + ((x) & 0x3F) #define CALTIMING0_CFG_ACT_TO_PCH(x) \ (((x) >> 6) & 0x3F) #define CALTIMING0_CFG_ACT_TO_ACT(x) \ @@ -118,7 +128,7 @@ struct altera_sdram_plat { (((x) >> 18) & 0x3F) #define CALTIMING1_CFG_RD_TO_RD(x) \ - (((x) >> 0) & 0x3F) + ((x) & 0x3F) #define CALTIMING1_CFG_RD_TO_RD_DC(x) \ (((x) >> 6) & 0x3F) #define CALTIMING1_CFG_RD_TO_RD_DB(x) \ @@ -129,7 +139,7 @@ struct altera_sdram_plat { (((x) >> 24) & 0x3F) #define CALTIMING2_CFG_RD_TO_WR_DB(x) \ - (((x) >> 0) & 0x3F) + ((x) & 0x3F) #define CALTIMING2_CFG_RD_TO_WR_PCH(x) \ (((x) >> 6) & 0x3F) #define CALTIMING2_CFG_RD_AP_TO_VALID(x) \ @@ -140,7 +150,7 @@ struct altera_sdram_plat { (((x) >> 24) & 0x3F) #define CALTIMING3_CFG_WR_TO_WR_DB(x) \ - (((x) >> 0) & 0x3F) + ((x) & 0x3F) #define CALTIMING3_CFG_WR_TO_RD(x) \ (((x) >> 6) & 0x3F) #define CALTIMING3_CFG_WR_TO_RD_DC(x) \ @@ -151,7 +161,7 @@ struct altera_sdram_plat { (((x) >> 24) & 0x3F) #define CALTIMING4_CFG_WR_AP_TO_VALID(x) \ - (((x) >> 0) & 0x3F) + ((x) & 0x3F) #define CALTIMING4_CFG_PCH_TO_VALID(x) \ (((x) >> 6) & 0x3F) #define CALTIMING4_CFG_PCH_ALL_TO_VALID(x) \ @@ -162,7 +172,7 @@ struct altera_sdram_plat { (((x) >> 26) & 0x3F) #define CALTIMING9_CFG_4_ACT_TO_ACT(x) \ - (((x) >> 0) & 0xFF) + ((x) & 0xFF) /* Firewall DDR scheduler MPFE */ #define FW_HMC_ADAPTOR_REG_ADDR 0xf8020004 From patchwork Fri Sep 20 07:02:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1987691 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=hBy3ZGUS; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X93NV1JhPz1y1t for ; Fri, 20 Sep 2024 17:07:06 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id C2DA4893AA; Fri, 20 Sep 2024 09:03:54 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="hBy3ZGUS"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 917BB893BC; Fri, 20 Sep 2024 09:03:54 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 8A5CE893AF for ; Fri, 20 Sep 2024 09:03:50 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=tien.fong.chee@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1726815831; x=1758351831; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gbTNxq/e/3C95nv+t97Jz6oOwVstC6Z957uFjYiFKgU=; b=hBy3ZGUSSjsGZVgTi/nnzFk9Rr1/XssNKQokZtEtneJvRNETpdDxh17j uEmoMw41sa1lr/GR3QCo2ndvxjVJdYxTG+aRPk+NljToZ8YXRzbzIN1aa rcCBAa4Q1B1+LW1nMJ3vuw8oZpQ20Sz33neT3+orlY/TQclvaIVdkLsM+ XtyqmIVO/U/prfUA2BNGfHFTjbl/ICONU8zhpW7RjXVx01hI8FedhfxWy cc/b8g20p6iLofNy6w/XwoNIV4QrZUp9L7Lp1YFruJbjdkhwQAth17bGh hkMJY1M5kjhudzhMY89jmLDFG2oUeFQTAXgI/oLsV/kodgRODi0LAbKfE A==; X-CSE-ConnectionGUID: sATIuIoPQTKX5T6rtBncYw== X-CSE-MsgGUID: BDbbeQ6CTZmgdFmW60YJIQ== X-IronPort-AV: E=McAfee;i="6700,10204,11200"; a="25961112" X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="25961112" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2024 00:03:50 -0700 X-CSE-ConnectionGUID: u2bwT2R/QiOb33a5FhB74g== X-CSE-MsgGUID: PsOiZFnDQwWMwOwpNysG1w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="70235272" Received: from pglc00502.png.intel.com ([10.221.239.194]) by orviesa009.jf.intel.com with ESMTP; 20 Sep 2024 00:03:48 -0700 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Cc: Marek Vasut , Simon Goldschmidt , Meng Tingting , Yuslaimi Alif Zakuan , Hea Kok Kiang , Tien Fong Chee Subject: [PATCH v1 17/20] arm: socfpga: agilex5: Add SPL for Agilex5 SoCFPGA Date: Fri, 20 Sep 2024 15:02:39 +0800 Message-Id: <20240920070242.20884-18-tien.fong.chee@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240920070242.20884-1-tien.fong.chee@intel.com> References: <20240920070242.20884-1-tien.fong.chee@intel.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Tien Fong Chee Add SPL support for Agilex5 SoCFPGA. Signed-off-by: Tien Fong Chee --- arch/arm/mach-socfpga/Makefile | 3 ++ arch/arm/mach-socfpga/spl_agilex5.c | 84 +++++++++++++++++++++++++++++ 2 files changed, 87 insertions(+) create mode 100644 arch/arm/mach-socfpga/spl_agilex5.c diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 32b3e7a57e2..3fbe3d4fa63 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -66,6 +66,8 @@ obj-y += reset_manager_s10.o obj-y += wrap_handoff_soc64.o obj-y += wrap_pll_config_soc64.o obj-y += ccu_ncore3.o +obj-y += system_manager_soc64.o +obj-y += timer_s10.o endif ifdef CONFIG_TARGET_SOCFPGA_N5X @@ -109,6 +111,7 @@ obj-y += spl_n5x.o endif ifdef CONFIG_TARGET_SOCFPGA_AGILEX5 obj-y += spl_soc64.o +obj-y += spl_agilex5.o endif else obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o diff --git a/arch/arm/mach-socfpga/spl_agilex5.c b/arch/arm/mach-socfpga/spl_agilex5.c new file mode 100644 index 00000000000..2852112f788 --- /dev/null +++ b/arch/arm/mach-socfpga/spl_agilex5.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Intel Corporation + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void board_init_f(ulong dummy) +{ + int ret; + struct udevice *dev; + + ret = spl_early_init(); + if (ret) + hang(); + + socfpga_get_managers_addr(); + + sysmgr_pinmux_init(); + + /* Ensure watchdog is paused when debugging is happening */ + writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, + socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG); + + timer_init(); + + ret = uclass_get_device(UCLASS_CLK, 0, &dev); + if (ret) { + debug("Clock init failed: %d\n", ret); + hang(); + } + + /* + * Enable watchdog as early as possible before initializing other + * component. Watchdog need to be enabled after clock driver because + * it will retrieve the clock frequency from clock driver. + */ + if (CONFIG_IS_ENABLED(WDT)) + initr_watchdog(); + + preloader_console_init(); + print_reset_info(); + cm_print_clock_quick_summary(); + + ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-ccu-config", &dev); + if (ret) { + printf("HPS CCU settings init failed: %d\n", ret); + hang(); + } + + ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-firewall-config", &dev); + if (ret) { + printf("HPS firewall settings init failed: %d\n", ret); + hang(); + } + + if (IS_ENABLED(CONFIG_SPL_ALTERA_SDRAM)) { + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + hang(); + } + } + + mbox_init(); + + if (IS_ENABLED(CONFIG_CADENCE_QSPI)) + mbox_qspi_open(); +} From patchwork Fri Sep 20 07:02:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1987692 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=DjUzGUM6; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X93Nm6tq7z1y1t for ; Fri, 20 Sep 2024 17:07:20 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 30E0A893A0; Fri, 20 Sep 2024 09:03:57 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="DjUzGUM6"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 637E989391; Fri, 20 Sep 2024 09:03:56 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 0434889393 for ; Fri, 20 Sep 2024 09:03:52 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=tien.fong.chee@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1726815834; x=1758351834; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hpaUwe6SCcCtUFjcAZi9CJ8edUOZ8tJJ0EagCALe1NE=; b=DjUzGUM6ejRBQopbGXHUHR/8nZrVBiZGOa+2zEe3FEdvccu3odTXhtF1 7hk6WeOw8dMBWAJ5JJ5j+omRrNu/mroiD4Qo//z1+vYfRqLHmcuxHRrg6 KnGcPz4MkMScKUl0ZvvpDzGd0vJn3n/7O62fWgiuINoLHkPX0cDJg/Qm2 qL7+pWcyxLGTFmAfaTBV7O4eSvsmWZdn70SBGSru2O91KVZf8vgzPIy3c giLq0Wf+rhqkqtabNPw1tY3ZliGFDmIkFxnMLAYw33Ps2R9F+HS07Omro JsQJMY307irsrS7BI7T0o4gxTE54JVtNpgqLHApVQ0KRdqobv6VYO2NIZ A==; X-CSE-ConnectionGUID: 4n9MnywDR0Gppo+URCL1UA== X-CSE-MsgGUID: Lz3SFhYnTPasKrCiZZHeSg== X-IronPort-AV: E=McAfee;i="6700,10204,11200"; a="25961118" X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="25961118" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2024 00:03:53 -0700 X-CSE-ConnectionGUID: qz2PO5nhROq0MsaYVFvlZg== X-CSE-MsgGUID: BeLxl+/ZRiSp1uv2a6czkg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="70235282" Received: from pglc00502.png.intel.com ([10.221.239.194]) by orviesa009.jf.intel.com with ESMTP; 20 Sep 2024 00:03:50 -0700 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Cc: Marek Vasut , Simon Goldschmidt , Meng Tingting , Yuslaimi Alif Zakuan , Hea Kok Kiang , Tien Fong Chee Subject: [PATCH v1 18/20] configs: socfpga: soc64: agilex5: Enable XGMAC Date: Fri, 20 Sep 2024 15:02:40 +0800 Message-Id: <20240920070242.20884-19-tien.fong.chee@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240920070242.20884-1-tien.fong.chee@intel.com> References: <20240920070242.20884-1-tien.fong.chee@intel.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Tien Fong Chee Enable XGMAC for SoCFPGA Agilex5 devkit. Signed-off-by: Tien Fong Chee --- configs/socfpga_agilex5_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig index 81bbe967dcf..a4a5064d9c2 100644 --- a/configs/socfpga_agilex5_defconfig +++ b/configs/socfpga_agilex5_defconfig @@ -92,3 +92,4 @@ CONFIG_WDT=y CONFIG_PANIC_HANG=y CONFIG_SPL_CRC32=y # CONFIG_EFI_LOADER is not set +CONFIG_DWC_ETH_XGMAC=y From patchwork Fri Sep 20 07:02:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1987693 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=AgVTg5W0; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X93P30XZGz1y1t for ; Fri, 20 Sep 2024 17:07:35 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 8E412893C0; Fri, 20 Sep 2024 09:03:59 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="AgVTg5W0"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 5DA78893BF; Fri, 20 Sep 2024 09:03:58 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id EEDDF893BD for ; Fri, 20 Sep 2024 09:03:54 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=tien.fong.chee@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1726815835; x=1758351835; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2wReknbTQ353XTrv1k2f19xn6aGsE+oRhXxCEb/DpiI=; b=AgVTg5W04CFGAEPnBubA6vv6j9pB4Ch59TIpd642Le/LcBlqvttZ7p0L K7tOyz/ROcIe5QkeI4nS5hsmSN4S7yG2KFfgJl1ACMqLIXUjlSuItQgr4 ZBWKHyIsAR5wRKpumfhqaIdsZRQ8p9635u2FRR0J+mA3vSFbQNHdeEyuG SSlvHowwOtVR9l5oTpuVXgvSy9JvDuI1KFFzLoDzOzTvMT4xDb5Oy41d1 ES+gFR1PxJ5KvqkcOOktrdROWGFhrrlDL8dOORkBo4Vfyuuk5klEq/vXb ob2/C68xSc4e5Mnw1KdEx4Z9N/bDNNH3qM/P0H+qlZZt4gr8a5B6wHpLb A==; X-CSE-ConnectionGUID: b8ad9jwlRAaMDVfQvhp67A== X-CSE-MsgGUID: iRdY6oxmQ+23T7fY2zpd5Q== X-IronPort-AV: E=McAfee;i="6700,10204,11200"; a="25961121" X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="25961121" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2024 00:03:55 -0700 X-CSE-ConnectionGUID: 54wx0oVpTgq8Bo1fXW/z5A== X-CSE-MsgGUID: PqO9i69eS0KF53wON7fqTQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="70235295" Received: from pglc00502.png.intel.com ([10.221.239.194]) by orviesa009.jf.intel.com with ESMTP; 20 Sep 2024 00:03:53 -0700 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Cc: Marek Vasut , Simon Goldschmidt , Meng Tingting , Yuslaimi Alif Zakuan , Hea Kok Kiang , Tien Fong Chee Subject: [PATCH v1 19/20] arm: socfpga: soc64: Add support for board_boot_order() Date: Fri, 20 Sep 2024 15:02:41 +0800 Message-Id: <20240920070242.20884-20-tien.fong.chee@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240920070242.20884-1-tien.fong.chee@intel.com> References: <20240920070242.20884-1-tien.fong.chee@intel.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Tien Fong Chee Add board_boot_order() to retrieve the list of boot devices from spl-boot-order property in device tree. This board_boot_order() would be used for all Intel SOC64 devices. Signed-off-by: Tien Fong Chee --- arch/arm/mach-socfpga/spl_soc64.c | 103 ++++++++++++++++++++++++++++++ 1 file changed, 103 insertions(+) diff --git a/arch/arm/mach-socfpga/spl_soc64.c b/arch/arm/mach-socfpga/spl_soc64.c index 3bfe4bb9dd3..9bfa15e9ded 100644 --- a/arch/arm/mach-socfpga/spl_soc64.c +++ b/arch/arm/mach-socfpga/spl_soc64.c @@ -15,6 +15,109 @@ u32 spl_boot_device(void) return BOOT_DEVICE_MMC1; } +/* This function is to map specified node onto SPL boot devices */ +static int spl_node_to_boot_device(int node) +{ + const void *blob = gd->fdt_blob; + struct udevice *parent; + const char *prop; + + if (!uclass_get_device_by_of_offset(UCLASS_MMC, node, &parent)) + return BOOT_DEVICE_MMC1; + else if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, &parent)) + return BOOT_DEVICE_SPI; + else if (!uclass_get_device_by_of_offset(UCLASS_MTD, node, &parent)) + return BOOT_DEVICE_NAND; + + prop = fdt_getprop(blob, node, "device_type", NULL); + if (prop) { + if (!strcmp(prop, "memory")) + return BOOT_DEVICE_RAM; + + printf("%s: unknown device_type %s\n", __func__, prop); + } + + return -ENODEV; +} + +static void default_spl_boot_list(u32 *spl_boot_list, int length) +{ + spl_boot_list[0] = spl_boot_device(); + + if (length > 1) + spl_boot_list[1] = BOOT_DEVICE_SPI; + + if (length > 2) + spl_boot_list[2] = BOOT_DEVICE_NAND; +} + +void board_boot_order(u32 *spl_boot_list) +{ + int idx = 0; + const void *blob = gd->fdt_blob; + int chosen_node = fdt_path_offset(blob, "/chosen"); + const char *conf; + int elem; + int boot_device; + int node; + int length; + + /* expect valid initialized spl_boot_list */ + if (!spl_boot_list) + return; + + length = 1; + while (spl_boot_list[length] == spl_boot_list[length - 1]) + length++; + + debug("%s: chosen_node is %d\n", __func__, chosen_node); + if (chosen_node < 0) { + printf("%s: /chosen not found, using default\n", __func__); + default_spl_boot_list(spl_boot_list, length); + return; + } + + for (elem = 0; + (conf = fdt_stringlist_get(blob, chosen_node, + "u-boot,spl-boot-order", elem, NULL)); + elem++) { + if (idx >= length) { + printf("%s: limit %d to spl_boot_list exceeded\n", __func__, + length); + break; + } + + /* Resolve conf item as a path in device tree */ + node = fdt_path_offset(blob, conf); + if (node < 0) { + debug("%s: could not find %s in FDT\n", __func__, conf); + continue; + } + + /* Try to map spl node back onto SPL boot devices */ + boot_device = spl_node_to_boot_device(node); + if (boot_device < 0) { + debug("%s: could not map node @%x to a boot-device\n", + __func__, node); + continue; + } + + spl_boot_list[idx] = boot_device; + debug("%s: spl_boot_list[%d] = %u\n", __func__, idx, + spl_boot_list[idx]); + idx++; + } + + if (idx == 0) { + if (!conf && !elem) { + printf("%s: spl-boot-order invalid, using default\n", __func__); + default_spl_boot_list(spl_boot_list, length); + } else { + printf("%s: no valid element spl-boot-order list\n", __func__); + } + } +} + #if IS_ENABLED(CONFIG_SPL_MMC) u32 spl_boot_mode(const u32 boot_device) { From patchwork Fri Sep 20 07:02:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1987694 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=aNOiW/rQ; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X93PK1LPxz1y1t for ; Fri, 20 Sep 2024 17:07:49 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id E825989391; Fri, 20 Sep 2024 09:04:01 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="aNOiW/rQ"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 5AE7789391; Fri, 20 Sep 2024 09:04:01 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 24C0489399 for ; Fri, 20 Sep 2024 09:03:56 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=tien.fong.chee@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1726815838; x=1758351838; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7XwlD1u6WsjUbiHCVN79JTX/k60Es+X5zsKy8NPLsog=; b=aNOiW/rQM1LN2UiOInkQbH3uP4fIT2KpOhs9IJTYSbSWalMBoGH11Ky+ tW2APCjOcMKC8S4WCHozeRVUkEW+vYqNwTDDaDOl04pU66Yr7WM7Iz90j TfvDzq8ubqrmZlRNxRAsBiZvbobrE7VKAD6vGw8k+nNbTfaQSCyGAX6ep ijsJDKSi4Fd+8JA784qqHRJmBdF72HXDDGtHHvrVxTRMTWnNJi3/27PDM 3G/PSdJ1poY3KsN8bHM6UAELMQG9xUTYHHXfgirCBdlbWxoXswqYBJylq jnN3+oTUVsjfI1iD1rFGPwyZL2vMLebVZKYYsLyVdeVpzB4OLnhmljaxu g==; X-CSE-ConnectionGUID: 7Wen6Ot4SDu2iflHW7WDXg== X-CSE-MsgGUID: Awk7TjozSvS1AzqlP/kI3w== X-IronPort-AV: E=McAfee;i="6700,10204,11200"; a="25961125" X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="25961125" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2024 00:03:57 -0700 X-CSE-ConnectionGUID: SIxrIrIISCWneLXGWpGdoQ== X-CSE-MsgGUID: P1wqM0D/R1qaz2niOrMbfQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="70235305" Received: from pglc00502.png.intel.com ([10.221.239.194]) by orviesa009.jf.intel.com with ESMTP; 20 Sep 2024 00:03:55 -0700 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Cc: Marek Vasut , Simon Goldschmidt , Meng Tingting , Yuslaimi Alif Zakuan , Hea Kok Kiang , Tien Fong Chee Subject: [PATCH v1 20/20] configs: socfpga: soc64: agilex5: Enable QSPI boot with UBI / UBIFS Date: Fri, 20 Sep 2024 15:02:42 +0800 Message-Id: <20240920070242.20884-21-tien.fong.chee@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240920070242.20884-1-tien.fong.chee@intel.com> References: <20240920070242.20884-1-tien.fong.chee@intel.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Alif Zakuan Yuslaimi Add the required configuration in the U-Boot env to enable Linux QSPI boot with UBI / UBIFS. Signed-off-by: Alif Zakuan Yuslaimi Signed-off-by: Tien Fong Chee --- configs/socfpga_agilex5_defconfig | 1 + include/configs/socfpga_soc64_common.h | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig index a4a5064d9c2..4ac118f1fec 100644 --- a/configs/socfpga_agilex5_defconfig +++ b/configs/socfpga_agilex5_defconfig @@ -37,6 +37,7 @@ CONFIG_SPL_SYS_MALLOC_SIZE=0x500000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_CACHE=y CONFIG_SPL_SPI_FLASH_MTD=y +CONFIG_SPL_MTD=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x04000000 CONFIG_SPL_ATF=y diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index b7ee1dbf201..7a44f042165 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -56,6 +56,11 @@ #define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \ "bootcmd_qspi=ubi detach; sf probe && " \ + "setenv mtdids 'nor0=nor0,nand0=nand.0' && " \ + "setenv mtdparts 'mtdparts=nor0:66m(u-boot),190m(root); " \ + "nand.0:2m(nand_uboot),500m(nand_root)' && " \ + "env select UBI; saveenv && " \ + "ubi part root && " \ "if ubi part root && ubi readvol ${scriptaddr} script; " \ "then echo QSPI: Running script from UBIFS; " \ "elif sf read ${scriptaddr} ${qspiscriptaddr} ${scriptsize}; " \