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Wed, 18 Sep 2024 15:29:01 +0000 From: To: CC: , , Saurabh Jha Subject: [PATCH v10 1/2] aarch64: Add AdvSIMD faminmax intrinsics Date: Wed, 18 Sep 2024 16:28:17 +0100 Message-ID: <20240918152818.2345370-2-saurabh.jha@arm.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240918152818.2345370-1-saurabh.jha@arm.com> References: <20240918152818.2345370-1-saurabh.jha@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: DB5PEPF00014B89:EE_|PAWPR08MB9758:EE_|DB1PEPF000509E5:EE_|DBBPR08MB10481:EE_ X-MS-Office365-Filtering-Correlation-Id: 5e68189f-e6ad-4e72-9e08-08dcd7f6aaeb x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; ARA:13230040|1800799024|36860700013|82310400026|376014; X-Microsoft-Antispam-Message-Info-Original: V4m/2iSR/RoamWnz2jGYOogSX9t5VbWtFR6lGVEQeqUw9WQ61ZCtGvsc56PwKjnTxa49h+wsql1qFKs9XsMGwvDc428sVPUGKHwH3oFN85CxJl4CrkBawRdOhPdSaO/ohVQXGcT+jS6ch6pOE4fgzd4Bt/BmiDHBoRnrXZ4iZLKTYjFY3M9S2z318GNVaByjo1ezPYxVKpwHirOZZETulXv2Q6d2GtLHFQVy9/E9xGsuvexzaUFauimTfRp4ptlU4ShBLTWvfCVIjNwnQlB9sM/egNhKoUIbKg5Vgpd8Sy1W2JAq0pvrH0YvFQuQ4Eqom2T2mapktXvHtBxipOQNhcXPQQZ7eogyaEMtxMd9C9jy8UpB7wmCvCUjVzlI1v4ibTInIk4daGT3U3qqDFGI+JFruC20SjJDhvlCnXqqsRKrSoWpfJg4JLjbgI+1k9wxEOzPygyxkUwGI44AhRgsSN7k+qtnNhSCt/BNubo3UzxjYgEiOOShZcZy6SeqjsXz5HzIbtQG7sc813VstjlHaoSVRmpQJ6iW29TWEEbmMdmy0Xa3fJUkAsSJx55AsZ1O8OGGHURLmBRKgs0VuqQSDiEFLL0RJKCmYJU6BbD54Q9Run6W1VeS6UEWfwHkzCgqZF4nzlnZZNHYdfHTqBuegDJvll6kkOWrLBX6YY5M7BRjTIRiL0Tgb809Zp9Rzu/fcLF2UUvZ5+28+GchY2T/yv6/xQf0qv2oNuIYwmFGF4E/k+8V+EB2NV/+k15BYoRkxFjVWirXXTc+JpLHAPfi81XjIv5b3lEhCTwByEFBRKmfI0YiwilJeXJy5ZCHdcdOv+7ehftMaiDSwktbvTT1yvFrComB1YgLpEB4XcKhxdQwqzxl6umM0u8/r6ikfPF8+B7hLznpulgMDFxiji86iubf04/EZMryDL8dy8jmsiXrTThjLV7/UUaqIL1TKq4L9E5VziXrvTqBLXfPxxeP6fKh7X9SchcsexhxUDlYoCP4JJxETOI+CvkbVBCPaVbrrJXg1U4oOyPgPfx8D6nucYYiJaD0waG/aXzycau+GIp4W9gklCj1aUQpnYWPhjtGDc23rxuPjrOtrhWzs/jLkTLURMeMfoEQK3S6OOepaYJrL27RfJAxVeRP6mXAyhBkjLyA1lYr9hnplMxOZ42K5ikz9R0nW+5jbD9evANCuc5wQ+TlJQl3T+EIBSFrbixHmrM/M+w+Fderv/hqKbqyrfwvXZtcEzV/Uu1BPGx9HybyC4hFhPNcgKmnysePFiWgQxTrTMD9/JAnve+3mwfK3F3WiN9N/J6UHrVO3sufvhEimp6YvPIFXnQsj3n17uXDFuoGd8oxLE89V6rlPR6rlO0jTYnKt+3FAe02sg24ikDiY+v59PFHXXy2PLmKXrArIpZIhlEAtPuzmHRWqPnNNw== X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; 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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ErrorRetry; CAT:NONE; SFS:(13230040)(1800799024)(82310400026)(36860700013)(35042699022)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Sep 2024 15:29:20.8793 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5e68189f-e6ad-4e72-9e08-08dcd7f6aaeb X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF000509E5.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR08MB10481 X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FORGED_SPF_HELO, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org The AArch64 FEAT_FAMINMAX extension is optional from Armv9.2-a and mandatory from Armv9.5-a. It introduces instructions for computing the floating point absolute maximum and minimum of the two vectors element-wise. This patch introduces AdvSIMD faminmax intrinsics. The intrinsics of this extension are implemented as the following builtin functions: * vamax_f16 * vamaxq_f16 * vamax_f32 * vamaxq_f32 * vamaxq_f64 * vamin_f16 * vaminq_f16 * vamin_f32 * vaminq_f32 * vaminq_f64 We are defining a new way to add AArch64 AdvSIMD intrinsics by listing all the intrinsics in a .def file and then using that .def file to initialise various data structures. This would lead to more concise code and easier addition of the new AdvSIMD intrinsics in future. The faminmax intrinsics are defined using the new approach. gcc/ChangeLog: * config/aarch64/aarch64-builtins.cc (ENTRY): Macro to parse the contents of aarch64-simd-pragma-builtins.def. (ENTRY_VHSDF): Macro to parse the contents of aarch64-simd-pragma-builtins.def. (enum aarch64_builtins): New enum values for faminmax builtins via aarch64-simd-pragma-builtins.def. (enum class aarch64_builtin_signatures): Enum class to specify the number of operands a builtin will take. (struct aarch64_pragma_builtins_data): Struct to hold data from aarch64-simd-pragma-builtins.def. (aarch64_fntype): New function to define function types of intrinsics given an object of type aarch64_pragma_builtins_data. (aarch64_init_pragma_builtins): New function to define pragma builtins. (aarch64_get_pragma_builtin): New function to get a row of aarch64_pragma_builtins, given code. (handle_arm_neon_h): Modify to call aarch64_init_pragma_builtins. (aarch64_general_check_builtin_call): Modify to check whether required flag is being used for pragma builtins. (aarch64_expand_pragma_builtin): New function to emit instructions of pragma_builtin. (aarch64_general_expand_builtin): Modify to call aarch64_expand_pragma_builtin. * config/aarch64/aarch64-option-extensions.def (AARCH64_OPT_EXTENSION): Introduce new flag for this extension. * config/aarch64/aarch64-simd.md (@aarch64_): Instruction pattern for faminmax intrinsics. * config/aarch64/aarch64.h (TARGET_FAMINMAX): Introduce new flag for this extension. * config/aarch64/iterators.md: New iterators and unspecs. * doc/invoke.texi: Document extension in AArch64 Options. * config/aarch64/aarch64-simd-pragma-builtins.def: New file to list pragma builtins. gcc/testsuite/ChangeLog: * gcc.target/aarch64/simd/faminmax-builtins-no-flag.c: New test. * gcc.target/aarch64/simd/faminmax-builtins.c: New test. --- gcc/config/aarch64/aarch64-builtins.cc | 119 ++++++++++++++++++ .../aarch64/aarch64-option-extensions.def | 2 + .../aarch64/aarch64-simd-pragma-builtins.def | 23 ++++ gcc/config/aarch64/aarch64-simd.md | 10 ++ gcc/config/aarch64/aarch64.h | 4 + gcc/config/aarch64/iterators.md | 9 ++ gcc/doc/invoke.texi | 2 + .../aarch64/simd/faminmax-builtins-no-flag.c | 10 ++ .../aarch64/simd/faminmax-builtins.c | 115 +++++++++++++++++ 9 files changed, 294 insertions(+) create mode 100644 gcc/config/aarch64/aarch64-simd-pragma-builtins.def create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/faminmax-builtins-no-flag.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/faminmax-builtins.c diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc index eb878b933fe..6266bea3b39 100644 --- a/gcc/config/aarch64/aarch64-builtins.cc +++ b/gcc/config/aarch64/aarch64-builtins.cc @@ -757,6 +757,18 @@ typedef struct #define VAR1(T, N, MAP, FLAG, A) \ AARCH64_SIMD_BUILTIN_##T##_##N##A, +#undef ENTRY +#define ENTRY(N, S, M, U, F) \ + AARCH64_##N, + +#undef ENTRY_VHSDF +#define ENTRY_VHSDF(NAME, SIGNATURE, UNSPEC, EXTENSIONS) \ + AARCH64_##NAME##_f16, \ + AARCH64_##NAME##q_f16, \ + AARCH64_##NAME##_f32, \ + AARCH64_##NAME##q_f32, \ + AARCH64_##NAME##q_f64, + enum aarch64_builtins { AARCH64_BUILTIN_MIN, @@ -829,6 +841,10 @@ enum aarch64_builtins AARCH64_RBIT, AARCH64_RBITL, AARCH64_RBITLL, + /* Pragma builtins. */ + AARCH64_PRAGMA_BUILTIN_START, +#include "aarch64-simd-pragma-builtins.def" + AARCH64_PRAGMA_BUILTIN_END, /* System register builtins. */ AARCH64_RSR, AARCH64_RSRP, @@ -947,6 +963,7 @@ const char *aarch64_scalar_builtin_types[] = { extern GTY(()) aarch64_simd_type_info aarch64_simd_types[]; +#undef ENTRY #define ENTRY(E, M, Q, G) \ {E, "__" #E, #G "__" #E, NULL_TREE, NULL_TREE, E_##M##mode, qualifier_##Q}, struct aarch64_simd_type_info aarch64_simd_types [] = { @@ -1547,6 +1564,78 @@ aarch64_init_simd_builtin_functions (bool called_from_pragma) } } +enum class aarch64_builtin_signatures +{ + binary, +}; + +#undef ENTRY +#define ENTRY(N, S, M, U, F) \ + {#N, aarch64_builtin_signatures::S, E_##M##mode, U, F}, + +#undef ENTRY_VHSDF +#define ENTRY_VHSDF(NAME, SIGNATURE, UNSPEC, EXTENSIONS) \ + ENTRY (NAME##_f16, SIGNATURE, V4HF, UNSPEC, EXTENSIONS) \ + ENTRY (NAME##q_f16, SIGNATURE, V8HF, UNSPEC, EXTENSIONS) \ + ENTRY (NAME##_f32, SIGNATURE, V2SF, UNSPEC, EXTENSIONS) \ + ENTRY (NAME##q_f32, SIGNATURE, V4SF, UNSPEC, EXTENSIONS) \ + ENTRY (NAME##q_f64, SIGNATURE, V2DF, UNSPEC, EXTENSIONS) + +/* Initialize pragma builtins. */ + +struct aarch64_pragma_builtins_data +{ + const char *name; + aarch64_builtin_signatures signature; + machine_mode mode; + int unspec; + aarch64_feature_flags required_extensions; +}; + +static aarch64_pragma_builtins_data aarch64_pragma_builtins[] = { +#include "aarch64-simd-pragma-builtins.def" +}; + +static tree +aarch64_fntype (const aarch64_pragma_builtins_data &builtin_data) +{ + auto type = aarch64_simd_builtin_type (builtin_data.mode, qualifier_none); + switch (builtin_data.signature) + { + case aarch64_builtin_signatures::binary: + return build_function_type_list (type, type, type, NULL_TREE); + default: + gcc_unreachable (); + } +} + +static void +aarch64_init_pragma_builtins () +{ + for (size_t i = 0; i < ARRAY_SIZE (aarch64_pragma_builtins); ++i) + { + auto data = aarch64_pragma_builtins[i]; + auto fntype = aarch64_fntype (data); + auto code = AARCH64_PRAGMA_BUILTIN_START + i + 1; + aarch64_builtin_decls[code] + = aarch64_general_simulate_builtin (data.name, fntype, code); + } +} + +/* If the builtin function with code CODE has an entry in + aarch64_pragma_builtins, return its entry, otherwise return null. */ + +static const aarch64_pragma_builtins_data* +aarch64_get_pragma_builtin (int code) +{ + if (!(code > AARCH64_PRAGMA_BUILTIN_START + && code < AARCH64_PRAGMA_BUILTIN_END)) + return NULL; + + auto idx = code - (AARCH64_PRAGMA_BUILTIN_START + 1); + return &aarch64_pragma_builtins[idx]; +} + /* Register the tuple type that contains NUM_VECTORS of the AdvSIMD type indexed by TYPE_INDEX. */ static void @@ -1640,6 +1729,7 @@ handle_arm_neon_h (void) aarch64_init_simd_builtin_functions (true); aarch64_init_simd_intrinsics (); + aarch64_init_pragma_builtins (); } static void @@ -2326,6 +2416,12 @@ aarch64_general_check_builtin_call (location_t location, vec, return aarch64_check_required_extensions (location, decl, AARCH64_FL_MEMTAG); + if (auto builtin_data = aarch64_get_pragma_builtin (code)) + { + auto flags = builtin_data->required_extensions; + return aarch64_check_required_extensions (location, decl, flags); + } + return true; } @@ -3189,6 +3285,25 @@ aarch64_expand_builtin_data_intrinsic (unsigned int fcode, tree exp, rtx target) return ops[0].value; } +static rtx +aarch64_expand_pragma_builtin (tree exp, rtx target, + const aarch64_pragma_builtins_data *builtin_data) +{ + expand_operand ops[3]; + auto mode = builtin_data->mode; + auto op1 = expand_normal (CALL_EXPR_ARG (exp, 0)); + auto op2 = expand_normal (CALL_EXPR_ARG (exp, 1)); + create_output_operand (&ops[0], target, mode); + create_input_operand (&ops[1], op1, mode); + create_input_operand (&ops[2], op2, mode); + + auto unspec = builtin_data->unspec; + auto icode = code_for_aarch64 (unspec, mode); + expand_insn (icode, 3, ops); + + return target; +} + /* Expand an expression EXP as fpsr or fpcr setter (depending on UNSPEC) using MODE. */ static void @@ -3369,6 +3484,9 @@ aarch64_general_expand_builtin (unsigned int fcode, tree exp, rtx target, && fcode <= AARCH64_RBITLL) return aarch64_expand_builtin_data_intrinsic (fcode, exp, target); + if (auto builtin_data = aarch64_get_pragma_builtin (fcode)) + return aarch64_expand_pragma_builtin (exp, target, builtin_data); + gcc_unreachable (); } @@ -4021,6 +4139,7 @@ aarch64_resolve_overloaded_builtin_general (location_t loc, tree function, #undef CF3 #undef CF4 #undef CF10 +#undef ENTRY_VHSDF #undef VAR1 #undef VAR2 #undef VAR3 diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def index 6998627f377..8279f5a76ea 100644 --- a/gcc/config/aarch64/aarch64-option-extensions.def +++ b/gcc/config/aarch64/aarch64-option-extensions.def @@ -234,6 +234,8 @@ AARCH64_OPT_EXTENSION("gcs", GCS, (), (), (), "gcs") AARCH64_OPT_EXTENSION("fp8", FP8, (SIMD), (), (), "fp8") +AARCH64_OPT_EXTENSION("faminmax", FAMINMAX, (SIMD), (), (), "faminmax") + #undef AARCH64_OPT_FMV_EXTENSION #undef AARCH64_OPT_EXTENSION #undef AARCH64_FMV_FEATURE diff --git a/gcc/config/aarch64/aarch64-simd-pragma-builtins.def b/gcc/config/aarch64/aarch64-simd-pragma-builtins.def new file mode 100644 index 00000000000..f432185be46 --- /dev/null +++ b/gcc/config/aarch64/aarch64-simd-pragma-builtins.def @@ -0,0 +1,23 @@ +/* AArch64 SIMD pragma builtins + Copyright (C) 2024 Free Software Foundation, Inc. + Contributed by ARM Ltd. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not see + . */ + +// faminmax +ENTRY_VHSDF (vamax, binary, UNSPEC_FAMAX, AARCH64_FL_FAMINMAX) +ENTRY_VHSDF (vamin, binary, UNSPEC_FAMIN, AARCH64_FL_FAMINMAX) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 23c03a96371..67f0fe26f93 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -9910,3 +9910,13 @@ "shl\\t%d0, %d1, #16" [(set_attr "type" "neon_shift_imm")] ) + +;; faminmax +(define_insn "@aarch64_" + [(set (match_operand:VHSDF 0 "register_operand" "=w") + (unspec:VHSDF [(match_operand:VHSDF 1 "register_operand" "w") + (match_operand:VHSDF 2 "register_operand" "w")] + FAMINMAX_UNS))] + "TARGET_FAMINMAX" + "\t%0., %1., %2." +) diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 2dfb999bea5..e754c4ea748 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -457,6 +457,10 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED enabled through +gcs. */ #define TARGET_GCS AARCH64_HAVE_ISA (GCS) +/* Floating Point Absolute Maximum/Minimum extension instructions are + enabled through +faminmax. */ +#define TARGET_FAMINMAX AARCH64_HAVE_ISA (FAMINMAX) + /* Prefer different predicate registers for the output of a predicated operation over re-using an existing input predicate. */ #define TARGET_SVE_PRED_CLOBBER (TARGET_SVE \ diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 20a318e023b..17ac5e073aa 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -1057,6 +1057,8 @@ UNSPEC_BFCVTN2 ; Used in aarch64-simd.md. UNSPEC_BFCVT ; Used in aarch64-simd.md. UNSPEC_FCVTXN ; Used in aarch64-simd.md. + UNSPEC_FAMAX ; Used in aarch64-simd.md. + UNSPEC_FAMIN ; Used in aarch64-simd.md. ;; All used in aarch64-sve2.md UNSPEC_FCVTN @@ -4463,3 +4465,10 @@ (UNSPECV_SET_FPCR "fpcr")]) (define_int_attr bits_etype [(8 "b") (16 "h") (32 "s") (64 "d")]) + +;; Iterators and attributes for faminmax + +(define_int_iterator FAMINMAX_UNS [UNSPEC_FAMAX UNSPEC_FAMIN]) + +(define_int_attr faminmax_uns_op + [(UNSPEC_FAMAX "famax") (UNSPEC_FAMIN "famin")]) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 511b8c8d311..e005d9bbfb0 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -21865,6 +21865,8 @@ Enable support for Armv8.9-a/9.4-a translation hardening extension. Enable the RCpc3 (Release Consistency) extension. @item fp8 Enable the fp8 (8-bit floating point) extension. +@item faminmax +Enable the Floating Point Absolute Maximum/Minimum extension. @end table diff --git a/gcc/testsuite/gcc.target/aarch64/simd/faminmax-builtins-no-flag.c b/gcc/testsuite/gcc.target/aarch64/simd/faminmax-builtins-no-flag.c new file mode 100644 index 00000000000..f9b683f8819 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/faminmax-builtins-no-flag.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv9-a" } */ + +#include "arm_neon.h" + +void +test (float32x4_t a, float32x4_t b) +{ + vamaxq_f32 (a, b); /* { dg-error {ACLE function 'vamaxq_f32' requires ISA extension 'faminmax'} } */ +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/faminmax-builtins.c b/gcc/testsuite/gcc.target/aarch64/simd/faminmax-builtins.c new file mode 100644 index 00000000000..dae9b6c2eea --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/faminmax-builtins.c @@ -0,0 +1,115 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O3 -march=armv9-a+faminmax" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "arm_neon.h" + +/* +** test_vamax_f16: +** famax v0.4h, v0.4h, v1.4h +** ret +*/ +float16x4_t +test_vamax_f16 (float16x4_t a, float16x4_t b) +{ + return vamax_f16 (a, b); +} + +/* +** test_vamaxq_f16: +** famax v0.8h, v0.8h, v1.8h +** ret +*/ +float16x8_t +test_vamaxq_f16 (float16x8_t a, float16x8_t b) +{ + return vamaxq_f16 (a, b); +} + +/* +** test_vamax_f32: +** famax v0.2s, v0.2s, v1.2s +** ret +*/ +float32x2_t +test_vamax_f32 (float32x2_t a, float32x2_t b) +{ + return vamax_f32 (a, b); +} + +/* +** test_vamaxq_f32: +** famax v0.4s, v0.4s, v1.4s +** ret +*/ +float32x4_t +test_vamaxq_f32 (float32x4_t a, float32x4_t b) +{ + return vamaxq_f32 (a, b); +} + +/* +** test_vamaxq_f64: +** famax v0.2d, v0.2d, v1.2d +** ret +*/ +float64x2_t +test_vamaxq_f64 (float64x2_t a, float64x2_t b) +{ + return vamaxq_f64 (a, b); +} + +/* +** test_vamin_f16: +** famin v0.4h, v0.4h, v1.4h +** ret +*/ +float16x4_t +test_vamin_f16 (float16x4_t a, float16x4_t b) +{ + return vamin_f16 (a, b); +} + +/* +** test_vaminq_f16: +** famin v0.8h, v0.8h, v1.8h +** ret +*/ +float16x8_t +test_vaminq_f16 (float16x8_t a, float16x8_t b) +{ + return vaminq_f16 (a, b); +} + +/* +** test_vamin_f32: +** famin v0.2s, v0.2s, v1.2s +** ret +*/ +float32x2_t +test_vamin_f32 (float32x2_t a, float32x2_t b) +{ + return vamin_f32 (a, b); +} + +/* +** test_vaminq_f32: +** famin v0.4s, v0.4s, v1.4s +** ret +*/ +float32x4_t +test_vaminq_f32 (float32x4_t a, float32x4_t b) +{ + return vaminq_f32 (a, b); +} + +/* +** test_vaminq_f64: +** famin v0.2d, v0.2d, v1.2d +** ret +*/ +float64x2_t +test_vaminq_f64 (float64x2_t a, float64x2_t b) +{ + return vaminq_f64 (a, b); +} From patchwork Wed Sep 18 15:28:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Saurabh Jha X-Patchwork-Id: 1986892 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256 header.s=selector1 header.b=LLoFHcD/; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.a=rsa-sha256 header.s=selector1 header.b=LLoFHcD/; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; 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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230040)(36860700013)(1800799024)(35042699022)(82310400026)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Sep 2024 15:29:24.6521 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a97273fd-147c-4ef6-4cd2-08dcd7f6ad2b X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5PEPF00014B88.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAVPR08MB9377 X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FORGED_SPF_HELO, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org The AArch64 FEAT_FAMINMAX extension is optional from Armv9.2-a and mandatory from Armv9.5-a. It introduces instructions for computing the floating point absolute maximum and minimum of the two vectors element-wise. This patch adds code generation support for famax and famin in terms of existing RTL operators. famax/famin is equivalent to first taking abs of the operands and then taking smax/smin on the results of abs. famax/famin (a, b) = smax/smin (abs (a), abs (b)) This fusion of operators is only possible when -march=armv9-a+faminmax flags are passed. We also need to pass -ffast-math flag; if we don't, then a statement like c[i] = __builtin_fmaxf16 (a[i], b[i]); is RTL expanded to UNSPEC_FMAXNM instead of smax (likewise for smin). This code generation is only available on -O2 or -O3 as that is when auto-vectorization is enabled. gcc/ChangeLog: * config/aarch64/aarch64-simd.md (*aarch64_faminmax_fused): Instruction pattern for faminmax codegen. * config/aarch64/iterators.md: Attribute for faminmax codegen. gcc/testsuite/ChangeLog: * gcc.target/aarch64/simd/faminmax-codegen-no-flag.c: New test. * gcc.target/aarch64/simd/faminmax-codegen.c: New test. * gcc.target/aarch64/simd/faminmax-no-codegen.c: New test. --- gcc/config/aarch64/aarch64-simd.md | 9 + gcc/config/aarch64/iterators.md | 3 + .../aarch64/simd/faminmax-codegen-no-flag.c | 217 ++++++++++++++ .../aarch64/simd/faminmax-codegen.c | 197 +++++++++++++ .../aarch64/simd/faminmax-no-codegen.c | 267 ++++++++++++++++++ 5 files changed, 693 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/faminmax-codegen-no-flag.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/faminmax-codegen.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/faminmax-no-codegen.c diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 67f0fe26f93..2a44aa3fcc3 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -9920,3 +9920,12 @@ "TARGET_FAMINMAX" "\t%0., %1., %2." ) + +(define_insn "*aarch64_faminmax_fused" + [(set (match_operand:VHSDF 0 "register_operand" "=w") + (FMAXMIN:VHSDF + (abs:VHSDF (match_operand:VHSDF 1 "register_operand" "w")) + (abs:VHSDF (match_operand:VHSDF 2 "register_operand" "w"))))] + "TARGET_FAMINMAX" + "\t%0., %1., %2." +) diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 17ac5e073aa..c2fcd18306e 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -4472,3 +4472,6 @@ (define_int_attr faminmax_uns_op [(UNSPEC_FAMAX "famax") (UNSPEC_FAMIN "famin")]) + +(define_code_attr faminmax_op + [(smax "famax") (smin "famin")]) diff --git a/gcc/testsuite/gcc.target/aarch64/simd/faminmax-codegen-no-flag.c b/gcc/testsuite/gcc.target/aarch64/simd/faminmax-codegen-no-flag.c new file mode 100644 index 00000000000..6688a7883b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/faminmax-codegen-no-flag.c @@ -0,0 +1,217 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O3 -ffast-math -march=armv9-a" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "arm_neon.h" + +#pragma GCC target "+nosve" + +/* +** test_vamax_f16: +** fabs v1.4h, v1.4h +** fabs v0.4h, v0.4h +** fmaxnm v0.4h, v0.4h, v1.4h +** ret +*/ +float16x4_t +test_vamax_f16 (float16x4_t a, float16x4_t b) +{ + int i; + float16x4_t c; + + for (i = 0; i < 4; ++i) { + a[i] = __builtin_fabsf16 (a[i]); + b[i] = __builtin_fabsf16 (b[i]); + c[i] = __builtin_fmaxf16 (a[i], b[i]); + } + return c; +} + +/* +** test_vamaxq_f16: +** fabs v1.8h, v1.8h +** fabs v0.8h, v0.8h +** fmaxnm v0.8h, v0.8h, v1.8h +** ret +*/ +float16x8_t +test_vamaxq_f16 (float16x8_t a, float16x8_t b) +{ + int i; + float16x8_t c; + + for (i = 0; i < 8; ++i) { + a[i] = __builtin_fabsf16 (a[i]); + b[i] = __builtin_fabsf16 (b[i]); + c[i] = __builtin_fmaxf16 (a[i], b[i]); + } + return c; +} + +/* +** test_vamax_f32: +** fabs v1.2s, v1.2s +** fabs v0.2s, v0.2s +** fmaxnm v0.2s, v0.2s, v1.2s +** ret +*/ +float32x2_t +test_vamax_f32 (float32x2_t a, float32x2_t b) +{ + int i; + float32x2_t c; + + for (i = 0; i < 2; ++i) { + a[i] = __builtin_fabsf32 (a[i]); + b[i] = __builtin_fabsf32 (b[i]); + c[i] = __builtin_fmaxf32 (a[i], b[i]); + } + return c; +} + +/* +** test_vamaxq_f32: +** fabs v1.4s, v1.4s +** fabs v0.4s, v0.4s +** fmaxnm v0.4s, v0.4s, v1.4s +** ret +*/ +float32x4_t +test_vamaxq_f32 (float32x4_t a, float32x4_t b) +{ + int i; + float32x4_t c; + + for (i = 0; i < 4; ++i) { + a[i] = __builtin_fabsf32 (a[i]); + b[i] = __builtin_fabsf32 (b[i]); + c[i] = __builtin_fmaxf32 (a[i], b[i]); + } + return c; +} + +/* +** test_vamaxq_f64: +** fabs v1.2d, v1.2d +** fabs v0.2d, v0.2d +** fmaxnm v0.2d, v0.2d, v1.2d +** ret +*/ +float64x2_t +test_vamaxq_f64 (float64x2_t a, float64x2_t b) +{ + int i; + float64x2_t c; + + for (i = 0; i < 2; ++i) { + a[i] = __builtin_fabsf64 (a[i]); + b[i] = __builtin_fabsf64 (b[i]); + c[i] = __builtin_fmaxf64 (a[i], b[i]); + } + return c; +} + +/* +** test_vamin_f16: +** fabs v1.4h, v1.4h +** fabs v0.4h, v0.4h +** fminnm v0.4h, v0.4h, v1.4h +** ret +*/ +float16x4_t +test_vamin_f16 (float16x4_t a, float16x4_t b) +{ + int i; + float16x4_t c; + + for (i = 0; i < 4; ++i) { + a[i] = __builtin_fabsf16 (a[i]); + b[i] = __builtin_fabsf16 (b[i]); + c[i] = __builtin_fminf16 (a[i], b[i]); + } + return c; +} + +/* +** test_vaminq_f16: +** fabs v1.8h, v1.8h +** fabs v0.8h, v0.8h +** fminnm v0.8h, v0.8h, v1.8h +** ret +*/ +float16x8_t +test_vaminq_f16 (float16x8_t a, float16x8_t b) +{ + int i; + float16x8_t c; + + for (i = 0; i < 8; ++i) { + a[i] = __builtin_fabsf16 (a[i]); + b[i] = __builtin_fabsf16 (b[i]); + c[i] = __builtin_fminf16 (a[i], b[i]); + } + return c; +} + +/* +** test_vamin_f32: +** fabs v1.2s, v1.2s +** fabs v0.2s, v0.2s +** fminnm v0.2s, v0.2s, v1.2s +** ret +*/ +float32x2_t +test_vamin_f32 (float32x2_t a, float32x2_t b) +{ + int i; + float32x2_t c; + + for (i = 0; i < 2; ++i) { + a[i] = __builtin_fabsf32 (a[i]); + b[i] = __builtin_fabsf32 (b[i]); + c[i] = __builtin_fminf32 (a[i], b[i]); + } + return c; +} + +/* +** test_vaminq_f32: +** fabs v1.4s, v1.4s +** fabs v0.4s, v0.4s +** fminnm v0.4s, v0.4s, v1.4s +** ret +*/ +float32x4_t +test_vaminq_f32 (float32x4_t a, float32x4_t b) +{ + int i; + float32x4_t c; + + for (i = 0; i < 4; ++i) { + a[i] = __builtin_fabsf32 (a[i]); + b[i] = __builtin_fabsf32 (b[i]); + c[i] = __builtin_fminf32 (a[i], b[i]); + } + return c; +} + +/* +** test_vaminq_f64: +** fabs v1.2d, v1.2d +** fabs v0.2d, v0.2d +** fminnm v0.2d, v0.2d, v1.2d +** ret +*/ +float64x2_t +test_vaminq_f64 (float64x2_t a, float64x2_t b) +{ + int i; + float64x2_t c; + + for (i = 0; i < 2; ++i) { + a[i] = __builtin_fabsf64 (a[i]); + b[i] = __builtin_fabsf64 (b[i]); + c[i] = __builtin_fminf64 (a[i], b[i]); + } + return c; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/faminmax-codegen.c b/gcc/testsuite/gcc.target/aarch64/simd/faminmax-codegen.c new file mode 100644 index 00000000000..d77bd905230 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/faminmax-codegen.c @@ -0,0 +1,197 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ffast-math -march=armv9-a+faminmax" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "arm_neon.h" + +#pragma GCC target "+nosve" + +/* +** test_vamax_f16: +** famax v0.4h, v1.4h, v0.4h +** ret +*/ +float16x4_t +test_vamax_f16 (float16x4_t a, float16x4_t b) +{ + int i; + float16x4_t c; + + for (i = 0; i < 4; ++i) { + a[i] = __builtin_fabsf16 (a[i]); + b[i] = __builtin_fabsf16 (b[i]); + c[i] = __builtin_fmaxf16 (a[i], b[i]); + } + return c; +} + +/* +** test_vamaxq_f16: +** famax v0.8h, v1.8h, v0.8h +** ret +*/ +float16x8_t +test_vamaxq_f16 (float16x8_t a, float16x8_t b) +{ + int i; + float16x8_t c; + + for (i = 0; i < 8; ++i) { + a[i] = __builtin_fabsf16 (a[i]); + b[i] = __builtin_fabsf16 (b[i]); + c[i] = __builtin_fmaxf16 (a[i], b[i]); + } + return c; +} + +/* +** test_vamax_f32: +** famax v0.2s, v1.2s, v0.2s +** ret +*/ +float32x2_t +test_vamax_f32 (float32x2_t a, float32x2_t b) +{ + int i; + float32x2_t c; + + for (i = 0; i < 2; ++i) { + a[i] = __builtin_fabsf32 (a[i]); + b[i] = __builtin_fabsf32 (b[i]); + c[i] = __builtin_fmaxf32 (a[i], b[i]); + } + return c; +} + +/* +** test_vamaxq_f32: +** famax v0.4s, v1.4s, v0.4s +** ret +*/ +float32x4_t +test_vamaxq_f32 (float32x4_t a, float32x4_t b) +{ + int i; + float32x4_t c; + + for (i = 0; i < 4; ++i) { + a[i] = __builtin_fabsf32 (a[i]); + b[i] = __builtin_fabsf32 (b[i]); + c[i] = __builtin_fmaxf32 (a[i], b[i]); + } + return c; +} + +/* +** test_vamaxq_f64: +** famax v0.2d, v1.2d, v0.2d +** ret +*/ +float64x2_t +test_vamaxq_f64 (float64x2_t a, float64x2_t b) +{ + int i; + float64x2_t c; + + for (i = 0; i < 2; ++i) { + a[i] = __builtin_fabsf64 (a[i]); + b[i] = __builtin_fabsf64 (b[i]); + c[i] = __builtin_fmaxf64 (a[i], b[i]); + } + return c; +} + +/* +** test_vamin_f16: +** famin v0.4h, v1.4h, v0.4h +** ret +*/ +float16x4_t +test_vamin_f16 (float16x4_t a, float16x4_t b) +{ + int i; + float16x4_t c; + + for (i = 0; i < 4; ++i) { + a[i] = __builtin_fabsf16 (a[i]); + b[i] = __builtin_fabsf16 (b[i]); + c[i] = __builtin_fminf16 (a[i], b[i]); + } + return c; +} + +/* +** test_vaminq_f16: +** famin v0.8h, v1.8h, v0.8h +** ret +*/ +float16x8_t +test_vaminq_f16 (float16x8_t a, float16x8_t b) +{ + int i; + float16x8_t c; + + for (i = 0; i < 8; ++i) { + a[i] = __builtin_fabsf16 (a[i]); + b[i] = __builtin_fabsf16 (b[i]); + c[i] = __builtin_fminf16 (a[i], b[i]); + } + return c; +} + +/* +** test_vamin_f32: +** famin v0.2s, v1.2s, v0.2s +** ret +*/ +float32x2_t +test_vamin_f32 (float32x2_t a, float32x2_t b) +{ + int i; + float32x2_t c; + + for (i = 0; i < 2; ++i) { + a[i] = __builtin_fabsf32 (a[i]); + b[i] = __builtin_fabsf32 (b[i]); + c[i] = __builtin_fminf32 (a[i], b[i]); + } + return c; +} + +/* +** test_vaminq_f32: +** famin v0.4s, v1.4s, v0.4s +** ret +*/ +float32x4_t +test_vaminq_f32 (float32x4_t a, float32x4_t b) +{ + int i; + float32x4_t c; + + for (i = 0; i < 4; ++i) { + a[i] = __builtin_fabsf32 (a[i]); + b[i] = __builtin_fabsf32 (b[i]); + c[i] = __builtin_fminf32 (a[i], b[i]); + } + return c; +} + +/* +** test_vaminq_f64: +** famin v0.2d, v1.2d, v0.2d +** ret +*/ +float64x2_t +test_vaminq_f64 (float64x2_t a, float64x2_t b) +{ + int i; + float64x2_t c; + + for (i = 0; i < 2; ++i) { + a[i] = __builtin_fabsf64 (a[i]); + b[i] = __builtin_fabsf64 (b[i]); + c[i] = __builtin_fminf64 (a[i], b[i]); + } + return c; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/faminmax-no-codegen.c b/gcc/testsuite/gcc.target/aarch64/simd/faminmax-no-codegen.c new file mode 100644 index 00000000000..3ec0a52b522 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/faminmax-no-codegen.c @@ -0,0 +1,267 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ffast-math -march=armv9-a+faminmax" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "arm_neon.h" + +#pragma GCC target "+nosve" + +/* +** test_abs_max_f16: +** fabs v1.4h, v1.4h +** fabs v0.4h, v0.4h +** fmax v0.4h, v0.4h, v1.4h +** ret +*/ +float16x4_t +test_abs_max_f16 (float16x4_t a, float16x4_t b) +{ + return vmax_f16 (vabs_f16 (a), vabs_f16 (b)); +} + +/* +** test_abs_maxnm_f16: +** fabs v1.4h, v1.4h +** fabs v0.4h, v0.4h +** fmaxnm v0.4h, v0.4h, v1.4h +** ret +*/ +float16x4_t +test_abs_maxnm_f16 (float16x4_t a, float16x4_t b) +{ + return vmaxnm_f16 (vabs_f16 (a), vabs_f16 (b)); +} + +/* +** test_abs_maxq_f16: +** fabs v1.8h, v1.8h +** fabs v0.8h, v0.8h +** fmax v0.8h, v0.8h, v1.8h +** ret +*/ +float16x8_t +test_abs_maxq_f16 (float16x8_t a, float16x8_t b) +{ + return vmaxq_f16 (vabsq_f16 (a), vabsq_f16 (b)); +} + +/* +** test_abs_maxnmq_f16: +** fabs v1.8h, v1.8h +** fabs v0.8h, v0.8h +** fmaxnm v0.8h, v0.8h, v1.8h +** ret +*/ +float16x8_t +test_abs_maxnmq_f16 (float16x8_t a, float16x8_t b) +{ + return vmaxnmq_f16 (vabsq_f16 (a), vabsq_f16 (b)); +} + +/* +** test_abs_max_f32: +** fabs v1.2s, v1.2s +** fabs v0.2s, v0.2s +** fmax v0.2s, v0.2s, v1.2s +** ret +*/ +float32x2_t +test_abs_max_f32 (float32x2_t a, float32x2_t b) +{ + return vmax_f32 (vabs_f32 (a), vabs_f32 (b)); +} + +/* +** test_abs_maxnm_f32: +** fabs v1.2s, v1.2s +** fabs v0.2s, v0.2s +** fmaxnm v0.2s, v0.2s, v1.2s +** ret +*/ +float32x2_t +test_abs_maxnm_f32 (float32x2_t a, float32x2_t b) +{ + return vmaxnm_f32 (vabs_f32 (a), vabs_f32 (b)); +} + +/* +** test_abs_maxq_f32: +** fabs v1.4s, v1.4s +** fabs v0.4s, v0.4s +** fmax v0.4s, v0.4s, v1.4s +** ret +*/ +float32x4_t +test_abs_maxq_f32 (float32x4_t a, float32x4_t b) +{ + return vmaxq_f32 (vabsq_f32 (a), vabsq_f32 (b)); +} + +/* +** test_abs_maxnmq_f32: +** fabs v1.4s, v1.4s +** fabs v0.4s, v0.4s +** fmaxnm v0.4s, v0.4s, v1.4s +** ret +*/ +float32x4_t +test_abs_maxnmq_f32 (float32x4_t a, float32x4_t b) +{ + return vmaxnmq_f32 (vabsq_f32 (a), vabsq_f32 (b)); +} + +/* +** test_abs_maxq_f64: +** fabs v1.2d, v1.2d +** fabs v0.2d, v0.2d +** fmax v0.2d, v0.2d, v1.2d +** ret +*/ +float64x2_t +test_abs_maxq_f64 (float64x2_t a, float64x2_t b) +{ + return vmaxq_f64 (vabsq_f64 (a), vabsq_f64 (b)); +} + +/* +** test_abs_maxnmq_f64: +** fabs v1.2d, v1.2d +** fabs v0.2d, v0.2d +** fmaxnm v0.2d, v0.2d, v1.2d +** ret +*/ +float64x2_t +test_abs_maxnmq_f64 (float64x2_t a, float64x2_t b) +{ + return vmaxnmq_f64 (vabsq_f64 (a), vabsq_f64 (b)); +} + +/* +** test_abs_min_f16: +** fabs v1.4h, v1.4h +** fabs v0.4h, v0.4h +** fmin v0.4h, v0.4h, v1.4h +** ret +*/ +float16x4_t +test_abs_min_f16 (float16x4_t a, float16x4_t b) +{ + return vmin_f16 (vabs_f16 (a), vabs_f16 (b)); +} + +/* +** test_abs_minnm_f16: +** fabs v1.4h, v1.4h +** fabs v0.4h, v0.4h +** fminnm v0.4h, v0.4h, v1.4h +** ret +*/ +float16x4_t +test_abs_minnm_f16 (float16x4_t a, float16x4_t b) +{ + return vminnm_f16 (vabs_f16 (a), vabs_f16 (b)); +} + +/* +** test_abs_minq_f16: +** fabs v1.8h, v1.8h +** fabs v0.8h, v0.8h +** fmin v0.8h, v0.8h, v1.8h +** ret +*/ +float16x8_t +test_abs_minq_f16 (float16x8_t a, float16x8_t b) +{ + return vminq_f16 (vabsq_f16 (a), vabsq_f16 (b)); +} + +/* +** test_abs_minnmq_f16: +** fabs v1.8h, v1.8h +** fabs v0.8h, v0.8h +** fminnm v0.8h, v0.8h, v1.8h +** ret +*/ +float16x8_t +test_abs_minnmq_f16 (float16x8_t a, float16x8_t b) +{ + return vminnmq_f16 (vabsq_f16 (a), vabsq_f16 (b)); +} + +/* +** test_abs_min_f32: +** fabs v1.2s, v1.2s +** fabs v0.2s, v0.2s +** fmin v0.2s, v0.2s, v1.2s +** ret +*/ +float32x2_t +test_abs_min_f32 (float32x2_t a, float32x2_t b) +{ + return vmin_f32 (vabs_f32 (a), vabs_f32 (b)); +} + +/* +** test_abs_minnm_f32: +** fabs v1.2s, v1.2s +** fabs v0.2s, v0.2s +** fminnm v0.2s, v0.2s, v1.2s +** ret +*/ +float32x2_t +test_abs_minnm_f32 (float32x2_t a, float32x2_t b) +{ + return vminnm_f32 (vabs_f32 (a), vabs_f32 (b)); +} + +/* +** test_abs_minq_f32: +** fabs v1.4s, v1.4s +** fabs v0.4s, v0.4s +** fmin v0.4s, v0.4s, v1.4s +** ret +*/ +float32x4_t +test_abs_minq_f32 (float32x4_t a, float32x4_t b) +{ + return vminq_f32 (vabsq_f32 (a), vabsq_f32 (b)); +} + +/* +** test_abs_minnmq_f32: +** fabs v1.4s, v1.4s +** fabs v0.4s, v0.4s +** fminnm v0.4s, v0.4s, v1.4s +** ret +*/ +float32x4_t +test_abs_minnmq_f32 (float32x4_t a, float32x4_t b) +{ + return vminnmq_f32 (vabsq_f32 (a), vabsq_f32 (b)); +} + +/* +** test_abs_minq_f64: +** fabs v1.2d, v1.2d +** fabs v0.2d, v0.2d +** fmin v0.2d, v0.2d, v1.2d +** ret +*/ +float64x2_t +test_abs_minq_f64 (float64x2_t a, float64x2_t b) +{ + return vminq_f64 (vabsq_f64 (a), vabsq_f64 (b)); +} + +/* +** test_abs_minnmq_f64: +** fabs v1.2d, v1.2d +** fabs v0.2d, v0.2d +** fminnm v0.2d, v0.2d, v1.2d +** ret +*/ +float64x2_t +test_abs_minnmq_f64 (float64x2_t a, float64x2_t b) +{ + return vminnmq_f64 (vabsq_f64 (a), vabsq_f64 (b)); +}