From patchwork Tue Sep 17 06:21:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 1986679 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20230601 header.b=OY+T/c/z; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X7pKW2CQXz1y1g for ; Wed, 18 Sep 2024 16:15:11 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 97E4988E6B; Wed, 18 Sep 2024 08:14:48 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="OY+T/c/z"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 81B5A88D51; Tue, 17 Sep 2024 08:22:04 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,SPF_HELO_NONE, SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id D35EA88D52 for ; Tue, 17 Sep 2024 08:22:00 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=l.rubusch@gmail.com Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-42ca5447142so8012695e9.2 for ; Mon, 16 Sep 2024 23:22:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726554120; x=1727158920; darn=lists.denx.de; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bO6I76dQapb5ZT3c2I1rMz/X1xbv1+w8Kn71VNxQ6nQ=; b=OY+T/c/z9tCZia1h2Yub7XAOINEfUQGxZolM8/q63VBgGzk6RoCzvgLq0ZpxavmHJn e6YfagsivlAKezJNY1NNS1xXK2e1VoZYH5v3iB5mcCHtiHj0NfWtpbVyrjGkY4WKMKJr hduaF5JSqoxwFDXEbUBoPTAmvejT8jM+/Fzbvo2XVe9MwbyN2nBx0KhjIw2DbYSPHOaX TaXcWDbTOvMjLVTdB583HHxs7ALK/Nlgl8LH7YVFpdDnWVsbUKlkAxzHLyH3wm/pmQ7j E9+QqhjCWqWre5wbpJLXk3iBkPtAc9v2XTnEmI9v+Ft4IShPLeBqNT8IrCB+p7RvvqUW vW8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726554120; x=1727158920; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bO6I76dQapb5ZT3c2I1rMz/X1xbv1+w8Kn71VNxQ6nQ=; b=I5MiQCD4H3WrGXq8KfdlNvFeGB+OncbOTvNoAz9Q4lgRlv7QcKtKa/psKX0y8zfEDS 5eYMdCo/GOweusmAnGQoRpxMb5/0lrvfCvZOvV6cvlo7x9OyfXvnvmmzEy67FfFdCAtc zrcb1ylaw5w6hZpHOpuE/n+F+NWf6RAdryLzkytMcQnDDSMU/yweu2xkxn2E2KKvSorK i2Mcg/wVxJR8rtoImekYRLk2oXkpMmqYrw+OX+FEBHg14rmjttKEkBGbx5UojzI6a/4/ idECKDpTGBqLYLMUnv926cUa/XssDsFbEbufju8j10YgEaIW3WTPxRy1DDODkx3C2zoX eVGw== X-Gm-Message-State: AOJu0Yws8hxpnB2mes0o6Q7t5y8GYnXNtJkj6LysXi8bM5kCAsh9/6Cw x8h4gjtd3870HjzhWkdJK94PgMJP4W2/LzqYtXZPFYcEgEFQHUH14kHTMQ== X-Google-Smtp-Source: AGHT+IFgl/Sa5egw7tR/EwF65vT3T6QClDXvMiTKOcNd9fka/LaRmb+YYFw5kE9sOzX8qIsFPHXZbA== X-Received: by 2002:a5d:6c66:0:b0:374:ca43:ac00 with SMTP id ffacd0b85a97d-378c2d051f3mr5627158f8f.4.1726554119723; Mon, 16 Sep 2024 23:21:59 -0700 (PDT) Received: from fc8b2ad344cc.pool3007.local ([83.68.141.146]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9061328e61sm403556366b.196.2024.09.16.23.21.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Sep 2024 23:21:59 -0700 (PDT) From: Lothar Rubusch To: u-boot@lists.denx.de, trini@konsulko.com, marex@denx.de, simon.k.r.goldschmidt@gmail.com, tien.fong.chee@intel.com Cc: l.rubusch@gmail.com Subject: [PATCH v2 1/7] doc: board: enclustra: add Enclustra Intel AA1 SoM Date: Tue, 17 Sep 2024 06:21:51 +0000 Message-Id: <20240917062157.3181-2-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240917062157.3181-1-l.rubusch@gmail.com> References: <20240917062157.3181-1-l.rubusch@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 18 Sep 2024 08:14:47 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Start documentation section for Enclustra. Cover Enclustra Intel SoMs and related carrier board setups. - Mercury AA1 (Arria10) Signed-off-by: Lothar Rubusch --- doc/board/enclustra/index.rst | 9 ++ doc/board/enclustra/mercury-aa1.rst | 207 ++++++++++++++++++++++++++++ doc/board/index.rst | 1 + 3 files changed, 217 insertions(+) create mode 100644 doc/board/enclustra/index.rst create mode 100644 doc/board/enclustra/mercury-aa1.rst diff --git a/doc/board/enclustra/index.rst b/doc/board/enclustra/index.rst new file mode 100644 index 0000000000..00727d0861 --- /dev/null +++ b/doc/board/enclustra/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Enclustra +========= + +.. toctree:: + :maxdepth: 2 + + mercury-aa1 diff --git a/doc/board/enclustra/mercury-aa1.rst b/doc/board/enclustra/mercury-aa1.rst new file mode 100644 index 0000000000..7c82fed212 --- /dev/null +++ b/doc/board/enclustra/mercury-aa1.rst @@ -0,0 +1,207 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later +.. sectionauthor:: Lothar Rubusch + +Mercury AA1 Module (Arria1 10) +============================== + +- SoM: https://www.enclustra.com/en/products/system-on-chip-modules/mercury-aa1/ +- Carrier board Mercury+ ST1: https://www.enclustra.com/en/products/base-boards/mercury-st1/ +- Carrier board Mercury+ PE1: https://www.enclustra.com/en/products/base-boards/mercury-pe1-200-300-400/ +- Carrier board Mercury+ PE3: https://www.enclustra.com/en/products/base-boards/mercury-pe3/ + +There are slightly different variants of the AA1 SoM, going by the identifier. + +- Me-aa1-270-2i2-d11e-nfx3 +- Me-aa1-270-3e4-d11e-nfx3 +- Me-aa1-480-2i3-d12e-nfx3 + +The u-boot setup is specific to a quartus design. Generate handoff files from +the design. Pass them to a python script to produce a handoff.h file. This is +needed as input for building the device-tree for u-boot. Eventually, building +the final u-boot depends on the particular Quartus design, the particular +carrier board, the selected boot media and boot mode. + +Enclustra provides reference design examples which can be built with +OpenEmbedded using their meta-layer. + +- Reference Design AA1 on ST1: https://github.com/enclustra/Mercury_AA1_ST1_Reference_Design +- Reference Design AA1 on PE1: https://github.com/enclustra/Mercury_AA1_PE1_Reference_Design +- Reference Design AA1 on PE3: https://github.com/enclustra/Mercury_AA1_PE3_Reference_Design +- OpenEmbedded meta-layer: https://github.com/enclustra/meta-enclustra-socfpga + +Quick Start +----------- + +- Setup and build a Quartus design project +- Obtain the hps.xml file from the Quartus design project +- Generate the handoff.h file for u-boot +- Adjust the device-tree file according to your setup +- Build u-boot +- Flash u-boot + +Build U-Boot +------------ + +The Quartus design produces a design specific ``hps.xml``, an ``emif.xml`` and +a corresponding ``id`` file contained in a directory ``handoff``. + +Generate the handoff.h file for u-boot, from a provided ``hps.xml`` using the +script provided in u-boot. + +.. code-block:: bash + + $ arch/arm/mach-socfpga/qts-filter-a10.sh /hps.xml arch/arm/dts/socfpga_arria10_mercury_aa1_handoff.h + +Adjust the device-tree file according to your setup. Follow the comments in the +file. + +.. code-block:: bash + + $ vi ./arch/arm/dts/enclustra-aa1.dts + +Build u-boot. Source your favorite toolchain for ARM first. + +.. code-block:: bash + + $ make socfpga_enclustra_mercury_aa1_defconfig + $ make -j8 + +Setup and compile a boot script as needed. Depending on the boot-mode select +``sd-aa1.cmd`` for SD/eMMC, or ``qspi-aa1.cmd`` for QSPI flash. Also, +optionally prepare an environment file. Examples of boot command files and +environment files are provided. + +.. code-block:: bash + + $ ./tools/mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n "Uboot mmc startscript" -d board/enclustra/bootscripts/sd-aa1.cmd boot.scr + $ ./tools/mkenvimage -s 0x80000 -o uboot.env board/enclustra/mercury_aa1/mercury_aa1.env + +Device-Tree setup +----------------- + +The basic u-boot device-tree fragments are provided here. The handoff tools +will generate further u-boot device-tree fragments. The various .dtsi files +then need to be included in a top-level .dts file. + +Flash the U-Boot Binary to a Micro SD Card +------------------------------------------ + +The following example describes the full approach. Prepare a micro SD card with +three partitions as follows e.g. on /dev/sda (check before): + +* ``type=c, start=2048, size=409600`` +* ``type=a2, start=411648, size=14336`` +* ``type=83, start=425984, size=1619968`` + +.. code-block:: bash + + $ cat ./partitionmap.txt + start= 2048, size= 102400, type=b, bootable + start= 104448, size= 4096, type=a2 + start= 108544, size= 819200, type=83 + + $ sudo sfdisk /dev/sde < ./partitionmap.txt + +Note: The ``bitstream.itb`` is needed to start the bootloader. A kernel +``devicetree.dtb`` is needed to boot into the system. Both are not part of +u-boot, but are be provided through OpenEmbedded using Enclustra's meta-layer. + +Generally the bitstream files depend on the logic design, but the meta-layer +provides a demo design. Copy the ``bitstream.periph.rbf`` and +``bitstream.core.rbf`` from your design or OpenEmbedded's deploy directory. The +``bitstream.its`` in board/enclustra then is used to bundle them. + + .. code-block:: bash + + $ cp /bitstream.periph.rbf ./board/enclustra/mercury_aa1/ + $ cp /bitstream.core.rbf ./board/enclustra/mercury_aa1/ + $ ./tools/mkimage -E -f ./board/enclustra/mercury_aa1/bitstream.its bitstream.itb + +Format the SD card, and copy the following artifacts to the mounted boot +partition, e.g. on /dev/sda. + + .. code-block:: bash + + $ mkfs.vfat -n boot /dev/sda1 + $ mount /dev/sda1 /media/boot + $ cp ./{boot.scr,u-boot.img,uboot.env,bitstream.itb,Image,devicetree.dtb} /media/boot/ + $ umount /dev/sda1 + +Flash the SPL directly. + + .. code-block:: bash + + $ dd if=./spl/u-boot-splx4.sfp of=/dev/sda2 conv=fdatasync bs=4k status=progress + +Format and flash a rootfs from image or files to the third partition. + + .. code-block:: bash + + $ mkfs.ext4 -L rootfs /dev/sda3 + $ mount /dev/sda3 /media/rootfs + $ tar xf ./rootfs.tar -C /media/rootfs + $ umount /dev/sda3 + +Boot Media +---------- + +Alternative boot media are possible as officially documented by Enclustra. + +* Micro-SD card +* eMMC +* QSPI + +Note: eMMC and QSPI can be flashed from off the u-boot shell. Usually after +flashing, the coorect boot mode needs to be set by a BSEL switch. Approaches +are described consistently in the official Enclustra documentation according to +their releases mentioned as links. + +Before turning on the setup, make sure to have the correct voltage configured +at the carrier board, using the jumpers on the voltage pin header. Also make +sure to have switched to the correct boot media using typically some dip +switches to be found on the carrier board. + +Boot Log +-------- + +The demo shows booting a AA1 + ST1 setup and stopping at the u-boot shell. + +Here is the console output:: + + U-Boot SPL 2024.10-rc4-00416-gf0b9c383e6c3 (Sep 08 2024 - 14:03:59 +0000) + FPGA: Checking FPGA configuration setting ... + FPGA: Start to program peripheral/full bitstream ... + FPGA: Early Release Succeeded. + FPGA: Checking FPGA configuration setting ... + FPGA: Start to program peripheral/full bitstream ... + FPGA: Early Release Succeeded. + + U-Boot SPL 2024.10-rc4-00416-gf0b9c383e6c3 (Sep 08 2024 - 14:03:59 +0000) + DDRCAL: Success + DDRCAL: Scrubbing ECC RAM (2048 MiB). + DDRCAL: Scrubbing ECC RAM done. + FPGA: Checking FPGA configuration setting ... + FPGA: Start to program core bitstream ... + Full Configuration Succeeded. + FPGA: Enter user mode. + Trying to boot from MMC1 + + + U-Boot 2024.10-rc4-00416-gf0b9c383e6c3 (Sep 08 2024 - 14:03:59 +0000)socfpga_arria10 + + CPU: Altera SoCFPGA Arria 10 + BOOT: SD/MMC External Transceiver (1.8V) + Model: Enclustra Mercury+ AA1 + DRAM: 2 GiB + Core: 80 devices, 20 uclasses, devicetree: separate + MMC: dwmmc0@ff808000: 0 + Loading Environment from FAT... OK + In: serial + Out: serial + Err: serial + Model: Enclustra Mercury+ AA1 + ethaddr set to 20:B0:F7:06:0D:BE + eth1addr set to 20:B0:F7:06:0D:BF + Net: eth0: ethernet@ff800000 + => + diff --git a/doc/board/index.rst b/doc/board/index.rst index 417c128c7a..42244a689b 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -24,6 +24,7 @@ Board-specific doc congatec/index coreboot/index emulation/index + enclustra/index gateworks/index google/index highbank/index From patchwork Tue Sep 17 06:21:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 1986680 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20230601 header.b=hJsiV+BC; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X7pKb1bGlz1y1g for ; Wed, 18 Sep 2024 16:15:15 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id E8D7288E97; Wed, 18 Sep 2024 08:14:48 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="hJsiV+BC"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 0D90A88D2C; Tue, 17 Sep 2024 08:22:05 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,SPF_HELO_NONE, SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [IPv6:2a00:1450:4864:20::62a]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 6995388D68 for ; Tue, 17 Sep 2024 08:22:01 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=l.rubusch@gmail.com Received: by mail-ej1-x62a.google.com with SMTP id a640c23a62f3a-a8a765f980dso95577466b.1 for ; Mon, 16 Sep 2024 23:22:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726554121; x=1727158921; darn=lists.denx.de; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XuXUBbV1hZTsObqmbjXXCuUwHIF3eQ3REbQ/6WwkCvs=; b=hJsiV+BCdIg4OYlcs7ZbDIgscKRDCx9JuG7pa1ROCALSKVkbJoQdzNJ7jJrBz8FpwJ 3lXZFkrtEShOWVjWCtFBMdxj7ygkBBakCbKEMornafI+BtPw/NXLjjl9/46LQqDLlnlk pIaUFsc540S6vt09lk87/N57CsbwdwKPDQpot0yCyrzDMXIKeo9kzEFyRqkWjT/yb4qP Y9n002Oe06xVjCf/Rv+XAHnlRTYf8U7y9Ly2YORUl20XCCaPlMyySI1o6aopdi1MQG66 7ONtkKDO7iB3Lh4GMLaO3ABXjYeWnTcwK/ENjirJi7uvVvmOq/ONxgDM1vsdKMv9Gjnw JYeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726554121; x=1727158921; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XuXUBbV1hZTsObqmbjXXCuUwHIF3eQ3REbQ/6WwkCvs=; b=CxDqwICn41d8f8hUxCE8iK14n3RbhYhfyB12zT0bAjlSfOsvxu5aa1exDdXTG7rEdh 1nhlm77yUwPW52pYCk8UdGQU19JmpwFs4s4PYDeGV2OJtDqi+CG56Wh48GBsrq1sGzp9 5Dfq4B3adyXCRRgbxOFVJvZt5Gkz/DmPf6MlerepzdjN4DKowUrA+JSPgPOcfS0WCZLW WflRhpVDQ801sSCVQ7suvVJIwLsXyUEt06kkAjjVhFYi6VOw04RpvTPFOO1L8FAcBj29 SI8JAgvxYUmNl00BZp2gBT//X4OALakHxQkMv4A6bGgH7qZOsP1QhMvctwZL0sA5k8fw kD9Q== X-Gm-Message-State: AOJu0Yx9GADWIEpDY9t43D/9RfKs7FSqEzLkx93m79aDvRkbI3QblJ80 VSzM+qC8CT/wlbtsyXKaSWA19IB/zQU6OX1NCn1zpNwnVDKvyzSE44luB0qa X-Google-Smtp-Source: AGHT+IE2jC0Y1mg2D4xZEYiBBLrxQcAhQOYzSup2wk+KtddflCVdM6KHWA6qHm3LlhWMrJEu3mypwg== X-Received: by 2002:a17:907:3fa4:b0:a86:9e3f:fdc8 with SMTP id a640c23a62f3a-a902941dc78mr828008466b.4.1726554120707; Mon, 16 Sep 2024 23:22:00 -0700 (PDT) Received: from fc8b2ad344cc.pool3007.local ([83.68.141.146]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9061328e61sm403556366b.196.2024.09.16.23.21.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Sep 2024 23:22:00 -0700 (PDT) From: Lothar Rubusch To: u-boot@lists.denx.de, trini@konsulko.com, marex@denx.de, simon.k.r.goldschmidt@gmail.com, tien.fong.chee@intel.com Cc: l.rubusch@gmail.com Subject: [PATCH v2 2/7] ARM: dts: socfpga: add Enclustra Intel AA1 Date: Tue, 17 Sep 2024 06:21:52 +0000 Message-Id: <20240917062157.3181-3-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240917062157.3181-1-l.rubusch@gmail.com> References: <20240917062157.3181-1-l.rubusch@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 18 Sep 2024 08:14:47 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Introduce device-tree files for Enclustra Intel AA1 SoMs and related support. - Mercury AA1 The setup depends on a selected boot mode. Various fragments for SD/MMC and QSPI flash boot are provided. In combination, the following Enclustra carrier boards are supported: - ST1 - PE1 - PE3 Signed-off-by: Andreas Buerkler Signed-off-by: Lothar Rubusch --- arch/arm/dts/ME-AA1-270-2I2-D11E-NFX3.dtsi | 14 + arch/arm/dts/ME-AA1-270-3E4-D11E-NFX3.dtsi | 14 + arch/arm/dts/ME-AA1-480-2I3-D12E-NFX3.dtsi | 15 + arch/arm/dts/Makefile | 2 + arch/arm/dts/enclustra-aa1.dts | 32 ++ .../dts/socfpga_arria10_mercury_aa1_handoff.h | 307 ++++++++++++++++++ .../dts/socfpga_enclustra_mercury_aa1.dtsi | 179 ++++++++++ ...cfpga_enclustra_mercury_aa1_qspi_boot.dtsi | 18 + ...fpga_enclustra_mercury_aa1_sdmmc_boot.dtsi | 18 + .../dts/socfpga_enclustra_mercury_pe1.dtsi | 7 + .../dts/socfpga_enclustra_mercury_pe3.dtsi | 8 + .../dts/socfpga_enclustra_mercury_st1.dtsi | 8 + 12 files changed, 622 insertions(+) create mode 100644 arch/arm/dts/ME-AA1-270-2I2-D11E-NFX3.dtsi create mode 100644 arch/arm/dts/ME-AA1-270-3E4-D11E-NFX3.dtsi create mode 100644 arch/arm/dts/ME-AA1-480-2I3-D12E-NFX3.dtsi create mode 100644 arch/arm/dts/enclustra-aa1.dts create mode 100644 arch/arm/dts/socfpga_arria10_mercury_aa1_handoff.h create mode 100644 arch/arm/dts/socfpga_enclustra_mercury_aa1.dtsi create mode 100644 arch/arm/dts/socfpga_enclustra_mercury_aa1_qspi_boot.dtsi create mode 100644 arch/arm/dts/socfpga_enclustra_mercury_aa1_sdmmc_boot.dtsi create mode 100644 arch/arm/dts/socfpga_enclustra_mercury_pe1.dtsi create mode 100644 arch/arm/dts/socfpga_enclustra_mercury_pe3.dtsi create mode 100644 arch/arm/dts/socfpga_enclustra_mercury_st1.dtsi diff --git a/arch/arm/dts/ME-AA1-270-2I2-D11E-NFX3.dtsi b/arch/arm/dts/ME-AA1-270-2I2-D11E-NFX3.dtsi new file mode 100644 index 0000000000..75550a77c9 --- /dev/null +++ b/arch/arm/dts/ME-AA1-270-2I2-D11E-NFX3.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/ { + model = "Enclustra Mercury+ AA1"; + + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x80000000>; /* 2GB */ + }; +}; diff --git a/arch/arm/dts/ME-AA1-270-3E4-D11E-NFX3.dtsi b/arch/arm/dts/ME-AA1-270-3E4-D11E-NFX3.dtsi new file mode 100644 index 0000000000..75550a77c9 --- /dev/null +++ b/arch/arm/dts/ME-AA1-270-3E4-D11E-NFX3.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/ { + model = "Enclustra Mercury+ AA1"; + + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x80000000>; /* 2GB */ + }; +}; diff --git a/arch/arm/dts/ME-AA1-480-2I3-D12E-NFX3.dtsi b/arch/arm/dts/ME-AA1-480-2I3-D12E-NFX3.dtsi new file mode 100644 index 0000000000..9ba850a84b --- /dev/null +++ b/arch/arm/dts/ME-AA1-480-2I3-D12E-NFX3.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/ { + model = "Enclustra Mercury+ AA1"; + + /* The module is equipped with 4Gbyte RAM but U-Boot limits the size to 2 Gbyte */ + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x80000000>; /* 2GB */ + }; +}; diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 64007a20e6..2fcc4512ef 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -414,6 +414,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_n5x_socdk.dtb \ socfpga_stratix10_socdk.dtb +dtb-$(CONFIG_TARGET_SOCFPGA_ENCLUSTRA_MERCURY_AA1) += enclustra-aa1.dtb + dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \ dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \ diff --git a/arch/arm/dts/enclustra-aa1.dts b/arch/arm/dts/enclustra-aa1.dts new file mode 100644 index 0000000000..09df8c846a --- /dev/null +++ b/arch/arm/dts/enclustra-aa1.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +/* arria10 family - NB: keep the order of the includes */ +#include "socfpga_arria10.dtsi" +#include "socfpga_arria10-u-boot.dtsi" + +/* The generated handoff.h goes here */ +#include "socfpga_arria10_mercury_aa1_handoff.h" + +/* Generic arria10 glue */ +#include "socfpga_arria10-handoff.dtsi" +#include "socfpga_arria10_handoff_u-boot.dtsi" +#include "socfpga_enclustra_mercury_aa1.dtsi" + +/* Select the boot mode: sd/mmc or qspi */ +//#include "socfpga_enclustra_mercury_aa1_qspi_boot.dtsi" +#include "socfpga_enclustra_mercury_aa1_sdmmc_boot.dtsi" + +/* Select the carrier board */ +//#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +//#include "socfpga_enclustra_mercury_pe3.dtsi" + +/* Select the type of AA1 module */ +//#include "ME-AA1-270-2I2-D11E-NFX3.dtsi" +//#include "ME-AA1-270-3E4-D11E-NFX3.dtsi" +#include "ME-AA1-480-2I3-D12E-NFX3.dtsi" diff --git a/arch/arm/dts/socfpga_arria10_mercury_aa1_handoff.h b/arch/arm/dts/socfpga_arria10_mercury_aa1_handoff.h new file mode 100644 index 0000000000..46e7e3c18b --- /dev/null +++ b/arch/arm/dts/socfpga_arria10_mercury_aa1_handoff.h @@ -0,0 +1,307 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Intel Arria 10 SoCFPGA configuration + * + * Copyright (C) 2024 Enclustra GmbH + */ + +#ifndef __SOCFPGA_ARRIA10_CONFIG_H__ +#define __SOCFPGA_ARRIA10_CONFIG_H__ + +/* Clocks */ +#define CB_INTOSC_LS_CLK_HZ 60000000 +#define EMAC0_CLK_HZ 250000000 +#define EMAC1_CLK_HZ 250000000 +#define EMAC2_CLK_HZ 250000000 +#define EOSC1_CLK_HZ 33333000 +#define F2H_FREE_CLK_HZ 200000000 +#define H2F_USER0_CLK_HZ 100000000 +#define H2F_USER1_CLK_HZ 50000000 +#define L3_MAIN_FREE_CLK_HZ 400000000 +#define SDMMC_CLK_HZ 200000000 +#define TPIU_CLK_HZ 100000000 +#define MAINPLLGRP_CNTR15CLK_CNT 900 +#define MAINPLLGRP_CNTR2CLK_CNT 900 +#define MAINPLLGRP_CNTR3CLK_CNT 900 +#define MAINPLLGRP_CNTR4CLK_CNT 900 +#define MAINPLLGRP_CNTR5CLK_CNT 900 +#define MAINPLLGRP_CNTR6CLK_CNT 9 +#define MAINPLLGRP_CNTR7CLK_CNT 19 +#define MAINPLLGRP_CNTR7CLK_SRC 0 +#define MAINPLLGRP_CNTR8CLK_CNT 39 +#define MAINPLLGRP_CNTR9CLK_CNT 900 +#define MAINPLLGRP_CNTR9CLK_SRC 0 +#define MAINPLLGRP_MPUCLK_CNT 0 +#define MAINPLLGRP_MPUCLK_SRC 0 +#define MAINPLLGRP_NOCCLK_CNT 0 +#define MAINPLLGRP_NOCCLK_SRC 0 +#define MAINPLLGRP_NOCDIV_CSATCLK 0 +#define MAINPLLGRP_NOCDIV_CSPDBGCLK 1 +#define MAINPLLGRP_NOCDIV_CSTRACECLK 0 +#define MAINPLLGRP_NOCDIV_L4MAINCLK 0 +#define MAINPLLGRP_NOCDIV_L4MPCLK 1 +#define MAINPLLGRP_NOCDIV_L4SPCLK 2 +#define MAINPLLGRP_VCO0_PSRC 0 +#define MAINPLLGRP_VCO1_DENOM 32 +#define MAINPLLGRP_VCO1_NUMER 1980 +#define PERPLLGRP_CNTR2CLK_CNT 7 +#define PERPLLGRP_CNTR2CLK_SRC 1 +#define PERPLLGRP_CNTR3CLK_CNT 900 +#define PERPLLGRP_CNTR3CLK_SRC 1 +#define PERPLLGRP_CNTR4CLK_CNT 19 +#define PERPLLGRP_CNTR4CLK_SRC 1 +#define PERPLLGRP_CNTR5CLK_CNT 499 +#define PERPLLGRP_CNTR5CLK_SRC 1 +#define PERPLLGRP_CNTR6CLK_CNT 900 +#define PERPLLGRP_CNTR6CLK_SRC 0 +#define PERPLLGRP_CNTR7CLK_CNT 900 +#define PERPLLGRP_CNTR8CLK_CNT 900 +#define PERPLLGRP_CNTR8CLK_SRC 0 +#define PERPLLGRP_CNTR9CLK_CNT 900 +#define PERPLLGRP_EMACCTL_EMAC0SEL 0 +#define PERPLLGRP_EMACCTL_EMAC1SEL 0 +#define PERPLLGRP_EMACCTL_EMAC2SEL 0 +#define PERPLLGRP_GPIODIV_GPIODBCLK 32000 +#define PERPLLGRP_VCO0_PSRC 0 +#define PERPLLGRP_VCO1_DENOM 32 +#define PERPLLGRP_VCO1_NUMER 1980 +#define CLKMGR_TESTIOCTRL_DEBUGCLKSEL 16 +#define CLKMGR_TESTIOCTRL_MAINCLKSEL 8 +#define CLKMGR_TESTIOCTRL_PERICLKSEL 8 +#define ALTERAGRP_MPUCLK_MAINCNT 1 +#define ALTERAGRP_MPUCLK_PERICNT 900 +#define ALTERAGRP_NOCCLK_MAINCNT 4 +#define ALTERAGRP_NOCCLK_PERICNT 900 +#define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \ + (ALTERAGRP_MPUCLK_MAINCNT)) +#define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT << 16) | \ + (ALTERAGRP_NOCCLK_MAINCNT)) + +/* Pin Mux Configuration */ +#define CONFIG_IO_10_INPUT_BUF_EN 1 +#define CONFIG_IO_10_PD_DRV_STRG 10 +#define CONFIG_IO_10_PD_SLW_RT 1 +#define CONFIG_IO_10_PU_DRV_STRG 8 +#define CONFIG_IO_10_PU_SLW_RT 1 +#define CONFIG_IO_10_RTRIM 1 +#define CONFIG_IO_10_WK_PU_EN 0 +#define CONFIG_IO_11_INPUT_BUF_EN 1 +#define CONFIG_IO_11_PD_DRV_STRG 10 +#define CONFIG_IO_11_PD_SLW_RT 1 +#define CONFIG_IO_11_PU_DRV_STRG 8 +#define CONFIG_IO_11_PU_SLW_RT 1 +#define CONFIG_IO_11_RTRIM 1 +#define CONFIG_IO_11_WK_PU_EN 0 +#define CONFIG_IO_12_INPUT_BUF_EN 1 +#define CONFIG_IO_12_PD_DRV_STRG 10 +#define CONFIG_IO_12_PD_SLW_RT 1 +#define CONFIG_IO_12_PU_DRV_STRG 8 +#define CONFIG_IO_12_PU_SLW_RT 1 +#define CONFIG_IO_12_RTRIM 1 +#define CONFIG_IO_12_WK_PU_EN 0 +#define CONFIG_IO_13_INPUT_BUF_EN 1 +#define CONFIG_IO_13_PD_DRV_STRG 10 +#define CONFIG_IO_13_PD_SLW_RT 1 +#define CONFIG_IO_13_PU_DRV_STRG 8 +#define CONFIG_IO_13_PU_SLW_RT 1 +#define CONFIG_IO_13_RTRIM 1 +#define CONFIG_IO_13_WK_PU_EN 0 +#define CONFIG_IO_14_INPUT_BUF_EN 1 +#define CONFIG_IO_14_PD_DRV_STRG 10 +#define CONFIG_IO_14_PD_SLW_RT 1 +#define CONFIG_IO_14_PU_DRV_STRG 8 +#define CONFIG_IO_14_PU_SLW_RT 1 +#define CONFIG_IO_14_RTRIM 1 +#define CONFIG_IO_14_WK_PU_EN 0 +#define CONFIG_IO_15_INPUT_BUF_EN 1 +#define CONFIG_IO_15_PD_DRV_STRG 10 +#define CONFIG_IO_15_PD_SLW_RT 1 +#define CONFIG_IO_15_PU_DRV_STRG 8 +#define CONFIG_IO_15_PU_SLW_RT 1 +#define CONFIG_IO_15_RTRIM 1 +#define CONFIG_IO_15_WK_PU_EN 0 +#define CONFIG_IO_16_INPUT_BUF_EN 0 +#define CONFIG_IO_16_PD_DRV_STRG 10 +#define CONFIG_IO_16_PD_SLW_RT 1 +#define CONFIG_IO_16_PU_DRV_STRG 8 +#define CONFIG_IO_16_PU_SLW_RT 1 +#define CONFIG_IO_16_RTRIM 1 +#define CONFIG_IO_16_WK_PU_EN 0 +#define CONFIG_IO_17_INPUT_BUF_EN 1 +#define CONFIG_IO_17_PD_DRV_STRG 10 +#define CONFIG_IO_17_PD_SLW_RT 1 +#define CONFIG_IO_17_PU_DRV_STRG 8 +#define CONFIG_IO_17_PU_SLW_RT 1 +#define CONFIG_IO_17_RTRIM 1 +#define CONFIG_IO_17_WK_PU_EN 0 +#define CONFIG_IO_1_INPUT_BUF_EN 1 +#define CONFIG_IO_1_PD_DRV_STRG 10 +#define CONFIG_IO_1_PD_SLW_RT 0 +#define CONFIG_IO_1_PU_DRV_STRG 8 +#define CONFIG_IO_1_PU_SLW_RT 0 +#define CONFIG_IO_1_RTRIM 1 +#define CONFIG_IO_1_WK_PU_EN 1 +#define CONFIG_IO_2_INPUT_BUF_EN 1 +#define CONFIG_IO_2_PD_DRV_STRG 10 +#define CONFIG_IO_2_PD_SLW_RT 0 +#define CONFIG_IO_2_PU_DRV_STRG 8 +#define CONFIG_IO_2_PU_SLW_RT 0 +#define CONFIG_IO_2_RTRIM 1 +#define CONFIG_IO_2_WK_PU_EN 1 +#define CONFIG_IO_3_INPUT_BUF_EN 1 +#define CONFIG_IO_3_PD_DRV_STRG 10 +#define CONFIG_IO_3_PD_SLW_RT 0 +#define CONFIG_IO_3_PU_DRV_STRG 8 +#define CONFIG_IO_3_PU_SLW_RT 0 +#define CONFIG_IO_3_RTRIM 1 +#define CONFIG_IO_3_WK_PU_EN 1 +#define CONFIG_IO_4_INPUT_BUF_EN 1 +#define CONFIG_IO_4_PD_DRV_STRG 10 +#define CONFIG_IO_4_PD_SLW_RT 1 +#define CONFIG_IO_4_PU_DRV_STRG 8 +#define CONFIG_IO_4_PU_SLW_RT 1 +#define CONFIG_IO_4_RTRIM 1 +#define CONFIG_IO_4_WK_PU_EN 0 +#define CONFIG_IO_5_INPUT_BUF_EN 1 +#define CONFIG_IO_5_PD_DRV_STRG 10 +#define CONFIG_IO_5_PD_SLW_RT 1 +#define CONFIG_IO_5_PU_DRV_STRG 8 +#define CONFIG_IO_5_PU_SLW_RT 1 +#define CONFIG_IO_5_RTRIM 1 +#define CONFIG_IO_5_WK_PU_EN 0 +#define CONFIG_IO_6_INPUT_BUF_EN 0 +#define CONFIG_IO_6_PD_DRV_STRG 10 +#define CONFIG_IO_6_PD_SLW_RT 1 +#define CONFIG_IO_6_PU_DRV_STRG 8 +#define CONFIG_IO_6_PU_SLW_RT 1 +#define CONFIG_IO_6_RTRIM 1 +#define CONFIG_IO_6_WK_PU_EN 0 +#define CONFIG_IO_7_INPUT_BUF_EN 1 +#define CONFIG_IO_7_PD_DRV_STRG 10 +#define CONFIG_IO_7_PD_SLW_RT 1 +#define CONFIG_IO_7_PU_DRV_STRG 8 +#define CONFIG_IO_7_PU_SLW_RT 1 +#define CONFIG_IO_7_RTRIM 1 +#define CONFIG_IO_7_WK_PU_EN 0 +#define CONFIG_IO_8_INPUT_BUF_EN 1 +#define CONFIG_IO_8_PD_DRV_STRG 10 +#define CONFIG_IO_8_PD_SLW_RT 1 +#define CONFIG_IO_8_PU_DRV_STRG 8 +#define CONFIG_IO_8_PU_SLW_RT 1 +#define CONFIG_IO_8_RTRIM 1 +#define CONFIG_IO_8_WK_PU_EN 0 +#define CONFIG_IO_9_INPUT_BUF_EN 1 +#define CONFIG_IO_9_PD_DRV_STRG 10 +#define CONFIG_IO_9_PD_SLW_RT 1 +#define CONFIG_IO_9_PU_DRV_STRG 8 +#define CONFIG_IO_9_PU_SLW_RT 1 +#define CONFIG_IO_9_RTRIM 1 +#define CONFIG_IO_9_WK_PU_EN 0 +#define CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO 1 +#define CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO 1 +#define PINMUX_DEDICATED_IO_10_SEL 15 +#define PINMUX_DEDICATED_IO_11_SEL 15 +#define PINMUX_DEDICATED_IO_12_SEL 15 +#define PINMUX_DEDICATED_IO_13_SEL 15 +#define PINMUX_DEDICATED_IO_14_SEL 15 +#define PINMUX_DEDICATED_IO_15_SEL 15 +#define PINMUX_DEDICATED_IO_16_SEL 13 +#define PINMUX_DEDICATED_IO_17_SEL 13 +#define PINMUX_DEDICATED_IO_4_SEL 8 +#define PINMUX_DEDICATED_IO_5_SEL 8 +#define PINMUX_DEDICATED_IO_6_SEL 8 +#define PINMUX_DEDICATED_IO_7_SEL 8 +#define PINMUX_DEDICATED_IO_8_SEL 8 +#define PINMUX_DEDICATED_IO_9_SEL 8 +#define PINMUX_I2C0_USEFPGA_SEL 0 +#define PINMUX_I2C1_USEFPGA_SEL 0 +#define PINMUX_I2CEMAC0_USEFPGA_SEL 0 +#define PINMUX_I2CEMAC1_USEFPGA_SEL 0 +#define PINMUX_I2CEMAC2_USEFPGA_SEL 0 +#define PINMUX_NAND_USEFPGA_SEL 0 +#define PINMUX_PLL_CLOCK_OUT_USEFPGA_SEL 0 +#define PINMUX_QSPI_USEFPGA_SEL 0 +#define PINMUX_RGMII0_USEFPGA_SEL 0 +#define PINMUX_RGMII1_USEFPGA_SEL 0 +#define PINMUX_RGMII2_USEFPGA_SEL 0 +#define PINMUX_SDMMC_USEFPGA_SEL 0 +#define PINMUX_SHARED_IO_Q1_10_SEL 8 +#define PINMUX_SHARED_IO_Q1_11_SEL 8 +#define PINMUX_SHARED_IO_Q1_12_SEL 8 +#define PINMUX_SHARED_IO_Q1_1_SEL 8 +#define PINMUX_SHARED_IO_Q1_2_SEL 8 +#define PINMUX_SHARED_IO_Q1_3_SEL 8 +#define PINMUX_SHARED_IO_Q1_4_SEL 8 +#define PINMUX_SHARED_IO_Q1_5_SEL 8 +#define PINMUX_SHARED_IO_Q1_6_SEL 8 +#define PINMUX_SHARED_IO_Q1_7_SEL 8 +#define PINMUX_SHARED_IO_Q1_8_SEL 8 +#define PINMUX_SHARED_IO_Q1_9_SEL 8 +#define PINMUX_SHARED_IO_Q2_10_SEL 4 +#define PINMUX_SHARED_IO_Q2_11_SEL 4 +#define PINMUX_SHARED_IO_Q2_12_SEL 4 +#define PINMUX_SHARED_IO_Q2_1_SEL 4 +#define PINMUX_SHARED_IO_Q2_2_SEL 4 +#define PINMUX_SHARED_IO_Q2_3_SEL 4 +#define PINMUX_SHARED_IO_Q2_4_SEL 4 +#define PINMUX_SHARED_IO_Q2_5_SEL 4 +#define PINMUX_SHARED_IO_Q2_6_SEL 4 +#define PINMUX_SHARED_IO_Q2_7_SEL 4 +#define PINMUX_SHARED_IO_Q2_8_SEL 4 +#define PINMUX_SHARED_IO_Q2_9_SEL 4 +#define PINMUX_SHARED_IO_Q3_10_SEL 15 +#define PINMUX_SHARED_IO_Q3_11_SEL 1 +#define PINMUX_SHARED_IO_Q3_12_SEL 1 +#define PINMUX_SHARED_IO_Q3_1_SEL 15 +#define PINMUX_SHARED_IO_Q3_2_SEL 15 +#define PINMUX_SHARED_IO_Q3_3_SEL 15 +#define PINMUX_SHARED_IO_Q3_4_SEL 15 +#define PINMUX_SHARED_IO_Q3_5_SEL 15 +#define PINMUX_SHARED_IO_Q3_6_SEL 15 +#define PINMUX_SHARED_IO_Q3_7_SEL 0 +#define PINMUX_SHARED_IO_Q3_8_SEL 0 +#define PINMUX_SHARED_IO_Q3_9_SEL 15 +#define PINMUX_SHARED_IO_Q4_10_SEL 15 +#define PINMUX_SHARED_IO_Q4_11_SEL 15 +#define PINMUX_SHARED_IO_Q4_12_SEL 15 +#define PINMUX_SHARED_IO_Q4_1_SEL 10 +#define PINMUX_SHARED_IO_Q4_2_SEL 10 +#define PINMUX_SHARED_IO_Q4_3_SEL 10 +#define PINMUX_SHARED_IO_Q4_4_SEL 10 +#define PINMUX_SHARED_IO_Q4_5_SEL 10 +#define PINMUX_SHARED_IO_Q4_6_SEL 10 +#define PINMUX_SHARED_IO_Q4_7_SEL 15 +#define PINMUX_SHARED_IO_Q4_8_SEL 15 +#define PINMUX_SHARED_IO_Q4_9_SEL 15 +#define PINMUX_SPIM0_USEFPGA_SEL 0 +#define PINMUX_SPIM1_USEFPGA_SEL 0 +#define PINMUX_SPIS0_USEFPGA_SEL 0 +#define PINMUX_SPIS1_USEFPGA_SEL 0 +#define PINMUX_UART0_USEFPGA_SEL 0 +#define PINMUX_UART1_USEFPGA_SEL 0 +#define PINMUX_USB0_USEFPGA_SEL 0 +#define PINMUX_USB1_USEFPGA_SEL 0 + +/* Bridge Configuration */ +#define F2H_AXI_SLAVE 0 +#define F2SDRAM0_AXI_SLAVE 0 +#define F2SDRAM1_AXI_SLAVE 0 +#define F2SDRAM2_AXI_SLAVE 0 +#define H2F_AXI_MASTER 1 +#define LWH2F_AXI_MASTER 1 + +/* Voltage Select for Config IO */ +#define CONFIG_IO_BANK_VSEL \ + (((CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \ + (CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3)) + +/* Macro for Config IO bit mapping */ +#define CONFIG_IO_MACRO(NAME) (((NAME ## _RTRIM & 0x7) << 19) | \ + ((NAME ## _INPUT_BUF_EN & 0x3) << 17) | \ + ((NAME ## _WK_PU_EN & 0x1) << 16) | \ + ((NAME ## _PU_SLW_RT & 0x1) << 13) | \ + ((NAME ## _PU_DRV_STRG & 0x1f) << 8) | \ + ((NAME ## _PD_SLW_RT & 0x1) << 5) | \ + (NAME ## _PD_DRV_STRG & 0x1f)) + +#endif /* __SOCFPGA_ARRIA10_CONFIG_H__ */ diff --git a/arch/arm/dts/socfpga_enclustra_mercury_aa1.dtsi b/arch/arm/dts/socfpga_enclustra_mercury_aa1.dtsi new file mode 100644 index 0000000000..c3d468b01e --- /dev/null +++ b/arch/arm/dts/socfpga_enclustra_mercury_aa1.dtsi @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/ { + compatible = "altr,socfpga-arria10", "altr,socfpga"; + + aliases { + serial0 = &uart1; + ethernet0 = &gmac0; + spi0 = &qspi; + i2c0 = &i2c1; + i2c1 = &i2c0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + /* define i2c label to be used in baseboard dtsi */ + soc { + i2c_encl: i2c@ffc02300 { + }; + i2c_encl_fpga: i2c@ffc02200 { + }; + }; + +}; + +&osc1 { + clock-frequency = <33330000>; +}; + +&l4_main_clk { + bootph-all; +}; + +&qspi_clk { + bootph-all; +}; + +&main_sdmmc_clk { + bootph-all; +}; + +&sdmmc_clk { + bootph-all; +}; + +&sdmmc_free_clk { + bootph-all; +}; + +&peri_sdmmc_clk { + bootph-all; +}; + +&uart1 { + bootph-all; + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&i2c_encl { + i2c-sda-hold-time-ns = <300>; + status = "okay"; + + clock-frequency = <100000>; + + atsha204a: atsha204a@64 { + status = "okay"; + compatible = "atmel,atsha204a"; + reg = <0x64>; + }; +}; + +&i2c_encl_fpga { + i2c-sda-hold-time-ns = <300>; + status = "disabled"; +}; + +&mmc { + bootph-all; + status = "okay"; + cap-sd-highspeed; + broken-cd; + bus-width = <4>; +}; + +&eccmgr { + sdmmca-ecc@ff8c2c00 { + compatible = "altr,socfpga-sdmmc-ecc"; + reg = <0xff8c2c00 0x400>; + altr,ecc-parent = <&mmc>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, + <47 IRQ_TYPE_LEVEL_HIGH>, + <16 IRQ_TYPE_LEVEL_HIGH>, + <48 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&qspi { + bootph-all; + status = "okay"; + + flash0: s25fl512s@0 { + bootph-all; + #address-cells = <1>; + #size-cells = <1>; + compatible = "spansion,s25fl512s", "jedec,spi-nor"; + reg = <0>; + + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + spi-max-frequency = <10000000>; + + page-size = <256>; + block-size = <16>; /* 2^16, 64KB */ + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,tshsl-ns = <200>; + cdns,tsd2d-ns = <255>; + cdns,tchsh-ns = <20>; + cdns,tslch-ns = <20>; + }; +}; + +&watchdog1 { + bootph-all; + status = "disabled"; +}; + +&gmac0 { + status = "okay"; + /delete-property/ mac-address; + phy-mode = "rgmii"; + phy-addr = <3>; + phy-handle = <&phy3>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy3: ethernet-phy@3 { + reg = <3>; + + /* Add 2ns RX clock delay (1.2ns + 0.78ns)*/ + rxc-skew-ps = <1680>; + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + rxdv-skew-ps = <420>; + + /* Add 1.38ns TX clock delay (0.96ns + 0.42ns)*/ + txc-skew-ps = <1860>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + txen-skew-ps = <0>; + }; + }; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; + diff --git a/arch/arm/dts/socfpga_enclustra_mercury_aa1_qspi_boot.dtsi b/arch/arm/dts/socfpga_enclustra_mercury_aa1_qspi_boot.dtsi new file mode 100644 index 0000000000..f51dc7c55f --- /dev/null +++ b/arch/arm/dts/socfpga_enclustra_mercury_aa1_qspi_boot.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/ { + fs_loader0: fs-loader { + bootph-all; + compatible = "u-boot,fs-loader"; + sfconfig = <0 0 50000000 3>; + }; +}; + +&fpga_mgr { + bootph-all; + firmware-loader = <&fs_loader0>; + altr,bitstream = "300000"; +}; diff --git a/arch/arm/dts/socfpga_enclustra_mercury_aa1_sdmmc_boot.dtsi b/arch/arm/dts/socfpga_enclustra_mercury_aa1_sdmmc_boot.dtsi new file mode 100644 index 0000000000..052726e318 --- /dev/null +++ b/arch/arm/dts/socfpga_enclustra_mercury_aa1_sdmmc_boot.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/ { + fs_loader0: fs-loader { + bootph-all; + compatible = "u-boot,fs-loader"; + phandlepart = <&mmc 1>; + }; +}; + +&fpga_mgr { + bootph-all; + firmware-loader = <&fs_loader0>; + altr,bitstream = "bitstream.itb"; +}; diff --git a/arch/arm/dts/socfpga_enclustra_mercury_pe1.dtsi b/arch/arm/dts/socfpga_enclustra_mercury_pe1.dtsi new file mode 100644 index 0000000000..e39474f443 --- /dev/null +++ b/arch/arm/dts/socfpga_enclustra_mercury_pe1.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/ { +}; diff --git a/arch/arm/dts/socfpga_enclustra_mercury_pe3.dtsi b/arch/arm/dts/socfpga_enclustra_mercury_pe3.dtsi new file mode 100644 index 0000000000..85d5050bb1 --- /dev/null +++ b/arch/arm/dts/socfpga_enclustra_mercury_pe3.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&i2c_encl_fpga { + status = "okay"; +}; diff --git a/arch/arm/dts/socfpga_enclustra_mercury_st1.dtsi b/arch/arm/dts/socfpga_enclustra_mercury_st1.dtsi new file mode 100644 index 0000000000..85d5050bb1 --- /dev/null +++ b/arch/arm/dts/socfpga_enclustra_mercury_st1.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&i2c_encl_fpga { + status = "okay"; +}; From patchwork Tue Sep 17 06:21:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 1986682 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20230601 header.b=WLi/TvJz; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X7pKz465Fz1y1g for ; Wed, 18 Sep 2024 16:15:35 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 9FBAB88ECB; Wed, 18 Sep 2024 08:14:49 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="WLi/TvJz"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id A4F0B88CDC; Tue, 17 Sep 2024 08:22:06 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,SPF_HELO_NONE, SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mail-ed1-x535.google.com (mail-ed1-x535.google.com [IPv6:2a00:1450:4864:20::535]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 4264388D1A for ; Tue, 17 Sep 2024 08:22:02 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=l.rubusch@gmail.com Received: by mail-ed1-x535.google.com with SMTP id 4fb4d7f45d1cf-5c2509f4143so703033a12.0 for ; Mon, 16 Sep 2024 23:22:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726554122; x=1727158922; darn=lists.denx.de; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KxM3xgAP1lFnwP1DOnnIlkk4em0DyyORCrxWPUMz3yg=; b=WLi/TvJzGmT5MMC2qOQhIiD9g39hpAET5asvv/cLL6o19Kgj/Z6nJJVP3Obyd+1HKo y12DKlC/rTXKmV4pZIyIlwYzk2kiJzXv+5glHtNeeKfWTZdDm4jk0V3CQ578OtJXRnQb 0OrbemT1hd7ZENTDOcDSPseY4JCi/hI0/aKK+1E0rZeNjzJo7oiQBIh2hA+pKyVbEPtD kij2dOTIXog01cl6dVfagr6s8jj/09pPR+QYofQbsWvgMYubDlJP6M0jyzqEvaK9EgB1 ToaSUfQv41nmTkauaOWWW+q/uaor+Bl0XxDIGubMgbKAcObe8CCWh67QFM8P3mpYwISd hGEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726554122; x=1727158922; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KxM3xgAP1lFnwP1DOnnIlkk4em0DyyORCrxWPUMz3yg=; b=VzRU8Xghq67qvWSCV/Tyn7Kt60VsZZXHbVxj4Y6t5fKWclonH6WH2BKGb1nygTfR4D cbT8plBpiC+Lo8+kvlxGjj7A1I8N8yYSUW527BVa47hK4t7YTazDZK/x8LI7gJdhaDZ3 Q8tNh55wQ66/zEHnl+XwxuuKi8uM4/tvwDQOfb4LajY3hRmnVg243i5zDB6OnxFtr50N XqDlYf4uIWemqKSnXlmQiIdmT39+UR67G2LLPgV/f8p8HcSLB7XEeDhzm4k6fSlNoaHI 8ZiSxVmXXiNS8Q15dB7rLtWMArV/PP2AVt6RUKZrgxeMidT+7gN4NdCQGq/frioXLfJE uE7A== X-Gm-Message-State: AOJu0Yy8R6AkGEs8LSzV67FjM3zM5Az2GqE0L5j+SRJTRZ+LpMGVGZB3 TjBEav21fsC/4O1xzsqmBlIUODDwjY1ctSD7fdzl+lloh5NsfxdriQRk1Rdq X-Google-Smtp-Source: AGHT+IGkZ6pjvemNYlWjFSkkNy7C3QL/PGhjUk1zNfNi8U1ZRpMKBNfKQtWBVKtMhfxSjGLs6rBlxA== X-Received: by 2002:a17:907:1c2a:b0:a8a:811e:3fd5 with SMTP id a640c23a62f3a-a9029448c6amr856179766b.4.1726554121585; Mon, 16 Sep 2024 23:22:01 -0700 (PDT) Received: from fc8b2ad344cc.pool3007.local ([83.68.141.146]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9061328e61sm403556366b.196.2024.09.16.23.22.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Sep 2024 23:22:01 -0700 (PDT) From: Lothar Rubusch To: u-boot@lists.denx.de, trini@konsulko.com, marex@denx.de, simon.k.r.goldschmidt@gmail.com, tien.fong.chee@intel.com Cc: l.rubusch@gmail.com Subject: [PATCH v2 3/7] ARM: socfpga: add Enclustra AA1 SoM support Date: Tue, 17 Sep 2024 06:21:53 +0000 Message-Id: <20240917062157.3181-4-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240917062157.3181-1-l.rubusch@gmail.com> References: <20240917062157.3181-1-l.rubusch@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 18 Sep 2024 08:14:47 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Introduce initial support for the Enclustra SoMs: - Mercury AA1 Cover general board files for SD/MMC and QSPI boot modes. Integrate the boards to kconfig. All build variants will depend on Quartus handoff files, thus they depend on the particular Quartus design. The approach is covered in the according documentation part. Additionally add configuration for SD/MMC boot and QSPI bootmodes. Register additional targets in kconfig. Signed-off-by: Andreas Buerkler Signed-off-by: Lothar Rubusch --- arch/arm/mach-socfpga/Kconfig | 9 + board/enclustra/common/Kconfig | 1 + board/enclustra/common/Makefile | 4 + board/enclustra/mercury_aa1/Kconfig | 15 ++ board/enclustra/mercury_aa1/MAINTAINERS | 11 ++ board/enclustra/mercury_aa1/Makefile | 8 + .../mercury_aa1/aa1_set_storage_cmd.c | 177 ++++++++++++++++++ board/enclustra/mercury_aa1/bitstream.its | 32 ++++ .../socfpga_enclustra_mercury_aa1_defconfig | 78 ++++++++ include/configs/socfpga_mercury_aa1.h | 33 ++++ 10 files changed, 368 insertions(+) create mode 100644 board/enclustra/common/Kconfig create mode 100644 board/enclustra/common/Makefile create mode 100644 board/enclustra/mercury_aa1/Kconfig create mode 100644 board/enclustra/mercury_aa1/MAINTAINERS create mode 100644 board/enclustra/mercury_aa1/Makefile create mode 100644 board/enclustra/mercury_aa1/aa1_set_storage_cmd.c create mode 100644 board/enclustra/mercury_aa1/bitstream.its create mode 100644 configs/socfpga_enclustra_mercury_aa1_defconfig create mode 100644 include/configs/socfpga_mercury_aa1.h diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 6b6a162f56..d42e7817be 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -221,6 +221,10 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT bool "Terasic SoCkit (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 +config TARGET_SOCFPGA_ENCLUSTRA_MERCURY_AA1 + bool "Enclustra Mercury+ AA1" + select TARGET_SOCFPGA_ARRIA10 + endchoice config SYS_BOARD @@ -244,6 +248,7 @@ config SYS_BOARD default "sr1500" if TARGET_SOCFPGA_SR1500 default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA + default "mercury_aa1" if TARGET_SOCFPGA_ENCLUSTRA_MERCURY_AA1 config SYS_VENDOR default "intel" if TARGET_SOCFPGA_AGILEX5_SOCDK @@ -264,6 +269,7 @@ config SYS_VENDOR default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT + default "enclustra" if TARGET_SOCFPGA_ENCLUSTRA_MERCURY_AA1 config SYS_SOC default "socfpga" @@ -289,5 +295,8 @@ config SYS_CONFIG_NAME default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA + default "socfpga_mercury_aa1" if TARGET_SOCFPGA_ENCLUSTRA_MERCURY_AA1 + +source "board/enclustra/common/Kconfig" endif diff --git a/board/enclustra/common/Kconfig b/board/enclustra/common/Kconfig new file mode 100644 index 0000000000..51169bada3 --- /dev/null +++ b/board/enclustra/common/Kconfig @@ -0,0 +1 @@ +source "board/enclustra/mercury_aa1/Kconfig" diff --git a/board/enclustra/common/Makefile b/board/enclustra/common/Makefile new file mode 100644 index 0000000000..16c8531d74 --- /dev/null +++ b/board/enclustra/common/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (c) 2024 Enclustra GmbH + +# Common for several Enclustra modules diff --git a/board/enclustra/mercury_aa1/Kconfig b/board/enclustra/mercury_aa1/Kconfig new file mode 100644 index 0000000000..40c7cb2687 --- /dev/null +++ b/board/enclustra/mercury_aa1/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SOCFPGA_ENCLUSTRA_MERCURY_AA1 + +config SYS_CPU + default "armv7" + +config SYS_BOARD + default "mercury_aa1" + +config SYS_VENDOR + default "enclustra" + +config SYS_CONFIG_NAME + default "socfpga_mercury_aa1" + +endif diff --git a/board/enclustra/mercury_aa1/MAINTAINERS b/board/enclustra/mercury_aa1/MAINTAINERS new file mode 100644 index 0000000000..862cb1ae31 --- /dev/null +++ b/board/enclustra/mercury_aa1/MAINTAINERS @@ -0,0 +1,11 @@ +Enclustra Mercury+ AA1 +M: Lothar Rubusch +S: Maintained +F: board/enclustra/mercury_aa1/ +F: board/enclustra/common/ +F: include/configs/socfpga_mercury_aa1.h +F: configs/socfpga_enclustra_mercury_aa1_defconfig +F: arch/arm/dts/socfpga_enclustra_mercury_aa1.dtsi +F: arch/arm/dts/socfpga_enclustra_mercury_aa1_emmc_boot.dtsi +F: arch/arm/dts/socfpga_enclustra_mercury_aa1_qspi_boot.dtsi +F: doc/board/enclustra/mercury-aa1.rst diff --git a/board/enclustra/mercury_aa1/Makefile b/board/enclustra/mercury_aa1/Makefile new file mode 100644 index 0000000000..53c84d8156 --- /dev/null +++ b/board/enclustra/mercury_aa1/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (c) 2024 Enclustra GmbH + +ifeq ($(CONFIG_SPL_BUILD),) + +obj-y += aa1_set_storage_cmd.o + +endif diff --git a/board/enclustra/mercury_aa1/aa1_set_storage_cmd.c b/board/enclustra/mercury_aa1/aa1_set_storage_cmd.c new file mode 100644 index 0000000000..650457feba --- /dev/null +++ b/board/enclustra/mercury_aa1/aa1_set_storage_cmd.c @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Enclustra GmbH + * + */ + +#include +#include +#include +#include +#include +#include + +/* Pin muxing */ +#define ALTERA_NONE 0 +#define ALTERA_MMC 1 +#define ALTERA_QSPI 2 +#define ALTERA_EMMC 3 +#define MMC_CLK_DIV 0x9 +#define QSPI_CLK_DIV 0x384 +#define ALTERA_PINMUX_OFFS 0xffd07200 +#define ALTERA_CLKMGR_MAINPLL_CNTR6CLK_BASE 0xFFD04078 + +static int altera_current_storage = ALTERA_NONE; + +static void set_mux_mmc(void) +{ + u32 pinmux_arr[] = {0x0c, 0x8, // IO4 connected to SDMMC + 0x10, 0x8, // IO5 + 0x14, 0x8, // IO6 + 0x18, 0x8, // IO7 + 0x1c, 0x8, // IO8 + 0x20, 0x8, // IO9 + 0x24, 0xf, // IO10 connected to GPIO + 0x28, 0xf, // IO11 + 0x2c, 0xf, // IO12 + 0x30, 0xf, // IO13 + 0x34, 0xf, // IO14 + 0x38, 0xf}; // IO15 + u32 len, i, offset, value; + + len = sizeof(pinmux_arr) / sizeof(u32); + for (i = 0; i < len; i += 2) { + offset = pinmux_arr[i]; + value = pinmux_arr[i + 1]; + writel(value, ALTERA_PINMUX_OFFS + offset); + } +} + +static void set_mux_emmc(void) +{ + u32 pinmux_arr[] = {0x0c, 0x8, // IO4 + 0x10, 0x8, // IO5 + 0x14, 0x8, // IO6 + 0x18, 0x8, // IO7 + 0x1c, 0x8, // IO8 + 0x20, 0x8, // IO9 + 0x24, 0xf, // IO10 + 0x28, 0xf, // IO11 + 0x2c, 0x8, // IO12 + 0x30, 0x8, // IO13 + 0x34, 0x8, // IO14 + 0x38, 0x8}; // IO15 + u32 len, i, offset, value; + + len = sizeof(pinmux_arr) / sizeof(u32); + for (i = 0; i < len; i += 2) { + offset = pinmux_arr[i]; + value = pinmux_arr[i + 1]; + writel(value, ALTERA_PINMUX_OFFS + offset); + } +} + +static void set_mux_qspi(void) +{ + u32 pinmux_arr[] = {0x0c, 0x4, // IO4 connected to QSPI + 0x10, 0x4, // IO5 + 0x14, 0x4, // IO6 + 0x18, 0x4, // IO7 + 0x1c, 0x4, // IO8 + 0x20, 0x4, // IO9 + 0x24, 0xf, // IO10 + 0x28, 0xf, // IO11 + 0x2c, 0xf, // IO12 + 0x30, 0xf, // IO13 + 0x34, 0xf, // IO14 + 0x38, 0xf}; // IO15 + u32 len, i, offset, value; + + len = sizeof(pinmux_arr) / sizeof(u32); + for (i = 0; i < len; i += 2) { + offset = pinmux_arr[i]; + value = pinmux_arr[i + 1]; + writel(value, ALTERA_PINMUX_OFFS + offset); + } +} + +static void altera_set_storage(int store) +{ + unsigned int gpio_flash_sel; + unsigned int gpio_flash_oe; + + if (store == altera_current_storage) + return; + + if (gpio_lookup_name("portb5", NULL, NULL, &gpio_flash_oe)) { + printf("ERROR: GPIO not found\n"); + return; + } + + if (gpio_request(gpio_flash_oe, "flash_oe")) { + printf("ERROR: GPIO request failed\n"); + return; + } + + if (gpio_lookup_name("portc6", NULL, NULL, &gpio_flash_sel)) { + printf("ERROR: GPIO not found\n"); + return; + } + + if (gpio_request(gpio_flash_sel, "flash_sel")) { + printf("ERROR: GPIO request failed\n"); + return; + } + + switch (store) { + case ALTERA_MMC: + set_mux_mmc(); + gpio_direction_output(gpio_flash_sel, 0); + gpio_direction_output(gpio_flash_oe, 0); + altera_current_storage = ALTERA_MMC; + writel(MMC_CLK_DIV, ALTERA_CLKMGR_MAINPLL_CNTR6CLK_BASE); + break; + case ALTERA_EMMC: + set_mux_emmc(); + gpio_direction_output(gpio_flash_sel, 1); + gpio_direction_output(gpio_flash_oe, 1); + altera_current_storage = ALTERA_EMMC; + writel(MMC_CLK_DIV, ALTERA_CLKMGR_MAINPLL_CNTR6CLK_BASE); + break; + case ALTERA_QSPI: + set_mux_qspi(); + gpio_direction_output(gpio_flash_sel, 1); + gpio_direction_output(gpio_flash_oe, 0); + altera_current_storage = ALTERA_QSPI; + writel(QSPI_CLK_DIV, ALTERA_CLKMGR_MAINPLL_CNTR6CLK_BASE); + break; + default: + altera_current_storage = ALTERA_NONE; + break; + } + + gpio_free(gpio_flash_sel); + gpio_free(gpio_flash_oe); +} + +static int altera_set_storage_cmd(struct cmd_tbl *cmdtp, int flag, + int argc, char * const argv[]) +{ + if (argc != 2) + return CMD_RET_USAGE; + + if (!strcmp(argv[1], "MMC")) + altera_set_storage(ALTERA_MMC); + else if (!strcmp(argv[1], "QSPI")) + altera_set_storage(ALTERA_QSPI); + else if (!strcmp(argv[1], "EMMC")) + altera_set_storage(ALTERA_EMMC); + else + return CMD_RET_USAGE; + + return CMD_RET_SUCCESS; +} + +U_BOOT_CMD(altera_set_storage, 2, 0, altera_set_storage_cmd, + "Set non volatile memory access", + " - Set access for the selected memory device"); diff --git a/board/enclustra/mercury_aa1/bitstream.its b/board/enclustra/mercury_aa1/bitstream.its new file mode 100644 index 0000000000..d16e4598de --- /dev/null +++ b/board/enclustra/mercury_aa1/bitstream.its @@ -0,0 +1,32 @@ +/dts-v1/; + +/ { + description = "FIT image with FPGA bistream"; + #address-cells = <1>; + + images { + fpga-periph-1 { + description = "FPGA peripheral bitstream"; + data = /incbin/("bitstream.periph.rbf"); + type = "fpga"; + arch = "arm"; + compression = "none"; + }; + + fpga-core-1 { + description = "FPGA core bitstream"; + data = /incbin/("bitstream.core.rbf"); + type = "fpga"; + arch = "arm"; + compression = "none"; + }; + }; + + configurations { + default = "config-1"; + config-1 { + description = "Boot with FPGA early IO release config"; + fpga = "fpga-periph-1", "fpga-core-1"; + }; + }; +}; diff --git a/configs/socfpga_enclustra_mercury_aa1_defconfig b/configs/socfpga_enclustra_mercury_aa1_defconfig new file mode 100644 index 0000000000..b475bd916d --- /dev/null +++ b/configs/socfpga_enclustra_mercury_aa1_defconfig @@ -0,0 +1,78 @@ +CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_MALLOC_LEN=0x4000000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xffe2b000 +CONFIG_SF_DEFAULT_SPEED=10000000 +CONFIG_ENV_SIZE=0x80000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="enclustra-aa1" +CONFIG_SPL_TEXT_BASE=0xFFE00000 +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK=0xffe2b000 +CONFIG_TARGET_SOCFPGA_ENCLUSTRA_MERCURY_AA1=y +CONFIG_IDENT_STRING="socfpga_arria10" +CONFIG_SPL_FS_FAT=y +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200" +CONFIG_DEFAULT_FDT_FILE="system.dtb" +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_CLOCKS=y +CONFIG_SPL_PAD_TO=0x40000 +CONFIG_SPL_NO_BSS_LIMIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xffe2b000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x15000 +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" +CONFIG_SPL_FPGA=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 +CONFIG_CMD_ASKENV=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_FPGA_LOADMK=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_FAT=y +CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_VERSION_VARIABLE=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_DWAPB_GPIO=y +CONFIG_SYS_I2C_DW=y +CONFIG_MISC=y +CONFIG_FS_LOADER=y +CONFIG_SPL_FS_LOADER=y +CONFIG_MMC_DW=y +CONFIG_SPI_FLASH_SPANSION=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SPI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_DESIGNWARE_APB_TIMER=y +CONFIG_USB=y +CONFIG_USB_DWC2=y diff --git a/include/configs/socfpga_mercury_aa1.h b/include/configs/socfpga_mercury_aa1.h new file mode 100644 index 0000000000..a5b63336e8 --- /dev/null +++ b/include/configs/socfpga_mercury_aa1.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2024 Enclustra GmbH + * + */ + +#ifndef __CONFIG_SOCFGPA_MERCURY_AA1_H__ +#define __CONFIG_SOCFGPA_MERCURY_AA1_H__ + +#include + +/* + * U-Boot general configurations + */ + +/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x80000000 + +/* + * Serial / UART configurations + */ +#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} + +/* + * L4 OSC1 Timer 0 + */ +/* reload value when timer count to zero */ +#define TIMER_LOAD_VAL 0xFFFFFFFF + +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIG_SOCFGPA_MERCURY_AA1_H__ */ From patchwork Tue Sep 17 06:21:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 1986681 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20230601 header.b=FPoUc7XW; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X7pKn4szXz1y1g for ; Wed, 18 Sep 2024 16:15:25 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 474BC88EA3; Wed, 18 Sep 2024 08:14:49 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="FPoUc7XW"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 6611888CDC; Tue, 17 Sep 2024 08:22:06 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-ed1-x535.google.com (mail-ed1-x535.google.com [IPv6:2a00:1450:4864:20::535]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 3F80088D3D for ; Tue, 17 Sep 2024 08:22:03 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=l.rubusch@gmail.com Received: by mail-ed1-x535.google.com with SMTP id 4fb4d7f45d1cf-5c4093d074aso793116a12.2 for ; Mon, 16 Sep 2024 23:22:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726554123; x=1727158923; darn=lists.denx.de; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DRCd/aYb0v7e7yYMyBvEnSLUhQuQPdo2E3oA4XELAVk=; b=FPoUc7XWYT06s0O5TFTISURLRchRFB1B5UH1xxudBZ9T/ynjNvSyZWtKHITYjxggUz ZDshxI7+MtIKuCYfYw9MpIPBb5jOjFvNBzVWFdAA/Eyt09qgeQcOKOQhmGYmBEazpjwQ Iy8r2JaSqNe45lWLOvHVsvW8nGGPcnDN0Z4dWEmt/8wpL8f/QxskWMpHtDH2MSKeXuOG WrbMaXFfIRBPWGeiEzKkHxhkpQETDJ8636NEqmKG08yBtlWOSfJ83zqjObC8H1IQBk/9 1Yw9Iy8Ssluok7lc7XYHnCGcUIf2uOale2QOSC1ACmpNa/RZ4UNZSzNGx6h9j+oNAS7u mMIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726554123; x=1727158923; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DRCd/aYb0v7e7yYMyBvEnSLUhQuQPdo2E3oA4XELAVk=; b=Dqv2pSHWzk2SV+ehynW5UENK5uBdZ7n5xhjewIhd2nkHlg33rzfONWDZ0/JnDPzAA9 sG/rG5qfxWFXriZydt955Un66uuYeagUtKtnF3mk5zADJUB3+yrfXq006WnTZ/EiukRk 3/bvxx5IxYCEZrcwKteITpK+Y4oqAHbVXifif/6abmbxqBla/Z0iDg6LTXoTl4vZU0z2 wpRdhP7Op2dMUKQbCAfX+gqyanxtL9Tw4hJkHFEN0hAhld2AlyVXDhoPsZhPAOWhGpM6 1x8ZD5KyQjMKQqs0BUKqwFChYj5TVwyyJ+8aFJORkMPJhDfmNJXNNkoSKVlkOSGjMxJ4 OclA== X-Gm-Message-State: AOJu0Yx5qzoG4MNVVkwM2KruLvD/7S5dbM7xKQUhob+fn30xmdpBN0L+ FSSyYuLRUjH7zb+VOllxog3ednHpp7mAdSuYogu8npbsAzZFU4aoO0j9+9xO X-Google-Smtp-Source: AGHT+IFmTwA8VJifm2jLT5Hs9+IWAAkOTeETga4pP18x0ISxSXvWxIx7l7iDOMx9IiWchCDQgry39Q== X-Received: by 2002:a17:906:fd83:b0:a8d:2624:1a83 with SMTP id a640c23a62f3a-a90296d7d09mr681766766b.14.1726554122518; Mon, 16 Sep 2024 23:22:02 -0700 (PDT) Received: from fc8b2ad344cc.pool3007.local ([83.68.141.146]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9061328e61sm403556366b.196.2024.09.16.23.22.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Sep 2024 23:22:02 -0700 (PDT) From: Lothar Rubusch To: u-boot@lists.denx.de, trini@konsulko.com, marex@denx.de, simon.k.r.goldschmidt@gmail.com, tien.fong.chee@intel.com Cc: l.rubusch@gmail.com Subject: [PATCH v2 4/7] ARM: socfpga: add Enclustra AA1 extra env settings Date: Tue, 17 Sep 2024 06:21:54 +0000 Message-Id: <20240917062157.3181-5-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240917062157.3181-1-l.rubusch@gmail.com> References: <20240917062157.3181-1-l.rubusch@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 18 Sep 2024 08:14:47 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add command files for boot scripts and initial boot environment. Signed-off-by: Andreas Buerkler Signed-off-by: Lothar Rubusch --- include/configs/socfpga_mercury_aa1.h | 35 +++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/include/configs/socfpga_mercury_aa1.h b/include/configs/socfpga_mercury_aa1.h index a5b63336e8..4b047e11a7 100644 --- a/include/configs/socfpga_mercury_aa1.h +++ b/include/configs/socfpga_mercury_aa1.h @@ -21,6 +21,41 @@ */ #define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} +/* U-Boot environment */ +#define CFG_EXTRA_ENV_SETTINGS \ + "bitstream_size=0xD00000\0" \ + "bootargs=earlycon console=ttyS0,115200 rw rootwait root=/dev/mmcblk0p3\0" \ + "bootargs_qspi=earlycon console=ttyS0,115200 rw root=/dev/ram0\0" \ + "bootm_size=0x0a000000\0" \ + "env_size=0x80000\0" \ + "fdt_addr_r=0x10000000\0" \ + "fdtfile=system.dtb\0" \ + "fdtload=load ${devtype} ${devnum}:${distro_bootpart} ${fdt_addr_r} ${bootdir}/${fdtfile}; load ${devtype} ${devnum}:${distro_bootpart} ${fdto_addr_r} ${bootdir}/${fdtofile}; fdt addr $fdt_addr_r; fdt resize 8192; fdt apply $fdto_addr_r\0" \ + "fdtload_qspi=sf probe; sf read ${fdt_addr_r} ${qspi_offset_addr_devicetree} ${fdt_size}; sf read ${fdto_addr_r} ${qspi_offset_addr_dtoverlay} ${fdto_size}; fdt addr ${fdt_addr_r}; fdt resize 8192; fdt apply ${fdto_addr_r}\0" \ + "fdto_addr_r=0x100c0000\0" \ + "fdtofile=socfpga_enclustra_mercury_XXX_overlay.dtbo\0" \ + "fdto_size=0x40000\0" \ + "fdt_size=0x40000\0" \ + "kernel_addr_r=0x11000000\0" \ + "kernel_size=0x1000000\0" \ + "qspiboot=source ${scriptaddr}\0" \ + "qspiload=setenv bootargs ${bootargs_qspi}; sf probe; sf read ${scriptaddr} ${qspi_offset_addr_boot_script} ${scriptsize}\0" \ + "qspi_offset_addr_bitstream=0x300000\0" \ + "qspi_offset_addr_boot_script=0x200000\0" \ + "qspi_offset_addr_devicetree=0x280000\0" \ + "qspi_offset_addr_dtoverlay=0x2c0000\0" \ + "qspi_offset_addr_kernel=0x1000000\0" \ + "qspi_offset_addr_rootfs=0x2000000\0" \ + "qspi_offset_addr_spl=0x0\0" \ + "qspi_offset_addr_uboot=0x100000\0" \ + "qspi_offset_addr_uboot_env=0x180000\0" \ + "rootfs_addr_r=0x12000000\0" \ + "rootfs_size=0x2000000\0" \ + "scriptaddr=0x10800000\0" \ + "scriptsize=0x80000\0" \ + "spl_size=0x100000\0" \ + "uboot_size=0x80000\0" + /* * L4 OSC1 Timer 0 */ From patchwork Tue Sep 17 06:21:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 1986683 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20230601 header.b=aDbwdQT7; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X7pL92M5fz1y1g for ; Wed, 18 Sep 2024 16:15:45 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id F333688EDD; Wed, 18 Sep 2024 08:14:49 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="aDbwdQT7"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 2423688CDC; Tue, 17 Sep 2024 08:22:08 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,SPF_HELO_NONE, SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mail-ej1-x636.google.com (mail-ej1-x636.google.com [IPv6:2a00:1450:4864:20::636]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 75C4688DB4 for ; Tue, 17 Sep 2024 08:22:04 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=l.rubusch@gmail.com Received: by mail-ej1-x636.google.com with SMTP id a640c23a62f3a-a8d302b6b30so82640366b.0 for ; Mon, 16 Sep 2024 23:22:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726554124; x=1727158924; darn=lists.denx.de; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DSVF56jI0SAxeTr7ecNh2ccSZTLatNX4L70TQd7wy8U=; b=aDbwdQT74H6NOyaTZukkNTE4IY0PpSarRtrch554+yUT3vQHqAAcIqE9LiO9tOOeMw EXCBZzvTfgKX8VAzCxrlJ5oCFhPEFkUZOPTibvGIKIC6jtwJtSWc9x0yfa/p50kE3gJ4 +bNVQ2I1bqHARwPq8dUuvjsA0Y/2Pnbu3806LNhETnJ1z2/AXc5KU5hlvI+TI0zwfuiX HtwYiPYYx2lEkfWoWETZPgNW1Mtge6cSwruEEjxh4WPEFDXn52Z0mYm7VEEbacOJFEND a/OpFesIf3/Y8MwzeGRvWqQZRDD/jlgJt2+6QHnzHSpbCbIBHVbD8+e+bN5BySSzl6OK Ai+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726554124; x=1727158924; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DSVF56jI0SAxeTr7ecNh2ccSZTLatNX4L70TQd7wy8U=; b=m1Rojly+FUAwP2NIy4yIl+yvZyGBZediZNUMrCiltX+7TNMfdMQhFsQkFOMYVQOdxf cOIMVGBTtxlGeXnqxULxaO8+qkQcJAhmp47ZtWGkSUSwlWxIPCbSt8Lv6JBmBXo61yrk DHDUnuvw87fK6+mHmhe2t+u72cKoU8IE+z0Yi17isRV68yXRrdbXx+/QMu4ygF8UhmtY yUYtp/3NEcSMYdMOuCvECyU6FXW5vEx1Jzq0BJ4hFGqYQJwoDxEm1MUUfsTLP9zXLtul DaIIbVSH7T83c2MvP1RPz6V37CHcc5iPeErcGSunY0cLFI/hAcz1pXQGo1hX0dr01O6d 7qZQ== X-Gm-Message-State: AOJu0YywZPAcVG2p1dCqW/xh9TecsUsV+cymbyPaTwFesvSuYzWZBZTj GisALKoAqZnu3louG+QZzhrwGyIyOQmb10T2M2ee4vChowt1V0s8UV89lf4i X-Google-Smtp-Source: AGHT+IFd8wC9fv0XAsM0VqDzJEXQggLUnLZkcSkrf3K1iEiJ6v1LUnay7odlOHQCjXX/26nktrCmKQ== X-Received: by 2002:a17:907:9724:b0:a7a:b895:6571 with SMTP id a640c23a62f3a-a9029612b9dmr755627566b.9.1726554123400; Mon, 16 Sep 2024 23:22:03 -0700 (PDT) Received: from fc8b2ad344cc.pool3007.local ([83.68.141.146]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9061328e61sm403556366b.196.2024.09.16.23.22.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Sep 2024 23:22:03 -0700 (PDT) From: Lothar Rubusch To: u-boot@lists.denx.de, trini@konsulko.com, marex@denx.de, simon.k.r.goldschmidt@gmail.com, tien.fong.chee@intel.com Cc: l.rubusch@gmail.com Subject: [PATCH v2 5/7] ARM: socfpga: add Enclustra AA1 demo env files Date: Tue, 17 Sep 2024 06:21:55 +0000 Message-Id: <20240917062157.3181-6-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240917062157.3181-1-l.rubusch@gmail.com> References: <20240917062157.3181-1-l.rubusch@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 18 Sep 2024 08:14:47 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Provide additional uboot.env text environment files meant as a generic demo. The default environment uses a uboot.env. The default environment works somehow. This environment provides better support but only shows one possible approach used in the Enclustra reference design setups. Signed-off-by: Lothar Rubusch --- board/enclustra/mercury_aa1/mercury_aa1.env | 65 +++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 board/enclustra/mercury_aa1/mercury_aa1.env diff --git a/board/enclustra/mercury_aa1/mercury_aa1.env b/board/enclustra/mercury_aa1/mercury_aa1.env new file mode 100644 index 0000000000..07b4a95a75 --- /dev/null +++ b/board/enclustra/mercury_aa1/mercury_aa1.env @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Enclustra GmbH + * + * + * This is an example configuration file for uboot.env generation. + * + * Given ENV_FAT_FILE defaults to "uboot.env" and ENV_SIZE defaults to 0x80000 + * (see configuration options). Then adjust the configuration to your needs and + * build the a binary .env file as follows + * $ ./tools/mkenvimage -s 0x80000 -o uboot.env ./board/enclustra/mercury_aa1/mercury_aa1.env + * + * NB: Without providing this binary uboot.env the board is supposed to come up + * with the generic environment based on the architecture. This can be helpful + * when upgrading and/or recuding environments. + */ +bitstream_size=0xD00000 +bootargs=earlycon console=ttyS0,115200 rw rootwait root=/dev/mmcblk0p3 +bootargs_qspi=earlycon console=ttyS0,115200 rw root=/dev/ram0 +bootm_size=0x0a000000 +devnum=0 +devtype=mmc +distro_bootpart=1 +env_size=0x80000 +fdt_addr_r=0x10000000 +fdtfile=system.dtb +fdtload= + load ${devtype} ${devnum}:${distro_bootpart} ${fdt_addr_r} ${bootdir}/${fdtfile}; + load ${devtype} ${devnum}:${distro_bootpart} ${fdto_addr_r} ${bootdir}/${fdtofile}; + fdt addr $fdt_addr_r; + fdt resize 8192; + fdt apply $fdto_addr_r +fdtload_qspi= + sf probe; + sf read ${fdt_addr_r} ${qspi_offset_addr_devicetree} ${fdt_size}; + sf read ${fdto_addr_r} ${qspi_offset_addr_dtoverlay} ${fdto_size}; + fdt addr ${fdt_addr_r}; + fdt resize 8192; + fdt apply ${fdto_addr_r} +fdto_addr_r=0x100c0000 +fdtofile=socfpga_enclustra_mercury_sdmmc_overlay.dtbo +fdto_size=0x40000 +fdt_size=0x40000 +kernel_addr_r=0x11000000 +kernel_size=0x1000000 +qspiboot=source ${scriptaddr} +qspiload= + setenv bootargs ${bootargs_qspi}; + sf probe; + sf read ${scriptaddr} ${qspi_offset_addr_boot_script} ${scriptsize} +qspi_offset_addr_bitstream=0x300000 +qspi_offset_addr_boot_script=0x200000 +qspi_offset_addr_devicetree=0x280000 +qspi_offset_addr_dtoverlay=0x2c0000 +qspi_offset_addr_kernel=0x1000000 +qspi_offset_addr_rootfs=0x2000000 +qspi_offset_addr_spl=0x0 +qspi_offset_addr_uboot=0x100000 +qspi_offset_addr_uboot_env=0x180000 +rootfs_addr_r=0x12000000 +rootfs_size=0x2000000 +scriptaddr=0x10800000 +scriptsize=0x80000 +spl_size=0x100000 +uboot_size=0x80000 From patchwork Tue Sep 17 06:21:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 1986684 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20230601 header.b=fhEhhMvw; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X7pLM1jYJz1y1g for ; Wed, 18 Sep 2024 16:15:55 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 5585288EEA; Wed, 18 Sep 2024 08:14:50 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="fhEhhMvw"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 4A11E88CDC; Tue, 17 Sep 2024 08:22:08 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [IPv6:2a00:1450:4864:20::62b]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 44D4388D51 for ; Tue, 17 Sep 2024 08:22:05 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=l.rubusch@gmail.com Received: by mail-ej1-x62b.google.com with SMTP id a640c23a62f3a-a8a765f980dso95578466b.1 for ; Mon, 16 Sep 2024 23:22:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726554125; x=1727158925; darn=lists.denx.de; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TD9JRY7G1DS8yikvGcH42adJEvkLry5qRRx6nFwl78M=; b=fhEhhMvwYiqrPdSUlNWETjBDLp8U8YX0KjV1zGdJa4C6WA8hCjxziaQSJPMQ24oGUR MF1ozXt4nh0VrQ5e7kU9xmxH2L/ycjXy29r4ISb+NcylLP8OaMKPi/tH8kpirhKytJud RaI/lGXBU4ihZGYELCr9ZxXWwAtI4niDLsu3q3JkVi7cQGPJMaDLWpki5Aw5HScAdKnm LkenKmkkRKdMl47+wueYC6FQVbkbRUV/HKjcGg9SQIyuF1LasR/gXFk99VkKuZhEmq+P Ue6ip1AB7FJ+sNA4J2HiwEDPejY4ZKbNdK+0sgbue5bw1fxlyVB5fLGE1kGotsVdQucZ U39g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726554125; x=1727158925; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TD9JRY7G1DS8yikvGcH42adJEvkLry5qRRx6nFwl78M=; b=J1h+wYrJ/4w0cEZ3R/acODQQmDhc8xzppqHAZuLGqRNHM4EcNObINPQtZIS3QTk1+T kJWFNDrZHfDW0o99ZeP+zGry87YOvvoy7DyFZngNUJgnKb0Z7fwF9Lq84JW8ezW0n8hg 9z3KsBejeylq2smqCalYGTVA2WP/AdOvmnePKQjMb6idhb2TlJ6rGGrUjZeYKdsY5yXh 8YfCkAAFNX/tTZn4KvrOjSbLRXxYZg+7MDqWDVwwS9+R+IAAH87O+YfswHPcSN5Ojlvi EYjVgNTpueVXOjEGW1r3biZlPMa6G1HwCpTOXBDzXsBpIKshPZT302BcglItlLN3+GMJ ScuQ== X-Gm-Message-State: AOJu0Yzk1bg2H+I4nyFfhSMS5juRNOB6/Ia6mzoWt5i2YBZWY8xzjUPn ++pT7nHnAk/vLP5+ZJqTjqKqhRaFLAOQgpEOUWaSKxURNGSWvbeKsvUWiB0R X-Google-Smtp-Source: AGHT+IGGf8gjIvSIpmoMUyCRf4kP6idumDg3hWaWk/p29ZHp6DcDle4MouhqOpP1xFj8J24qayKsbA== X-Received: by 2002:a17:907:ea0:b0:a8d:2624:1a84 with SMTP id a640c23a62f3a-a90296100ddmr902005066b.11.1726554124243; Mon, 16 Sep 2024 23:22:04 -0700 (PDT) Received: from fc8b2ad344cc.pool3007.local ([83.68.141.146]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9061328e61sm403556366b.196.2024.09.16.23.22.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Sep 2024 23:22:03 -0700 (PDT) From: Lothar Rubusch To: u-boot@lists.denx.de, trini@konsulko.com, marex@denx.de, simon.k.r.goldschmidt@gmail.com, tien.fong.chee@intel.com Cc: l.rubusch@gmail.com Subject: [PATCH v2 6/7] ARM: socfpga: add Enclustra AA1 boot scripts Date: Tue, 17 Sep 2024 06:21:56 +0000 Message-Id: <20240917062157.3181-7-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240917062157.3181-1-l.rubusch@gmail.com> References: <20240917062157.3181-1-l.rubusch@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 18 Sep 2024 08:14:47 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add support to boot Enclustra SoMs from MMC, SD or QSPI flash. Signed-off-by: Lothar Rubusch --- board/enclustra/bootscripts/qspi-aa1.cmd | 12 ++++++++++++ board/enclustra/bootscripts/sd-aa1.cmd | 10 ++++++++++ 2 files changed, 22 insertions(+) create mode 100644 board/enclustra/bootscripts/qspi-aa1.cmd create mode 100644 board/enclustra/bootscripts/sd-aa1.cmd diff --git a/board/enclustra/bootscripts/qspi-aa1.cmd b/board/enclustra/bootscripts/qspi-aa1.cmd new file mode 100644 index 0000000000..42d02cfce1 --- /dev/null +++ b/board/enclustra/bootscripts/qspi-aa1.cmd @@ -0,0 +1,12 @@ +# This is an example input file for boot.scr generation. +# Generate boot.scr +# ./tools/mkimage -A arm -O linux -T script -C none -a 0 -e 0 -d board/enclustra/bootscripts/qspi-aa1.cmd boot.scr +# +# NB: The needed variables need to be set in the environment. +bridge enable +sf probe +sf read $kernel_addr_r $qspi_offset_addr_kernel $kernel_size +sf read $fdt_addr_r $qspi_offset_addr_devicetree $fdt_size +sf read $rootfs_addr_r $qspi_offset_addr_rootfs $rootfs_size +run fdtload_qspi +bootm $kernel_addr_r $rootfs_addr_r $fdt_addr_r diff --git a/board/enclustra/bootscripts/sd-aa1.cmd b/board/enclustra/bootscripts/sd-aa1.cmd new file mode 100644 index 0000000000..4beefc7e13 --- /dev/null +++ b/board/enclustra/bootscripts/sd-aa1.cmd @@ -0,0 +1,10 @@ +# This is an example input file for boot.scr generation. +# Generate boot.scr +# ./tools/mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n "U-boot mmc start script" -d board/enclustra/bootscripts/sd-aa1.cmd boot.scr +# +# NB: The needed variables need to be set in the environment. +bridge enable +fatload mmc $devnum:$distro_bootpart $kernel_addr_r Image +fatload mmc $devnum:$distro_bootpart $fdt_addr_r $fdtfile +run fdtload +bootm $kernel_addr_r - $fdt_addr_r From patchwork Tue Sep 17 06:21:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 1986685 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20230601 header.b=TARFpRba; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X7pLZ22Dfz1y1g for ; Wed, 18 Sep 2024 16:16:06 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id AE4AA88EFE; Wed, 18 Sep 2024 08:14:50 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="TARFpRba"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id E022A88CBB; Tue, 17 Sep 2024 08:22:08 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [IPv6:2a00:1450:4864:20::534]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id AF4C288D5C for ; Tue, 17 Sep 2024 08:22:05 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=l.rubusch@gmail.com Received: by mail-ed1-x534.google.com with SMTP id 4fb4d7f45d1cf-5c42bad4eb9so273823a12.2 for ; Mon, 16 Sep 2024 23:22:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726554125; x=1727158925; darn=lists.denx.de; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8JttTZz4Ql1M90z5DqNOjEGdjkFPqgzN7mWbBzn6EaA=; b=TARFpRbaZTNVoyKbupefQhwC+aTK6oZxkixyVSwjveGj8iLx02lRwwXPsZqynPtVfC 7di8EIN4OQlMFpoEmYRt7iTIBUTDx+xYHb9/xDHLau+46eJxIu4+LmaZuIqt+q8Bw9oD 8/+IHI8b2ZWI7rUe2tbHFRmyC4i9DsbXM36qv95XZ3XWewO4mCxioaI8rPIGjRe3161u H0mxbWKN58ZXnTdx/I66b59YBbUvDaOmiwhLKS8IrLnQESHvn3ZrxGwEg3VM4L2cVOpp FkQFq8DzCRCR1dHlzvqtU1CcERoIPLp25uH4A+MDhJXEKnOhSerNYLCAZyxUxgGA4YGj tBWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726554125; x=1727158925; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8JttTZz4Ql1M90z5DqNOjEGdjkFPqgzN7mWbBzn6EaA=; b=qqexD0MHH1cs9bOwGQuAStNC+XDlNBCVVQsYK74zTjTLlda89VUaZ3t8zwsBO8sbwB XVfPzoc2IowG4tshQoGyHcQodQWi9gnxVnjP7i/tsacpOq6XG0c9Fa7yVL66unO36IrE h9LRrRuqVs7kZKI+oA+2/6+YzwOEuTAp+wSkshnNjlXDjiqoMY+flMofOfPxwxyyUhT+ C7NV6YW1dqF0HcaWuZMJKT9z4WzZ1oH7Tho69yxVIeicNuWUZFNtl3099ha49bBfijat Tnp1pjSncCKhhLjep2sdMeYT6Gj0Vh8N/7JKquEvukNim4CVQnFhEHI52Y82YthtC39u aGyA== X-Gm-Message-State: AOJu0Yw8jJ7gheaYZRbT4RU+HlVe1XvKrEw8fPCTZbJMAU3QolNK2i7s utzlvg4k6DiF3TLXVkeiGnkGgZBVU42IptArvMOsIMEiKEX8KVpMxMqrR+bX X-Google-Smtp-Source: AGHT+IHE0OTecpMP6WhbDQrj09/bo8Gs3aViRTJhslBSjODTtDyfnKcDDr/zcdYyyQp73DykHFqE8w== X-Received: by 2002:a17:906:f5aa:b0:a8d:2624:1a86 with SMTP id a640c23a62f3a-a9029645b74mr782926466b.13.1726554125147; Mon, 16 Sep 2024 23:22:05 -0700 (PDT) Received: from fc8b2ad344cc.pool3007.local ([83.68.141.146]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9061328e61sm403556366b.196.2024.09.16.23.22.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Sep 2024 23:22:04 -0700 (PDT) From: Lothar Rubusch To: u-boot@lists.denx.de, trini@konsulko.com, marex@denx.de, simon.k.r.goldschmidt@gmail.com, tien.fong.chee@intel.com Cc: l.rubusch@gmail.com Subject: [PATCH v2 7/7] ARM: socfpga: AA1: support MAC from secure eeprom Date: Tue, 17 Sep 2024 06:21:57 +0000 Message-Id: <20240917062157.3181-8-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240917062157.3181-1-l.rubusch@gmail.com> References: <20240917062157.3181-1-l.rubusch@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 18 Sep 2024 08:14:47 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Several Enclustra devices store MAC address in a secure eeprom device. In most cases this is the atsha204a (alternatively DS28). The atsha204a device is preconfigured accordingly. Reading then is based on u-boot's atsha204a driver. Add such support for Enclustra's AA1 SoMs. Signed-off-by: Lothar Rubusch --- board/enclustra/common/Kconfig | 23 +++++ board/enclustra/common/Makefile | 3 + board/enclustra/common/enclustra_mac.h | 48 +++++++++ board/enclustra/common/mac_atsha204.c | 97 +++++++++++++++++++ board/enclustra/common/mac_common.c | 54 +++++++++++ board/enclustra/common/mac_ds28.c | 88 +++++++++++++++++ board/enclustra/mercury_aa1/Makefile | 2 + .../mercury_aa1/aa1_board_late_init.c | 17 ++++ .../socfpga_enclustra_mercury_aa1_defconfig | 1 + drivers/misc/Kconfig | 2 +- 10 files changed, 334 insertions(+), 1 deletion(-) create mode 100644 board/enclustra/common/enclustra_mac.h create mode 100644 board/enclustra/common/mac_atsha204.c create mode 100644 board/enclustra/common/mac_common.c create mode 100644 board/enclustra/common/mac_ds28.c create mode 100644 board/enclustra/mercury_aa1/aa1_board_late_init.c diff --git a/board/enclustra/common/Kconfig b/board/enclustra/common/Kconfig index 51169bada3..51991f7882 100644 --- a/board/enclustra/common/Kconfig +++ b/board/enclustra/common/Kconfig @@ -1 +1,24 @@ +config ENCLUSTRA_EEPROM_MAC + bool "Enclustra MAC address" + select ATSHA204A + default y if TARGET_SOCFPGA_ENCLUSTRA_MERCURY_AA1 + help + Reads the MAC address out of the EEPROM and configures the MAC + addresses in the environment. + +choice + prompt "Enclustra EEPROM device" + depends on ENCLUSTRA_EEPROM_MAC + default ENCLUSTRA_EEPROM_MAC_ATSHA204 if TARGET_SOCFPGA_ENCLUSTRA_MERCURY_AA1 + help + Specify the device where the MAC is stored. + +config ENCLUSTRA_EEPROM_MAC_ATSHA204 + bool "MAC stored in 'ATSHA204'" + +config ENCLUSTRA_EEPROM_MAC_DS28 + bool "MAC stored in 'DS28'" + +endchoice + source "board/enclustra/mercury_aa1/Kconfig" diff --git a/board/enclustra/common/Makefile b/board/enclustra/common/Makefile index 16c8531d74..c83743abe7 100644 --- a/board/enclustra/common/Makefile +++ b/board/enclustra/common/Makefile @@ -2,3 +2,6 @@ # Copyright (c) 2024 Enclustra GmbH # Common for several Enclustra modules +obj-$(CONFIG_ENCLUSTRA_EEPROM_MAC) += mac_common.o +obj-$(CONFIG_ENCLUSTRA_EEPROM_MAC_ATSHA204) += mac_atsha204.o +obj-$(CONFIG_ENCLUSTRA_EEPROM_MAC_DS28) += mac_ds28.o diff --git a/board/enclustra/common/enclustra_mac.h b/board/enclustra/common/enclustra_mac.h new file mode 100644 index 0000000000..9631e9d458 --- /dev/null +++ b/board/enclustra/common/enclustra_mac.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright 2024 Enclustra GmbH, + */ + +#ifndef ENCLUSTRA_MAC +# define ENCLUSTRA_MAC 0xF7B020 +#endif + +/* + * enclustra_mac_is_in_env - Check if MAC address is already set + * + * @env: name of the environment variable + * Return: true if MAC is set, false otherwise + */ +bool enclustra_mac_is_in_env(const char *env); + +/* + * enclustra_get_mac_is_enabled - Test if ethernet MAC is enabled in DT + * + * @alias: alias for ethernet MAC device tree node + * Return: 0 if OK, other value on error + */ +int enclustra_get_mac_is_enabled(const char *alias); + +/* + * enclustra_get_mac_from_eeprom - Get MAC address from eeprom and write it to enetaddr + * + * @enetaddr: buffer where address is to be stored + * @alias: alias for EEPROM device tree node + * Return: 0 if OK, other value on error + */ +int enclustra_get_mac_from_eeprom(unsigned char *enetaddr, const char *alias); + +/* + * enclustra_get_mac1_from_mac - Get MAC1 address from MAC and write it to enetaddr + * + * @enetaddr: buffer where MAC is passed, MAC will be modified to MAC1 + * Return: 0 if OK, else error value + */ +int enclustra_get_mac1_from_mac(unsigned char *enetaddr); + +/* + * enclustra_setup_mac_address - Try to get MAC address from various locations and write it to env + * + * Return: 0 if OK, other value on error + */ +int enclustra_setup_mac_address(void); diff --git a/board/enclustra/common/mac_atsha204.c b/board/enclustra/common/mac_atsha204.c new file mode 100644 index 0000000000..4bd25505d6 --- /dev/null +++ b/board/enclustra/common/mac_atsha204.c @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2024 Enclustra GmbH + */ + +#include +#include +#include + +#include "enclustra_mac.h" + +int enclustra_get_mac_from_eeprom(unsigned char *enetaddr, const char *alias) +{ + struct udevice *dev; + u32 hwaddr_h; + u8 data[4]; + int i, j, eeprom_addr, mac_len, ret; + + ret = uclass_get_device_by_name(UCLASS_MISC, alias, &dev); + if (ret) { + printf("%s: Failed, cannot find EEPROM! ret = %d\n", __func__, ret); + return ret; + } + + /* Make sure atsha204a is in a defined state (part of protocol) */ + if (atsha204a_sleep(dev)) { + printf("%s(): Failed to bring EEPROM in defined state\n", __func__); + return -ENODEV; + } + + if (atsha204a_wakeup(dev)) { + printf("%s(): Failed to wakeup EEPROM\n", __func__); + return -ENODEV; + } + + /* Read twice portions of 4 bytes (atsha204 protocol). One from address 4 + * the other from address 5 of the OTP zone. Then convert the data to + * the 6 elements of the MAC address. + */ + eeprom_addr = 4; + mac_len = 6; + for (i = 0; i < 2; i++) { + eeprom_addr += i; + if (atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, eeprom_addr, data)) { + printf("%s(): Failed to parse ATSHA204A_ZONE_OTP of EEPROM\n", + __func__); + return -EFAULT; + } + + for (j = 0; j < 4 && j + i * 4 < mac_len; j++) + enetaddr[j + i * 4] = data[j]; + } + + /* Check if the value is a valid mac registered for + * Enclustra GmbH + */ + hwaddr_h = enetaddr[0] | enetaddr[1] << 8 | enetaddr[2] << 16; + if ((hwaddr_h & 0xFFFFFF) != ENCLUSTRA_MAC) { + printf("%s(): Failed, parsed MAC is no Enclustra MAC\n", __func__); + return -ENOENT; + } + + if (!is_valid_ethaddr(enetaddr)) { + printf("%s(): Failed, address read from EEPROM is invalid!\n", + __func__); + return -EINVAL; + } + + printf("ethaddr set to %02X:%02X:%02X:%02X:%02X:%02X\n", + enetaddr[0], enetaddr[1], enetaddr[2], + enetaddr[3], enetaddr[4], enetaddr[5]); + + return 0; +} + +__weak int enclustra_setup_mac_address(void) +{ + unsigned char enetaddr[6]; + + if (enclustra_mac_is_in_env("ethaddr")) + return 0; + + if (enclustra_get_mac_is_enabled("ethernet0")) + return 0; + + if (enclustra_get_mac_from_eeprom(enetaddr, "atsha204a@64")) + return -ENXIO; + + if (eth_env_set_enetaddr("ethaddr", enetaddr)) + return -ENXIO; + + if (!enclustra_get_mac1_from_mac(enetaddr)) + return eth_env_set_enetaddr("eth1addr", enetaddr); + + printf("%s(): Failed, unable to set mac address!\n", __func__); + return -ENXIO; +} diff --git a/board/enclustra/common/mac_common.c b/board/enclustra/common/mac_common.c new file mode 100644 index 0000000000..cf5dac0e0e --- /dev/null +++ b/board/enclustra/common/mac_common.c @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2024 Enclustra GmbH + */ + +#include +#include +#include + +#include "enclustra_mac.h" + +bool enclustra_mac_is_in_env(const char *env) +{ + unsigned char enetaddr[6]; + + return eth_env_get_enetaddr(env, enetaddr); +} + +int enclustra_get_mac_is_enabled(const char *alias) +{ + ofnode node = ofnode_path(alias); + + if (!ofnode_valid(node)) + return -EINVAL; + + if (!ofnode_is_enabled(node)) + return -EINVAL; + + return 0; +} + +int enclustra_get_mac1_from_mac(unsigned char *enetaddr) +{ + u32 hwaddr_h; + + /* Increment MAC addr */ + hwaddr_h = (enetaddr[3] << 16) | (enetaddr[4] << 8) | enetaddr[5]; + hwaddr_h = (hwaddr_h + 1) & 0xFFFFFF; + enetaddr[3] = (hwaddr_h >> 16) & 0xFF; + enetaddr[4] = (hwaddr_h >> 8) & 0xFF; + enetaddr[5] = hwaddr_h & 0xFF; + + if (!is_valid_ethaddr(enetaddr)) { + printf("%s(): Failed, address computed from enetaddr is invalid!\n", + __func__); + return -EINVAL; + } + + printf("eth1addr set to %02X:%02X:%02X:%02X:%02X:%02X\n", + enetaddr[0], enetaddr[1], enetaddr[2], + enetaddr[3], enetaddr[4], enetaddr[5]); + + return 0; +} diff --git a/board/enclustra/common/mac_ds28.c b/board/enclustra/common/mac_ds28.c new file mode 100644 index 0000000000..9aed4f1de1 --- /dev/null +++ b/board/enclustra/common/mac_ds28.c @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2024 Enclustra GmbH + */ + +#include +#include +#include +#include + +#include "enclustra_mac.h" + +#define DS28_I2C_ADDR 0x5C +#define DS28_SYS_I2C_EEPROM_BUS 0 + +int enclustra_get_mac_from_eeprom(unsigned char *enetaddr, const char *alias) +{ + struct udevice *dev; + u32 hwaddr_h; + struct dm_i2c_chip *chip; + uint chip_addr = DS28_I2C_ADDR; + int alen = 1; + int ret; + + if (i2c_get_chip_for_busnum(DS28_SYS_I2C_EEPROM_BUS, chip_addr, + alen, &dev)) + return -ENODEV; + + chip = dev_get_parent_plat(dev); + if (chip->offset_len != alen) { + debug("I2C chip %x: alen %d does not match offset_len %d\n", + chip_addr, alen, chip->offset_len); + return -EADDRNOTAVAIL; + } + + ret = dm_i2c_read(dev, 0x10, enetaddr, 6); + if (ret) { + printf("%s(): Failed reading EEPROM! ret = %d\n", __func__, ret); + return ret; + } + + /* Check if the value is a valid mac registered for + * Enclustra GmbH + */ + hwaddr_h = enetaddr[0] | enetaddr[1] << 8 | enetaddr[2] << 16; + if ((hwaddr_h & 0xFFFFFF) != ENCLUSTRA_MAC) { + printf("%s(): Failed, parsed MAC is no Enclustra MAC\n", __func__); + return -ENOENT; + } + + if (!is_valid_ethaddr(enetaddr)) { + printf("%s(): Failed, address read from EEPROM is invalid!\n", + __func__); + return -EINVAL; + } + + printf("ethaddr set to %02X:%02X:%02X:%02X:%02X:%02X\n", + enetaddr[0], enetaddr[1], enetaddr[2], + enetaddr[3], enetaddr[4], enetaddr[5]); + + return 0; +} + +__weak int enclustra_setup_mac_address(void) +{ + unsigned char enetaddr[6]; + + if (enclustra_mac_is_in_env("ethaddr")) + return 0; + + if (enclustra_get_mac_is_enabled("ethernet0")) + return 0; + + // NB: DS28 is still not available in official DT, so referencing + // here by i2c busnumber and address directly + // preparation for DT access here, though + if (enclustra_get_mac_from_eeprom(enetaddr, "")) + return -ENXIO; + + if (eth_env_set_enetaddr("ethaddr", enetaddr)) + return -ENXIO; + + if (!enclustra_get_mac1_from_mac(enetaddr)) + return eth_env_set_enetaddr("eth1addr", enetaddr); + + printf("%s(): Failed, unable to set mac address!\n", __func__); + return -ENXIO; +} diff --git a/board/enclustra/mercury_aa1/Makefile b/board/enclustra/mercury_aa1/Makefile index 53c84d8156..b145254466 100644 --- a/board/enclustra/mercury_aa1/Makefile +++ b/board/enclustra/mercury_aa1/Makefile @@ -6,3 +6,5 @@ ifeq ($(CONFIG_SPL_BUILD),) obj-y += aa1_set_storage_cmd.o endif + +obj-y += aa1_board_late_init.o diff --git a/board/enclustra/mercury_aa1/aa1_board_late_init.c b/board/enclustra/mercury_aa1/aa1_board_late_init.c new file mode 100644 index 0000000000..2e8f8459e3 --- /dev/null +++ b/board/enclustra/mercury_aa1/aa1_board_late_init.c @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Enclustra GmbH + * + */ + +#include +#include +#include +#include + +#include "../common/enclustra_mac.h" + +int board_late_init(void) +{ + return enclustra_setup_mac_address(); +} diff --git a/configs/socfpga_enclustra_mercury_aa1_defconfig b/configs/socfpga_enclustra_mercury_aa1_defconfig index b475bd916d..58c718864b 100644 --- a/configs/socfpga_enclustra_mercury_aa1_defconfig +++ b/configs/socfpga_enclustra_mercury_aa1_defconfig @@ -26,6 +26,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_BOARD_LATE_INIT=y CONFIG_CLOCKS=y CONFIG_SPL_PAD_TO=0x40000 CONFIG_SPL_NO_BSS_LIMIT=y diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 6009d55f40..90fa8c9eae 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -73,7 +73,7 @@ config ATSHA204A help Enable support for I2C connected Atmel's ATSHA204A CryptoAuthentication module found for example on the Turris Omnia - board. + board and Enclustra SoC FPGA boards. config GATEWORKS_SC bool "Gateworks System Controller Support"