From patchwork Wed Sep 11 06:29:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1983696 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=LLQY2Ggy; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X3W1k6VRGz1y1C for ; Wed, 11 Sep 2024 16:31:38 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 39F9C385840B for ; Wed, 11 Sep 2024 06:31:36 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by sourceware.org (Postfix) with ESMTPS id 3ED7A3858C98 for ; Wed, 11 Sep 2024 06:31:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3ED7A3858C98 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 3ED7A3858C98 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1726036270; cv=none; b=uLan4VcoC//AzpuZaHCcl8k+EaRi2He9YDHqkBv64Hz0x6vuVcZ16d+RWyo1Al75AOjchN+/C5nUcgwmNWLu6j3LBs2MtaqsKkjaZYEgpUtVx6LWj5lc8QfNY36jW64tuKSO4QiDo7n2WnTH8QL6Jbp8IYCdG+rZcRY2rjeFjKU= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1726036270; c=relaxed/simple; bh=rcA1EWt5F62aer5+xGFEnNFPKaA4dT+DDtnxhMMy8bM=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=Cs+wpJ/X9m7yBSe23tSkmEzGDdXrjdBltIoE2ooix8PQ9osPpmE5/irA7fuBpUOdROGAswqlXxgay+DmchoR7jqEpg1YxZqEO6AnOgEamhZsmZ9nARUAusgdXs2MeGERoPdcWiu4sUG9Zu6/KC73ENNS9pXNbl/K6w0ngCNGOS8= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1726036263; x=1757572263; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=rcA1EWt5F62aer5+xGFEnNFPKaA4dT+DDtnxhMMy8bM=; b=LLQY2GgypbqxmpG7B8G79IW+az3+2GVyLGkUTC/hYXc7ntrkb4KdBeAX UHoL8+4LnmNpx1/iu6kdBsvnUyu5vKMbqfb2LowS12+qpqsQyU/zr5T4i bSinAzVmXHpIELqEbUd7EoaEmLuPA2tI9o4PmhL6WToYDatK6/G2zoEp7 g8hbXZhZZwhGtItRVpNFMsYbl5XIAZZmea1/NnqKu36mIbg2f3n5trF69 PgLvw7VvbOMGcL9/zxqC9CuShasQriA7yUj30XY2KRPHHKKR2T8oxdEgK FVm5omqmlmq3ZgU1NWxrr6HYARm0fpiALM2JnSksAsNGI6gd70WQFChST w==; X-CSE-ConnectionGUID: Y0r3JmJlQ0aDjngA5zVpVQ== X-CSE-MsgGUID: LO/8Ai5BS5K9jzA5It/SKw== X-IronPort-AV: E=McAfee;i="6700,10204,11191"; a="25013731" X-IronPort-AV: E=Sophos;i="6.10,219,1719903600"; d="scan'208";a="25013731" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Sep 2024 23:30:55 -0700 X-CSE-ConnectionGUID: yJv5FkXTRHmoj7RzproSFQ== X-CSE-MsgGUID: lGNo0traQCei6zQBTXX+ZA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,219,1719903600"; d="scan'208";a="66974655" Received: from panli.sh.intel.com ([10.239.154.73]) by fmviesa007.fm.intel.com with ESMTP; 10 Sep 2024 23:30:38 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: richard.guenther@gmail.com, Tamar.Christina@arm.com, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v3 1/5] Genmatch: Add control flow graph match for case 0 and case 1 Date: Wed, 11 Sep 2024 14:29:41 +0800 Message-ID: <20240911062945.3358247-1-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li The gen_phi_on_cond can only support below control flow for cond from day 1. Aka: +------+ | def | | ... | +-----+ | cond |------>| def | +------+ | ... | | +-----+ | | v | +-----+ | | PHI |<----------+ +-----+ Unfortunately, there will be more scenarios of control flow on PHI. For example as below: T __attribute__((noinline)) \ sat_s_add_##T##_fmt_3 (T x, T y) \ { \ T sum; \ bool overflow = __builtin_add_overflow (x, y, &sum); \ return overflow ? x < 0 ? MIN : MAX : sum; \ } DEF_SAT_S_ADD_FMT_3(int8_t, uint8_t, INT8_MIN, INT8_MAX) With expanded RTL like below. 3 │ 4 │ __attribute__((noinline)) 5 │ int8_t sat_s_add_int8_t_fmt_3 (int8_t x, int8_t y) 6 │ { 7 │ signed char _1; 8 │ signed char _2; 9 │ int8_t _3; 10 │ __complex__ signed char _6; 11 │ _Bool _8; 12 │ signed char _9; 13 │ signed char _10; 14 │ signed char _11; 15 │ 16 │ ;; basic block 2, loop depth 0 17 │ ;; pred: ENTRY 18 │ _6 = .ADD_OVERFLOW (x_4(D), y_5(D)); 19 │ _2 = IMAGPART_EXPR <_6>; 20 │ if (_2 != 0) 21 │ goto ; [50.00%] 22 │ else 23 │ goto ; [50.00%] 24 │ ;; succ: 4 25 │ ;; 3 26 │ 27 │ ;; basic block 3, loop depth 0 28 │ ;; pred: 2 29 │ _1 = REALPART_EXPR <_6>; 30 │ goto ; [100.00%] 31 │ ;; succ: 5 32 │ 33 │ ;; basic block 4, loop depth 0 34 │ ;; pred: 2 35 │ _8 = x_4(D) < 0; 36 │ _9 = (signed char) _8; 37 │ _10 = -_9; 38 │ _11 = _10 ^ 127; 39 │ ;; succ: 5 40 │ 41 │ ;; basic block 5, loop depth 0 42 │ ;; pred: 3 43 │ ;; 4 44 │ # _3 = PHI <_1(3), _11(4)> 45 │ return _3; 46 │ ;; succ: EXIT 47 │ 48 │ } The above code will have below control flow which is not supported by the gen_phi_on_cond. +------+ | def | | ... | +-----+ | cond |------>| def | +------+ | ... | | +-----+ | | v | +-----+ | | def | | | ... | | +-----+ | | | | | v | +-----+ | | PHI |<----------+ +-----+ This patch would like to add support above control flow matching for the gen_phi_on_cond. The below testsuites are passed for this patch: * The rv64gcv fully regression test. * The x86 bootstrap test. * The x86 fully regression test. gcc/ChangeLog: * gimple-match-head.cc (match_control_flow_graph_case_0): Add new func impl to match case 0 of cfg. (match_control_flow_graph_case_1): Ditto but for case 1. Signed-off-by: Pan Li --- gcc/gimple-match-head.cc | 115 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 115 insertions(+) diff --git a/gcc/gimple-match-head.cc b/gcc/gimple-match-head.cc index 924d3f1e710..c51728ae742 100644 --- a/gcc/gimple-match-head.cc +++ b/gcc/gimple-match-head.cc @@ -375,3 +375,118 @@ gimple_bitwise_inverted_equal_p (tree expr1, tree expr2, bool &wascmp, tree (*va return true; return false; } + +/* + * Return TRUE if the cfg matches the below layout by the given b2 in + * the first argument. Or return FALSE. + * + * If return TRUE, the output argument b_out will be updated to the b0 + * block as below example. + * + * If return FALSE, the output argument b_out will be NULL_BLOCK. + * + * | + * | + * v + * +------+ + * | b0: | + * | def | +-----+ + * | ... | | b1: | + * | cond |------>| def | + * +------+ | ... | + * | +-----+ + * | | + * v | + * +-----+ | + * | b2: | | + * | def |<----------+ + * +-----+ + */ +static inline bool +match_control_flow_graph_case_0 (basic_block b2, basic_block *b_out) +{ + *b_out = NULL; + + if (EDGE_COUNT (b2->preds) != 2) + return false; + + basic_block pred_0 = EDGE_PRED (b2, 0)->src; + basic_block pred_1 = EDGE_PRED (b2, 1)->src; + + if (pred_0 == NULL || pred_1 == NULL) + return false; + + if (!(EDGE_COUNT (pred_0->succs) == 2 && EDGE_COUNT (pred_1->succs) == 1) + && !(EDGE_COUNT (pred_0->succs) == 1 && EDGE_COUNT (pred_1->succs) == 2)) + return false; + + basic_block b0 = EDGE_COUNT (pred_0->succs) == 2 ? pred_0 : pred_1; + basic_block b1 = EDGE_COUNT (pred_0->succs) == 1 ? pred_0 : pred_1; + + if (EDGE_COUNT (b1->preds) != 1 || EDGE_PRED (b1, 0)->src != b0) + return false; + + *b_out = b0; + return true; +} + +/* + * Return TRUE if the cfg matches the below layout by the given b3 in + * the first argument. Or return FALSE. + * + * If return TRUE, the output argument b_out will be updated to the b0 + * block as below example. + * + * If return FALSE, the output argument b_out will be NULL. + * + * | + * | + * v + * +------+ + * | b0: | + * | ... | +-----+ + * | cond |------>| b2: | + * +------+ | ... | + * | +-----+ + * | | + * v | + * +-----+ | + * | b1: | | + * | ... | | + * +-----+ | + * | | + * | | + * v | + * +-----+ | + * | b3: |<----------+ + * | ... | + * +-----+ + */ +static inline bool +match_control_flow_graph_case_1 (basic_block b3, basic_block *b_out) +{ + *b_out = NULL; + + if (EDGE_COUNT (b3->preds) != 2) + return false; + + basic_block b1 = EDGE_PRED (b3, 0)->src; + basic_block b2 = EDGE_PRED (b3, 1)->src; + + if (b1 == NULL || b2 == NULL) + return false; + + if (EDGE_COUNT (b1->succs) != 1 + || EDGE_COUNT (b1->preds) != 1 + || EDGE_COUNT (b2->succs) != 1 + || EDGE_COUNT (b2->preds) != 1) + return false; + + basic_block b0 = EDGE_PRED (b1, 0)->src; + + if (EDGE_COUNT (b0->succs) != 2 || EDGE_PRED (b2, 0)->src != b0) + return false; + + *b_out = b0; + return true; +} From patchwork Wed Sep 11 06:29:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1983701 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=imy8H39m; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X3W2j2PbTz1y1C for ; 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X-CSE-ConnectionGUID: O3M8ESEqQ66LAvzS7IRlhg== X-CSE-MsgGUID: b2syOov4S1uS0Z3YcGEtsw== X-IronPort-AV: E=McAfee;i="6700,10204,11191"; a="25013755" X-IronPort-AV: E=Sophos;i="6.10,219,1719903600"; d="scan'208";a="25013755" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Sep 2024 23:30:56 -0700 X-CSE-ConnectionGUID: ulJxPTnZRO+I5TsbOL2qkA== X-CSE-MsgGUID: ZKQJz3fkRCG2iJFVcsSr6w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,219,1719903600"; d="scan'208";a="66974660" Received: from panli.sh.intel.com ([10.239.154.73]) by fmviesa007.fm.intel.com with ESMTP; 10 Sep 2024 23:30:40 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: richard.guenther@gmail.com, Tamar.Christina@arm.com, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v3 2/5] Match: Add interface match_cond_with_binary_phi for true/false arg Date: Wed, 11 Sep 2024 14:29:42 +0800 Message-ID: <20240911062945.3358247-2-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240911062945.3358247-1-pan2.li@intel.com> References: <20240911062945.3358247-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li When matching the cond with 2 args phi node, we need to figure out which arg of phi node comes from the true edge of cond block, as well as the false edge. This patch would like to add interface to perform the action and return the true and false arg in TREE type. There will be some additional handling if one of the arg is INTEGER_CST. Because the INTEGER_CST args may have no source block, thus its' edge source points to the condition block. See below example in line 31, the 255 INTEGER_CST has block 2 as source. Thus, we need to find the non-INTEGER_CST (aka _1) to tell which one is the true/false edge. For example, the _1(3) takes block 3 as source, which is the dest of false edge of the condition block. 4 │ __attribute__((noinline)) 5 │ uint8_t sat_u_add_imm_type_check_uint8_t_fmt_2 (uint8_t x) 6 │ { 7 │ unsigned char _1; 8 │ unsigned char _2; 9 │ uint8_t _3; 10 │ __complex__ unsigned char _5; 11 │ 12 │ ;; basic block 2, loop depth 0 13 │ ;; pred: ENTRY 14 │ _5 = .ADD_OVERFLOW (x_4(D), 9); 15 │ _2 = IMAGPART_EXPR <_5>; 16 │ if (_2 != 0) 17 │ goto ; [35.00%] 18 │ else 19 │ goto ; [65.00%] 20 │ ;; succ: 3 21 │ ;; 4 22 │ 23 │ ;; basic block 3, loop depth 0 24 │ ;; pred: 2 25 │ _1 = REALPART_EXPR <_5>; 26 │ ;; succ: 4 27 │ 28 │ ;; basic block 4, loop depth 0 29 │ ;; pred: 2 30 │ ;; 3 31 │ # _3 = PHI <255(2), _1(3)> 32 │ return _3; 33 │ ;; succ: EXIT 34 │ 35 │ } The below test suites are passed for this patch. * The rv64gcv fully regression test. * The x86 bootstrap test. * The x86 fully regression test. gcc/ChangeLog: * gimple-match-head.cc (match_cond_with_binary_phi): Add new func impl to match binary phi for true and false arg. Signed-off-by: Pan Li --- gcc/gimple-match-head.cc | 60 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/gcc/gimple-match-head.cc b/gcc/gimple-match-head.cc index c51728ae742..64f4f28cc72 100644 --- a/gcc/gimple-match-head.cc +++ b/gcc/gimple-match-head.cc @@ -490,3 +490,63 @@ match_control_flow_graph_case_1 (basic_block b3, basic_block *b_out) *b_out = b0; return true; } + +/* + * Return the relevant gcond * of the given phi, as well as the true + * and false TREE args of the phi. Or return NULL. + * + * If matched the gcond *, the output argument TREE true_arg and false_arg + * will be updated to the relevant args of phi. + * + * If failed to match, NULL gcond * will be returned, as well as the output + * arguments will be set to NULL_TREE. + */ + +static inline gcond * +match_cond_with_binary_phi (gphi *phi, tree *true_arg, tree *false_arg) +{ + basic_block cond_block; + *true_arg = *false_arg = NULL_TREE; + + if (gimple_phi_num_args (phi) != 2) + return NULL; + + if (!match_control_flow_graph_case_0 (gimple_bb (phi), &cond_block) + && !match_control_flow_graph_case_1 (gimple_bb (phi), &cond_block)) + return NULL; + + gcond *cond = safe_dyn_cast (*gsi_last_bb (cond_block)); + + if (!cond || EDGE_COUNT (cond_block->succs) != 2) + return NULL; + + tree t0 = gimple_phi_arg_def (phi, 0); + tree t1 = gimple_phi_arg_def (phi, 1); + edge e0 = gimple_phi_arg_edge (phi, 0); + edge e1 = gimple_phi_arg_edge (phi, 1); + + if (TREE_CODE (t0) == INTEGER_CST && TREE_CODE (t1) == INTEGER_CST) + return NULL; + + bool arg_0_cst_p = TREE_CODE (t0) == INTEGER_CST; + edge arg_edge = arg_0_cst_p ? e1 : e0; + tree arg = arg_0_cst_p ? t1 : t0; + tree other_arg = arg_0_cst_p ? t0 : t1; + + edge cond_e0 = EDGE_SUCC (cond_block, 0); + edge cond_e1 = EDGE_SUCC (cond_block, 1); + edge matched_edge = arg_edge->src == cond_e0->dest ? cond_e0 : cond_e1; + + if (matched_edge->flags & EDGE_TRUE_VALUE) + { + *true_arg = arg; + *false_arg = other_arg; + } + else + { + *false_arg = arg; + *true_arg = other_arg; + } + + return cond; +} From patchwork Wed Sep 11 06:29:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1983697 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=JEcTy3uu; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; 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d="scan'208";a="66974669" Received: from panli.sh.intel.com ([10.239.154.73]) by fmviesa007.fm.intel.com with ESMTP; 10 Sep 2024 23:30:43 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: richard.guenther@gmail.com, Tamar.Christina@arm.com, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v3 3/5] Genmatch: Refine the gen_phi_on_cond by match_cond_with_binary_phi Date: Wed, 11 Sep 2024 14:29:43 +0800 Message-ID: <20240911062945.3358247-3-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240911062945.3358247-1-pan2.li@intel.com> References: <20240911062945.3358247-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li This patch would like to leverage the match_cond_with_binary_phi to match the phi on cond, and get the true/false arg if matched. This helps a lot to simplify the implementation of gen_phi_on_cond. Before this patch: basic_block _b1 = gimple_bb (_a1); if (gimple_phi_num_args (_a1) == 2) { basic_block _pb_0_1 = EDGE_PRED (_b1, 0)->src; basic_block _pb_1_1 = EDGE_PRED (_b1, 1)->src; basic_block _db_1 = safe_dyn_cast (*gsi_last_bb (_pb_0_1)) ? _pb_0_1 : _pb_1_1; basic_block _other_db_1 = safe_dyn_cast (*gsi_last_bb (_pb_0_1)) ? _pb_1_1 : _pb_0_1; gcond *_ct_1 = safe_dyn_cast (*gsi_last_bb (_db_1)); if (_ct_1 && EDGE_COUNT (_other_db_1->preds) == 1 && EDGE_COUNT (_other_db_1->succs) == 1 && EDGE_PRED (_other_db_1, 0)->src == _db_1) { tree _cond_lhs_1 = gimple_cond_lhs (_ct_1); tree _cond_rhs_1 = gimple_cond_rhs (_ct_1); tree _p0 = build2 (gimple_cond_code (_ct_1), boolean_type_node, _cond_lhs_1, _cond_rhs_1); bool _arg_0_is_true_1 = gimple_phi_arg_edge (_a1, 0)->flags & EDGE_TRUE_VALUE; tree _p1 = gimple_phi_arg_def (_a1, _arg_0_is_true_1 ? 0 : 1); tree _p2 = gimple_phi_arg_def (_a1, _arg_0_is_true_1 ? 1 : 0); ... After this patch: basic_block _b1 = gimple_bb (_a1); tree _p1, _p2; gcond *_cond_1 = match_cond_with_binary_phi (_a1, &_p1, &_p2); if (_cond_1 && _p1 && _p2) { tree _cond_lhs_1 = gimple_cond_lhs (_cond_1); tree _cond_rhs_1 = gimple_cond_rhs (_cond_1); tree _p0 = build2 (gimple_cond_code (_cond_1), boolean_type_node, _cond_lhs_1, _cond_rhs_1); ... The below test suites are passed for this patch. * The rv64gcv fully regression test. * The x86 bootstrap test. * The x86 fully regression test. gcc/ChangeLog: * genmatch.cc (dt_operand::gen_phi_on_cond): Leverage the match_cond_with_binary_phi API to get cond gimple, true and false TREE arg. Signed-off-by: Pan Li --- gcc/genmatch.cc | 67 +++++++++++-------------------------------------- 1 file changed, 15 insertions(+), 52 deletions(-) diff --git a/gcc/genmatch.cc b/gcc/genmatch.cc index a56bd90cb2c..e3d2ecc6266 100644 --- a/gcc/genmatch.cc +++ b/gcc/genmatch.cc @@ -3516,79 +3516,42 @@ dt_operand::gen (FILE *f, int indent, bool gimple, int depth) void dt_operand::gen_phi_on_cond (FILE *f, int indent, int depth) { - fprintf_indent (f, indent, - "basic_block _b%d = gimple_bb (_a%d);\n", depth, depth); - - fprintf_indent (f, indent, "if (gimple_phi_num_args (_a%d) == 2)\n", depth); + char opname_0[20]; + char opname_1[20]; + char opname_2[20]; - indent += 2; - fprintf_indent (f, indent, "{\n"); - indent += 2; + gen_opname (opname_0, 0); + gen_opname (opname_1, 1); + gen_opname (opname_2, 2); fprintf_indent (f, indent, - "basic_block _pb_0_%d = EDGE_PRED (_b%d, 0)->src;\n", depth, depth); - fprintf_indent (f, indent, - "basic_block _pb_1_%d = EDGE_PRED (_b%d, 1)->src;\n", depth, depth); - fprintf_indent (f, indent, - "basic_block _db_%d = safe_dyn_cast (*gsi_last_bb (_pb_0_%d)) ? " - "_pb_0_%d : _pb_1_%d;\n", depth, depth, depth, depth); + "basic_block _b%d = gimple_bb (_a%d);\n", depth, depth); + fprintf_indent (f, indent, "tree %s, %s;\n", opname_1, opname_2); fprintf_indent (f, indent, - "basic_block _other_db_%d = safe_dyn_cast " - "(*gsi_last_bb (_pb_0_%d)) ? _pb_1_%d : _pb_0_%d;\n", - depth, depth, depth, depth); + "gcond *_cond_%d = match_cond_with_binary_phi (_a%d, &%s, &%s);\n", + depth, depth, opname_1, opname_2); - fprintf_indent (f, indent, - "gcond *_ct_%d = safe_dyn_cast (*gsi_last_bb (_db_%d));\n", - depth, depth); - fprintf_indent (f, indent, "if (_ct_%d" - " && EDGE_COUNT (_other_db_%d->preds) == 1\n", depth, depth); - fprintf_indent (f, indent, - " && EDGE_COUNT (_other_db_%d->succs) == 1\n", depth); - fprintf_indent (f, indent, - " && EDGE_PRED (_other_db_%d, 0)->src == _db_%d)\n", depth, depth); + fprintf_indent (f, indent, "if (_cond_%d && %s && %s)\n", + depth, opname_1, opname_2); indent += 2; fprintf_indent (f, indent, "{\n"); indent += 2; fprintf_indent (f, indent, - "tree _cond_lhs_%d = gimple_cond_lhs (_ct_%d);\n", depth, depth); + "tree _cond_lhs_%d = gimple_cond_lhs (_cond_%d);\n", depth, depth); fprintf_indent (f, indent, - "tree _cond_rhs_%d = gimple_cond_rhs (_ct_%d);\n", depth, depth); - - char opname_0[20]; - char opname_1[20]; - char opname_2[20]; - gen_opname (opname_0, 0); - + "tree _cond_rhs_%d = gimple_cond_rhs (_cond_%d);\n", depth, depth); fprintf_indent (f, indent, - "tree %s = build2 (gimple_cond_code (_ct_%d), " + "tree %s = build2 (gimple_cond_code (_cond_%d), " "boolean_type_node, _cond_lhs_%d, _cond_rhs_%d);\n", opname_0, depth, depth, depth); - fprintf_indent (f, indent, - "bool _arg_0_is_true_%d = gimple_phi_arg_edge (_a%d, 0)->flags" - " & EDGE_TRUE_VALUE;\n", depth, depth); - - gen_opname (opname_1, 1); - fprintf_indent (f, indent, - "tree %s = gimple_phi_arg_def (_a%d, _arg_0_is_true_%d ? 0 : 1);\n", - opname_1, depth, depth); - - gen_opname (opname_2, 2); - fprintf_indent (f, indent, - "tree %s = gimple_phi_arg_def (_a%d, _arg_0_is_true_%d ? 1 : 0);\n", - opname_2, depth, depth); - gen_kids (f, indent, true, depth); indent -= 2; fprintf_indent (f, indent, "}\n"); indent -= 2; - - indent -= 2; - fprintf_indent (f, indent, "}\n"); - indent -= 2; } /* Emit a logging call to the debug file to the file F, with the INDENT from From patchwork Wed Sep 11 06:29:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1983698 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=ZS8Mamfl; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X3W1v0Zcbz1y1C for ; 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X-CSE-ConnectionGUID: onYBnhiaTjqHEmjgpts/gA== X-CSE-MsgGUID: rJR2zNS1RKeaLXAzXP2w8g== X-IronPort-AV: E=McAfee;i="6700,10204,11191"; a="25013744" X-IronPort-AV: E=Sophos;i="6.10,219,1719903600"; d="scan'208";a="25013744" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Sep 2024 23:30:56 -0700 X-CSE-ConnectionGUID: PcRCtDDhTPeCdDAgXOEIUA== X-CSE-MsgGUID: aWCg3rfKTxCEpeZjIWdhrw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,219,1719903600"; d="scan'208";a="66974672" Received: from panli.sh.intel.com ([10.239.154.73]) by fmviesa007.fm.intel.com with ESMTP; 10 Sep 2024 23:30:45 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: richard.guenther@gmail.com, Tamar.Christina@arm.com, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v3 4/5] Match: Support form 3 for scalar signed integer .SAT_ADD Date: Wed, 11 Sep 2024 14:29:44 +0800 Message-ID: <20240911062945.3358247-4-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240911062945.3358247-1-pan2.li@intel.com> References: <20240911062945.3358247-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li This patch would like to support the form 3 of the scalar signed integer .SAT_ADD. Aka below example: Form 3: #define DEF_SAT_S_ADD_FMT_3(T, UT, MIN, MAX) \ T __attribute__((noinline)) \ sat_s_add_##T##_fmt_3 (T x, T y) \ { \ T sum; \ bool overflow = __builtin_add_overflow (x, y, &sum); \ return overflow ? x < 0 ? MIN : MAX : sum; \ } DEF_SAT_S_ADD_FMT_3(int8_t, uint8_t, INT8_MIN, INT8_MAX) We can tell the difference before and after this patch if backend implemented the ssadd3 pattern similar as below. Before this patch: 4 │ __attribute__((noinline)) 5 │ int8_t sat_s_add_int8_t_fmt_3 (int8_t x, int8_t y) 6 │ { 7 │ signed char _1; 8 │ signed char _2; 9 │ int8_t _3; 10 │ __complex__ signed char _6; 11 │ _Bool _8; 12 │ signed char _9; 13 │ signed char _10; 14 │ signed char _11; 15 │ 16 │ ;; basic block 2, loop depth 0 17 │ ;; pred: ENTRY 18 │ _6 = .ADD_OVERFLOW (x_4(D), y_5(D)); 19 │ _2 = IMAGPART_EXPR <_6>; 20 │ if (_2 != 0) 21 │ goto ; [50.00%] 22 │ else 23 │ goto ; [50.00%] 24 │ ;; succ: 4 25 │ ;; 3 26 │ 27 │ ;; basic block 3, loop depth 0 28 │ ;; pred: 2 29 │ _1 = REALPART_EXPR <_6>; 30 │ goto ; [100.00%] 31 │ ;; succ: 5 32 │ 33 │ ;; basic block 4, loop depth 0 34 │ ;; pred: 2 35 │ _8 = x_4(D) < 0; 36 │ _9 = (signed char) _8; 37 │ _10 = -_9; 38 │ _11 = _10 ^ 127; 39 │ ;; succ: 5 40 │ 41 │ ;; basic block 5, loop depth 0 42 │ ;; pred: 3 43 │ ;; 4 44 │ # _3 = PHI <_1(3), _11(4)> 45 │ return _3; 46 │ ;; succ: EXIT 47 │ 48 │ } After this patch: 4 │ __attribute__((noinline)) 5 │ int8_t sat_s_add_int8_t_fmt_3 (int8_t x, int8_t y) 6 │ { 7 │ int8_t _3; 8 │ 9 │ ;; basic block 2, loop depth 0 10 │ ;; pred: ENTRY 11 │ _3 = .SAT_ADD (x_4(D), y_5(D)); [tail call] 12 │ return _3; 13 │ ;; succ: EXIT 14 │ 15 │ } The below test suites are passed for this patch. * The rv64gcv fully regression test. * The x86 bootstrap test. * The x86 fully regression test. gcc/ChangeLog: * match.pd: Add the form 3 of signed .SAT_ADD matching. Signed-off-by: Pan Li --- gcc/match.pd | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/gcc/match.pd b/gcc/match.pd index 4cef965c9c7..167b1b106dd 100644 --- a/gcc/match.pd +++ b/gcc/match.pd @@ -3237,6 +3237,16 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) @2) (if (INTEGRAL_TYPE_P (type) && !TYPE_UNSIGNED (type)))) +/* Signed saturation add, case 4: + Z = .ADD_OVERFLOW (X, Y) + SAT_S_ADD = IMAGPART_EXPR (Z) != 0 ? (-(T)(X < 0) ^ MAX) : sum; */ +(match (signed_integer_sat_add @0 @1) + (cond^ (ne (imagpart (IFN_ADD_OVERFLOW:c@2 @0 @1)) integer_zerop) + (bit_xor:c (negate (convert (lt @0 integer_zerop))) max_value) + (realpart @2)) + (if (INTEGRAL_TYPE_P (type) && !TYPE_UNSIGNED (type) + && types_match (type, @0, @1)))) + /* Unsigned saturation sub, case 1 (branch with gt): SAT_U_SUB = X > Y ? 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X-CSE-ConnectionGUID: PeV/FMAATnmXM1l90bR4CA== X-CSE-MsgGUID: yXsUbfzkSDi/UQLPuJCygg== X-IronPort-AV: E=McAfee;i="6700,10204,11191"; a="25013750" X-IronPort-AV: E=Sophos;i="6.10,219,1719903600"; d="scan'208";a="25013750" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Sep 2024 23:30:56 -0700 X-CSE-ConnectionGUID: fmqkX/WuRDWhRJen+nD/JA== X-CSE-MsgGUID: Twu5dMXySQWka3cnd2uLcg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,219,1719903600"; d="scan'208";a="66974677" Received: from panli.sh.intel.com ([10.239.154.73]) by fmviesa007.fm.intel.com with ESMTP; 10 Sep 2024 23:30:47 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: richard.guenther@gmail.com, Tamar.Christina@arm.com, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v3 5/5] RISC-V: Fix vector SAT_ADD dump check due to middle-end change Date: Wed, 11 Sep 2024 14:29:45 +0800 Message-ID: <20240911062945.3358247-5-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240911062945.3358247-1-pan2.li@intel.com> References: <20240911062945.3358247-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li This patch would like fix the dump check times of vector SAT_ADD. The middle-end change makes the match times from 2 to 4 times. The below test suites are passed for this patch. * The rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c: Adjust the dump check times from 2 to 4. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c: Ditto. Signed-off-by: Pan Li --- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c | 2 +- 16 files changed, 16 insertions(+), 16 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c index c525ba97c52..47dd5012cc6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_6(uint8_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c index 41372d08e52..df8d5a8d275 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_6(uint16_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c index dddebb54426..f286bd10e4b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_6(uint32_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c index ad5162d10a0..307ff36cc35 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_6(uint64_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c index 39c20b3cea6..3218962724c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_7(uint8_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c index 6eefaeebf31..922df02278d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_7(uint16_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c index 78beb1bd39e..7653f81531c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_7(uint32_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c index 369fa296d08..18803afd19a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_7(uint64_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c index e827cdd1657..e95d6f73c38 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_8(uint8_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c index af16f48e228..34e10236381 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_8(uint16_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c index 0a8eabfbad1..7fc5e73fe1d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_8(uint32_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c index 38cbdfbcf07..9684fdf37f7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_8(uint64_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c index fe8a5a8262d..96787fc15e2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_2(uint8_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c index 1aeb24eed0d..f155d7c47c7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_2(uint16_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c index 0d2b0e4ab80..5fdb67cc1ca 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_2(uint32_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c index 168c269f75e..eee4d902fb5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_2(uint64_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */