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a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1725927389; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=qwBnozHbj+1+MPcnn4cmAaty2V+btQZueolpQWtwk9w=; b=sa42syYWN82avDvCl9aIidzqo9ZM6zwe/W2uPE4N1pzX0CpEJcfSJntoQsgmoqFqjGAXJV Vx1d7p32vB2o6Cp+YXKgiVulvSYtop+HcBGmiH67maovoYXlv9FhBUgiwNaDaVQDmYS8kp UmFLT6t0P3os2peF3LX4U0AcWpV4jmfVp4zBrn35kjvZcMWwCOgCyl9gZ0oKzmy/LhGDnr iV+OlEE3kpDCWJCoh+P/MN0TuDe/LUi54INwLthiJZGPP5EDQdf9z9OvXzpl6BNc0OHCqk 9AIvDJwXCBX2ga+rT+Psc6vf1N83D8MNSGvECOBI3PCw8VHKYOtr8BlQOErxeA== To: u-boot@lists.denx.de Cc: Marek Vasut , Ilias Apalodimas , Nobuhiro Iwamatsu , Tom Rini Subject: [PATCH] sh: cache: Fill in invalidate_icache_all() Date: Tue, 10 Sep 2024 02:15:58 +0200 Message-ID: <20240910001612.88569-1-marek.vasut+renesas@mailbox.org> MIME-Version: 1.0 X-MBO-RS-META: 98rows8qkmxm13qhoswezy94661md4ki X-MBO-RS-ID: 399a87f5b62b1188897 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Implement invalidate_icache_all() by clearing all V bits in IC and OC. This is done by setting CCR cache control register ICI and OCI bits. Signed-off-by: Marek Vasut --- Cc: Ilias Apalodimas Cc: Nobuhiro Iwamatsu Cc: Tom Rini Cc: u-boot@lists.denx.de --- arch/sh/cpu/sh4/cache.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/sh/cpu/sh4/cache.c b/arch/sh/cpu/sh4/cache.c index d3c480e79ed..99acc599965 100644 --- a/arch/sh/cpu/sh4/cache.c +++ b/arch/sh/cpu/sh4/cache.c @@ -33,8 +33,9 @@ static inline void cache_wback_all(void) } } -#define CACHE_ENABLE 0 -#define CACHE_DISABLE 1 +#define CACHE_ENABLE 0 +#define CACHE_DISABLE 1 +#define CACHE_INVALIDATE 2 static int cache_control(unsigned int cmd) { @@ -46,7 +47,9 @@ static int cache_control(unsigned int cmd) if (ccr & CCR_CACHE_ENABLE) cache_wback_all(); - if (cmd == CACHE_DISABLE) + if (cmd == CACHE_INVALIDATE) + outl(CCR_CACHE_ICI | ccr, CCR); + else if (cmd == CACHE_DISABLE) outl(CCR_CACHE_STOP, CCR); else outl(CCR_CACHE_INIT, CCR); @@ -103,7 +106,7 @@ void icache_disable(void) void invalidate_icache_all(void) { - puts("No arch specific invalidate_icache_all available!\n"); + cache_control(CACHE_INVALIDATE); } int icache_status(void)