From patchwork Fri Sep 6 17:30:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jin Ma X-Patchwork-Id: 1981991 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.a=rsa-sha256 header.s=default header.b=n7gGn1yV; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X0jvT42dFz1y1G for ; Sat, 7 Sep 2024 03:31:32 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7F26D384A415 for ; Fri, 6 Sep 2024 17:31:30 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from out30-110.freemail.mail.aliyun.com (out30-110.freemail.mail.aliyun.com [115.124.30.110]) by sourceware.org (Postfix) with ESMTPS id 8953F385DDE2 for ; Fri, 6 Sep 2024 17:31:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8953F385DDE2 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.alibaba.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 8953F385DDE2 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=115.124.30.110 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1725643870; cv=none; b=jFRIL9FjUgmNWKMSv+uwGVhDxqzdZTsX+PZrpyriEoiOnAAHfFhL3B0ybcX6mzUKrbIlMfUAxwa1jyReu8bXua0dd9tIGAbr23MofB8C3Ujm1/NtRyMBwubpgbXYDbWBOd/8u6aH4gcqBVNKdnPhB2+MCvddw/u8Gp8tQfFoioc= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1725643870; c=relaxed/simple; bh=Sxy2kWrfs2czDj8GV9EWSeLHdc80sjS+N5rKs8cpYMw=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=Gwz5RSn28Mt8WO3pdseXvk5tL1ettgN1rX+5MEMRFb/XhN9A5cSoL0VHl8xW5yOZLNVpcdMDNDo12XEjXYopPBh6Vkds0RXls/CpMRZFyPPnlpQoozuegzM5OYk/jupnceiMXuc/SY4uizeV0uIHC2gKFavVOoKUSME5nheJZJc= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1725643861; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=FaSif7qusQe7qs0bjWQRY4zJPApOtw0xfMcHjQSYuVg=; b=n7gGn1yVhgDZpKI3Kc0vbbW5wypraSBI9t7gSF8XctFptCmuSw2SU00Sk6XnMz+xmoj62DC8KDfbCDhFzM4U68VwRb/ib77ZBtXwfPVPm98ef5m+LWYyO1mirxuCF9CuaROHeAuXLaVoRI1n7oiaujGjrEl4y5zqEVHpvpV2z6A= Received: from localhost.localdomain(mailfrom:jinma@linux.alibaba.com fp:SMTPD_---0WEQ67Hs_1725643858) by smtp.aliyun-inc.com; Sat, 07 Sep 2024 01:30:59 +0800 From: Jin Ma To: gcc-patches@gcc.gnu.org Cc: jeffreyalaw@gmail.com, juzhe.zhong@rivai.ai, pan2.li@intel.com, kito.cheng@gmail.com, jinma.contrib@gmail.com, Jin Ma Subject: [PATCH] RISC-V: Fix ICE for rvv in lto Date: Sat, 7 Sep 2024 01:30:47 +0800 Message-Id: <20240906173047.306-1-jinma@linux.alibaba.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 X-Spam-Status: No, score=-27.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY, URIBL_SBL_A, USER_IN_DEF_DKIM_WL, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org When we use flto, the function list of rvv will be generated twice, once in the cc1 phase and once in the lto phase. However, due to the different generation methods, the two lists are different. For example, when there is no zvfh or zvfhmin in arch, it is generated by calling function "riscv_pragma_intrinsic". since the TARGET_VECTOR_ELEN_FP_16 is enabled before rvv function generation, a list of rvv functions related to float16 will be generated. In the lto phase, the rvv function list is generated only by calling the function "riscv_init_builtins", but the TARGET_VECTOR_ELEN_FP_16 is disabled, so that the float16-related rvv function list cannot be generated like cc1. This will cause confusion, resulting in matching tothe wrong function due to inconsistent fcode in the lto phase, eventually leading to ICE. So I think we should be consistent with their generated lists, which is exactly what this patch does. But there is still a problem here. If we use "-fchecking", we still have ICE. This is because in the lto phase, after the rvv function list is generated and before the expand_builtin, the ggc_grow will be called to clean up the memory, resulting in "(* registered_functions)[code]->decl" being cleaned up to ", and finally ICE". I think this is wrong and needs to be fixed, maybe we shouldn't use "ggc_alloc ()", or is there another better way to implement it? I'm trying to fix it here. Any comments here? gcc/ChangeLog: * config/riscv/riscv-c.cc (struct pragma_intrinsic_flags): Mov to riscv-protos.h. (riscv_pragma_intrinsic_flags_pollute): Mov to riscv-vector-builtins.c. (riscv_pragma_intrinsic_flags_restore): Likewise. (riscv_pragma_intrinsic): Likewise. * config/riscv/riscv-protos.h (struct pragma_intrinsic_flags): New. (riscv_pragma_intrinsic_flags_restore): New. (riscv_pragma_intrinsic_flags_pollute): New. * config/riscv/riscv-vector-builtins.cc (riscv_pragma_intrinsic_flags_pollute): New. (riscv_pragma_intrinsic_flags_restore): New. (handle_pragma_vector_for_lto): New. (init_builtins): Correct the processing logic for lto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/bug-10.c: New test. --- gcc/config/riscv/riscv-c.cc | 70 +--------------- gcc/config/riscv/riscv-protos.h | 13 +++ gcc/config/riscv/riscv-vector-builtins.cc | 83 ++++++++++++++++++- .../gcc.target/riscv/rvv/base/bug-10.c | 18 ++++ 4 files changed, 114 insertions(+), 70 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/bug-10.c diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc index 71112d9c66d7..7037ecc1268a 100644 --- a/gcc/config/riscv/riscv-c.cc +++ b/gcc/config/riscv/riscv-c.cc @@ -34,72 +34,6 @@ along with GCC; see the file COPYING3. If not see #define builtin_define(TXT) cpp_define (pfile, TXT) -struct pragma_intrinsic_flags -{ - int intrinsic_target_flags; - - int intrinsic_riscv_vector_elen_flags; - int intrinsic_riscv_zvl_flags; - int intrinsic_riscv_zvb_subext; - int intrinsic_riscv_zvk_subext; -}; - -static void -riscv_pragma_intrinsic_flags_pollute (struct pragma_intrinsic_flags *flags) -{ - flags->intrinsic_target_flags = target_flags; - flags->intrinsic_riscv_vector_elen_flags = riscv_vector_elen_flags; - flags->intrinsic_riscv_zvl_flags = riscv_zvl_flags; - flags->intrinsic_riscv_zvb_subext = riscv_zvb_subext; - flags->intrinsic_riscv_zvk_subext = riscv_zvk_subext; - - target_flags = target_flags - | MASK_VECTOR; - - riscv_zvl_flags = riscv_zvl_flags - | MASK_ZVL32B - | MASK_ZVL64B - | MASK_ZVL128B; - - riscv_vector_elen_flags = riscv_vector_elen_flags - | MASK_VECTOR_ELEN_32 - | MASK_VECTOR_ELEN_64 - | MASK_VECTOR_ELEN_FP_16 - | MASK_VECTOR_ELEN_FP_32 - | MASK_VECTOR_ELEN_FP_64; - - riscv_zvb_subext = riscv_zvb_subext - | MASK_ZVBB - | MASK_ZVBC - | MASK_ZVKB; - - riscv_zvk_subext = riscv_zvk_subext - | MASK_ZVKG - | MASK_ZVKNED - | MASK_ZVKNHA - | MASK_ZVKNHB - | MASK_ZVKSED - | MASK_ZVKSH - | MASK_ZVKN - | MASK_ZVKNC - | MASK_ZVKNG - | MASK_ZVKS - | MASK_ZVKSC - | MASK_ZVKSG - | MASK_ZVKT; -} - -static void -riscv_pragma_intrinsic_flags_restore (struct pragma_intrinsic_flags *flags) -{ - target_flags = flags->intrinsic_target_flags; - - riscv_vector_elen_flags = flags->intrinsic_riscv_vector_elen_flags; - riscv_zvl_flags = flags->intrinsic_riscv_zvl_flags; - riscv_zvb_subext = flags->intrinsic_riscv_zvb_subext; - riscv_zvk_subext = flags->intrinsic_riscv_zvk_subext; -} - static int riscv_ext_version_value (unsigned major, unsigned minor) { @@ -269,14 +203,14 @@ riscv_pragma_intrinsic (cpp_reader *) { struct pragma_intrinsic_flags backup_flags; - riscv_pragma_intrinsic_flags_pollute (&backup_flags); + riscv_vector::riscv_pragma_intrinsic_flags_pollute (&backup_flags); riscv_option_override (); init_adjust_machine_modes (); riscv_vector::reinit_builtins (); riscv_vector::handle_pragma_vector (); - riscv_pragma_intrinsic_flags_restore (&backup_flags); + riscv_vector::riscv_pragma_intrinsic_flags_restore (&backup_flags); /* Re-initialize after the flags are restored. */ riscv_option_override (); diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 3358e3887b95..651df2310da6 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -102,6 +102,15 @@ struct riscv_address_info { int shift; }; +struct pragma_intrinsic_flags +{ + int intrinsic_target_flags; + int intrinsic_riscv_vector_elen_flags; + int intrinsic_riscv_zvl_flags; + int intrinsic_riscv_zvb_subext; + int intrinsic_riscv_zvk_subext; +}; + /* Routines implemented in riscv.cc. */ extern const char *riscv_asm_output_opcode (FILE *asm_out_file, const char *p); extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx); @@ -569,6 +578,10 @@ enum avl_type VLS = 2, }; /* Routines implemented in riscv-vector-builtins.cc. */ +void +riscv_pragma_intrinsic_flags_restore (struct pragma_intrinsic_flags *); +void +riscv_pragma_intrinsic_flags_pollute (struct pragma_intrinsic_flags *); void init_builtins (void); void reinit_builtins (void); const char *mangle_builtin_type (const_tree); diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index 41730c483ee1..c6ddbeea71e7 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -4505,6 +4505,83 @@ builtin_type_p (const_tree type) return lookup_vector_type_attribute (type); } +void +riscv_pragma_intrinsic_flags_pollute (struct pragma_intrinsic_flags *flags) +{ + flags->intrinsic_target_flags = target_flags; + flags->intrinsic_riscv_vector_elen_flags = riscv_vector_elen_flags; + flags->intrinsic_riscv_zvl_flags = riscv_zvl_flags; + flags->intrinsic_riscv_zvb_subext = riscv_zvb_subext; + flags->intrinsic_riscv_zvk_subext = riscv_zvk_subext; + + target_flags = target_flags + | MASK_VECTOR; + + riscv_zvl_flags = riscv_zvl_flags + | MASK_ZVL32B + | MASK_ZVL64B + | MASK_ZVL128B; + + riscv_vector_elen_flags = riscv_vector_elen_flags + | MASK_VECTOR_ELEN_32 + | MASK_VECTOR_ELEN_64 + | MASK_VECTOR_ELEN_FP_16 + | MASK_VECTOR_ELEN_FP_32 + | MASK_VECTOR_ELEN_FP_64; + + riscv_zvb_subext = riscv_zvb_subext + | MASK_ZVBB + | MASK_ZVBC + | MASK_ZVKB; + + riscv_zvk_subext = riscv_zvk_subext + | MASK_ZVKG + | MASK_ZVKNED + | MASK_ZVKNHA + | MASK_ZVKNHB + | MASK_ZVKSED + | MASK_ZVKSH + | MASK_ZVKN + | MASK_ZVKNC + | MASK_ZVKNG + | MASK_ZVKS + | MASK_ZVKSC + | MASK_ZVKSG + | MASK_ZVKT; +} + +void +riscv_pragma_intrinsic_flags_restore (struct pragma_intrinsic_flags *flags) +{ + target_flags = flags->intrinsic_target_flags; + + riscv_vector_elen_flags = flags->intrinsic_riscv_vector_elen_flags; + riscv_zvl_flags = flags->intrinsic_riscv_zvl_flags; + riscv_zvb_subext = flags->intrinsic_riscv_zvb_subext; + riscv_zvk_subext = flags->intrinsic_riscv_zvk_subext; +} + +/* Helper for init_builtins in LTO. */ +static void +handle_pragma_vector_for_lto () +{ + struct pragma_intrinsic_flags backup_flags; + + riscv_pragma_intrinsic_flags_pollute (&backup_flags); + + riscv_option_override (); + init_adjust_machine_modes (); + + register_builtin_types (); + + handle_pragma_vector (); + riscv_pragma_intrinsic_flags_restore (&backup_flags); + + /* Re-initialize after the flags are restored. */ + riscv_option_override (); + init_adjust_machine_modes (); +} + /* Initialize all compiler built-ins related to RVV that should be defined at start-up. */ void @@ -4513,9 +4590,11 @@ init_builtins () rvv_switcher rvv; if (!TARGET_VECTOR) return; - register_builtin_types (); + if (in_lto_p) - handle_pragma_vector (); + handle_pragma_vector_for_lto (); + else + register_builtin_types (); } /* Reinitialize builtins similar to init_builtins, but only the null diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-10.c new file mode 100644 index 000000000000..c6b49da0768e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-10.c @@ -0,0 +1,18 @@ +/* Test that we do not have ice when compile */ + +/* { dg-do run } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl -flto -O2 -fno-checking" } */ + +#include + +int +main () +{ + size_t vl = 8; + vint32m1_t vs1 = {}; + vint32m1_t vs2 = {}; + + __volatile__ vint32m1_t vd = __riscv_vadd_vv_i32m1(vs1, vs2, vl); + + return 0; +} From patchwork Tue Sep 10 05:56:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jin Ma X-Patchwork-Id: 1982959 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.a=rsa-sha256 header.s=default header.b=ArbUkXqd; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X2tJp13Bhz1y1C for ; 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Date: Tue, 10 Sep 2024 13:56:47 +0800 Message-Id: <20240910055647.634-1-jinma@linux.alibaba.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20240906173047.306-1-jinma@linux.alibaba.com> References: <20240906173047.306-1-jinma@linux.alibaba.com> MIME-Version: 1.0 X-Spam-Status: No, score=-27.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, UNPARSEABLE_RELAY, URIBL_SBL_A, USER_IN_DEF_DKIM_WL, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org When we use flto, the function list of rvv will be generated twice, once in the cc1 phase and once in the lto phase. However, due to the different generation methods, the two lists are different. For example, when there is no zvfh or zvfhmin in arch, it is generated by calling function "riscv_pragma_intrinsic". since the TARGET_VECTOR_ELEN_FP_16 is enabled before rvv function generation, a list of rvv functions related to float16 will be generated. In the lto phase, the rvv function list is generated only by calling the function "riscv_init_builtins", but the TARGET_VECTOR_ELEN_FP_16 is disabled, so that the float16-related rvv function list cannot be generated like cc1. This will cause confusion, resulting in matching tothe wrong function due to inconsistent fcode in the lto phase, eventually leading to ICE. So I think we should be consistent with their generated lists, which is exactly what this patch does. gcc/ChangeLog: * config/riscv/riscv-c.cc (struct pragma_intrinsic_flags): Mov to riscv-protos.h. (riscv_pragma_intrinsic_flags_pollute): Mov to riscv-vector-builtins.c. (riscv_pragma_intrinsic_flags_restore): Likewise. (riscv_pragma_intrinsic): Likewise. * config/riscv/riscv-protos.h (struct pragma_intrinsic_flags): New. (riscv_pragma_intrinsic_flags_restore): New. (riscv_pragma_intrinsic_flags_pollute): New. * config/riscv/riscv-vector-builtins.cc (riscv_pragma_intrinsic_flags_pollute): New. (riscv_pragma_intrinsic_flags_restore): New. (handle_pragma_vector_for_lto): New. (init_builtins): Correct the processing logic for lto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/bug-11.c: New test. --- gcc/config/riscv/riscv-c.cc | 70 +------------------ gcc/config/riscv/riscv-protos.h | 13 ++++ gcc/config/riscv/riscv-vector-builtins.cc | 83 ++++++++++++++++++++++- 3 files changed, 96 insertions(+), 70 deletions(-) diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc index 71112d9c66d7..7037ecc1268a 100644 --- a/gcc/config/riscv/riscv-c.cc +++ b/gcc/config/riscv/riscv-c.cc @@ -34,72 +34,6 @@ along with GCC; see the file COPYING3. If not see #define builtin_define(TXT) cpp_define (pfile, TXT) -struct pragma_intrinsic_flags -{ - int intrinsic_target_flags; - - int intrinsic_riscv_vector_elen_flags; - int intrinsic_riscv_zvl_flags; - int intrinsic_riscv_zvb_subext; - int intrinsic_riscv_zvk_subext; -}; - -static void -riscv_pragma_intrinsic_flags_pollute (struct pragma_intrinsic_flags *flags) -{ - flags->intrinsic_target_flags = target_flags; - flags->intrinsic_riscv_vector_elen_flags = riscv_vector_elen_flags; - flags->intrinsic_riscv_zvl_flags = riscv_zvl_flags; - flags->intrinsic_riscv_zvb_subext = riscv_zvb_subext; - flags->intrinsic_riscv_zvk_subext = riscv_zvk_subext; - - target_flags = target_flags - | MASK_VECTOR; - - riscv_zvl_flags = riscv_zvl_flags - | MASK_ZVL32B - | MASK_ZVL64B - | MASK_ZVL128B; - - riscv_vector_elen_flags = riscv_vector_elen_flags - | MASK_VECTOR_ELEN_32 - | MASK_VECTOR_ELEN_64 - | MASK_VECTOR_ELEN_FP_16 - | MASK_VECTOR_ELEN_FP_32 - | MASK_VECTOR_ELEN_FP_64; - - riscv_zvb_subext = riscv_zvb_subext - | MASK_ZVBB - | MASK_ZVBC - | MASK_ZVKB; - - riscv_zvk_subext = riscv_zvk_subext - | MASK_ZVKG - | MASK_ZVKNED - | MASK_ZVKNHA - | MASK_ZVKNHB - | MASK_ZVKSED - | MASK_ZVKSH - | MASK_ZVKN - | MASK_ZVKNC - | MASK_ZVKNG - | MASK_ZVKS - | MASK_ZVKSC - | MASK_ZVKSG - | MASK_ZVKT; -} - -static void -riscv_pragma_intrinsic_flags_restore (struct pragma_intrinsic_flags *flags) -{ - target_flags = flags->intrinsic_target_flags; - - riscv_vector_elen_flags = flags->intrinsic_riscv_vector_elen_flags; - riscv_zvl_flags = flags->intrinsic_riscv_zvl_flags; - riscv_zvb_subext = flags->intrinsic_riscv_zvb_subext; - riscv_zvk_subext = flags->intrinsic_riscv_zvk_subext; -} - static int riscv_ext_version_value (unsigned major, unsigned minor) { @@ -269,14 +203,14 @@ riscv_pragma_intrinsic (cpp_reader *) { struct pragma_intrinsic_flags backup_flags; - riscv_pragma_intrinsic_flags_pollute (&backup_flags); + riscv_vector::riscv_pragma_intrinsic_flags_pollute (&backup_flags); riscv_option_override (); init_adjust_machine_modes (); riscv_vector::reinit_builtins (); riscv_vector::handle_pragma_vector (); - riscv_pragma_intrinsic_flags_restore (&backup_flags); + riscv_vector::riscv_pragma_intrinsic_flags_restore (&backup_flags); /* Re-initialize after the flags are restored. */ riscv_option_override (); diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 3358e3887b95..651df2310da6 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -102,6 +102,15 @@ struct riscv_address_info { int shift; }; +struct pragma_intrinsic_flags +{ + int intrinsic_target_flags; + int intrinsic_riscv_vector_elen_flags; + int intrinsic_riscv_zvl_flags; + int intrinsic_riscv_zvb_subext; + int intrinsic_riscv_zvk_subext; +}; + /* Routines implemented in riscv.cc. */ extern const char *riscv_asm_output_opcode (FILE *asm_out_file, const char *p); extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx); @@ -569,6 +578,10 @@ enum avl_type VLS = 2, }; /* Routines implemented in riscv-vector-builtins.cc. */ +void +riscv_pragma_intrinsic_flags_restore (struct pragma_intrinsic_flags *); +void +riscv_pragma_intrinsic_flags_pollute (struct pragma_intrinsic_flags *); void init_builtins (void); void reinit_builtins (void); const char *mangle_builtin_type (const_tree); diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index 0176670fbdf2..421c40be3ba5 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -4510,6 +4510,83 @@ builtin_type_p (const_tree type) return lookup_vector_type_attribute (type); } +void +riscv_pragma_intrinsic_flags_pollute (struct pragma_intrinsic_flags *flags) +{ + flags->intrinsic_target_flags = target_flags; + flags->intrinsic_riscv_vector_elen_flags = riscv_vector_elen_flags; + flags->intrinsic_riscv_zvl_flags = riscv_zvl_flags; + flags->intrinsic_riscv_zvb_subext = riscv_zvb_subext; + flags->intrinsic_riscv_zvk_subext = riscv_zvk_subext; + + target_flags = target_flags + | MASK_VECTOR; + + riscv_zvl_flags = riscv_zvl_flags + | MASK_ZVL32B + | MASK_ZVL64B + | MASK_ZVL128B; + + riscv_vector_elen_flags = riscv_vector_elen_flags + | MASK_VECTOR_ELEN_32 + | MASK_VECTOR_ELEN_64 + | MASK_VECTOR_ELEN_FP_16 + | MASK_VECTOR_ELEN_FP_32 + | MASK_VECTOR_ELEN_FP_64; + + riscv_zvb_subext = riscv_zvb_subext + | MASK_ZVBB + | MASK_ZVBC + | MASK_ZVKB; + + riscv_zvk_subext = riscv_zvk_subext + | MASK_ZVKG + | MASK_ZVKNED + | MASK_ZVKNHA + | MASK_ZVKNHB + | MASK_ZVKSED + | MASK_ZVKSH + | MASK_ZVKN + | MASK_ZVKNC + | MASK_ZVKNG + | MASK_ZVKS + | MASK_ZVKSC + | MASK_ZVKSG + | MASK_ZVKT; +} + +void +riscv_pragma_intrinsic_flags_restore (struct pragma_intrinsic_flags *flags) +{ + target_flags = flags->intrinsic_target_flags; + + riscv_vector_elen_flags = flags->intrinsic_riscv_vector_elen_flags; + riscv_zvl_flags = flags->intrinsic_riscv_zvl_flags; + riscv_zvb_subext = flags->intrinsic_riscv_zvb_subext; + riscv_zvk_subext = flags->intrinsic_riscv_zvk_subext; +} + +/* Helper for init_builtins in LTO. */ +static void +handle_pragma_vector_for_lto () +{ + struct pragma_intrinsic_flags backup_flags; + + riscv_pragma_intrinsic_flags_pollute (&backup_flags); + + riscv_option_override (); + init_adjust_machine_modes (); + + register_builtin_types (); + + handle_pragma_vector (); + riscv_pragma_intrinsic_flags_restore (&backup_flags); + + /* Re-initialize after the flags are restored. */ + riscv_option_override (); + init_adjust_machine_modes (); +} + /* Initialize all compiler built-ins related to RVV that should be defined at start-up. */ void @@ -4518,9 +4595,11 @@ init_builtins () rvv_switcher rvv; if (!TARGET_VECTOR) return; - register_builtin_types (); + if (in_lto_p) - handle_pragma_vector (); + handle_pragma_vector_for_lto (); + else + register_builtin_types (); } /* Reinitialize builtins similar to init_builtins, but only the null