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Fri, 6 Sep 2024 04:32:10 -0500 From: Thippeswamy Havalige To: , , , , , , , , CC: , , , , Thippeswamy Havalige Subject: [PATCH 1/2] dt-bindings: PCI: xilinx-cpm: Add compatible string for CPM5 controller-1. Date: Fri, 6 Sep 2024 15:01:47 +0530 Message-ID: <20240906093148.830452-2-thippesw@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240906093148.830452-1-thippesw@amd.com> References: <20240906093148.830452-1-thippesw@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB04.amd.com: thippesw@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A103:EE_|DS0PR12MB8218:EE_ X-MS-Office365-Filtering-Correlation-Id: 430969aa-ae08-48ee-5c9f-08dcce56cb3d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|36860700013|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: pU7VHhDXZMIdu0vKSuGpK1cedd+O1LaNYgRWojOyUtNPz3zsRbpDODeDp/C3YZd1CEdTeh0GUZATkX63BpsQ4sskfD8lrl8NsKN/t3yx8q5WuvnNQdjVRv61mQeF+pjDGcDaQbpuPR2ieaVugU7SLCuiTpudokVjBiNcUDup2z+6oCBjXSuFFhnrxDARa7ts/Fs9+v93GBVtxFS1NsZD6DgBFusN4wQO+vISqnf4dX/01aZ1mRDdwUBzi/0sZR3g5oGG63ZkWujx8CZRHSvBTnjNuxKYs9cGHqYCON+c2qs/2nbh3j9Br9K57Oy+N1ysHxyin+04CrSt91ifFAfjaLwGcsnfTPtE7napJdRmuaHy2710SqhT3aygd1qJgCKtyaUAXzjQa+rQ/nodenlvbEDecaP/jVmqujZSt68CIYBWvU9nIEBgOiCH3oXDoHB9IiKu/h6T8Dzf/CYZDH8v5Sfj3by4utVia0JYol37c2qWne9bdcQYFRjoA+TVVqoOyxBUe+/sZ0Ela59m+JYG9tgPD69tBnnpyGfxPb63lamO2uFQWalt3BuQOGa6VzWmILmDaBifHuC4dsxTY/JaeKPBzOuMM5Qldh0C9c6dyXylj7x3JvwLt5Ousr81SZDaYhvFuz2AKXOYGrhcW8pItvVRjSjQhP/4kjRCK9i6DwbzSlY/bIAacQmF/ctofjQEVWg8CAk7VnkTyC0zVnOC/zBvyXO4tDuBsuxEL5hXmPgsxj/GCvTAJARps0EpLU5S6E8gm0t9wG3rIva6RbRTDx2wuJwBKDleqUmRY5aAoMehw5roQpjBZzdMMDEDgZ9NvwquUYYVpEpovUmxv6UQhQlPFnWN0XQS0zxYXq2mYWnidczeASF3UenmbxuzVuRnEb0UDuWXFByp3aNmL9JEru3dcPNXQSrmv/oEt58bR7aIrvbV4wuWOnfd8WoyqQYeWd3rmzZFZ1/3/0W/6I2LWQjY4pRl1KF/u1YP1L2cGxoth9PKg0nuY+QeCCM4e1VsTrGfmoFZMvZtUuT+zLkwM3INJlIKsdU0wx0M+ZG4g3dMNDacYu6s8Bc/WRy2PNvHfO+6fggJpmKkWrkEv+8hmVjs3ZsTbuq6RFPjthiJToPkvoboyydJz8mgDjeBygBpwOQkTUi5vuFgVXl3pO8TrgskyyDHRkV5egFwHZ/l0NjxhoO9KJONQrxp4jmbnp6IH9k/6p/9/tGiksqketbHpTa+61tJT95PYk0vOdHMUn9yl09144Hx8ctYMAsfcOHMG6hPH9Tbpe1fXcvO2VH7oYlTIaDZ5Y++cRAffbbmGPS7loSGFNO2lzqyfsCpqvJEoUr11zDsxC2TuhzjAUdh15webE/cvI21KiGp0hdBIavTR+uN6QZeivN2WCWA18zBc2HCo2luxfZjoSFDPTL4kKgnmUV//k/XVETgck3afq3q7CJ4Z/1YQpp+bCFkIuNM X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(7416014)(36860700013)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Sep 2024 09:32:15.1135 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 430969aa-ae08-48ee-5c9f-08dcce56cb3d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A103.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8218 The Xilinx Versal premium series has CPM5 block which supports two typeA Root Port controller functionality at Gen5 speed. Add compatible string to distinguish between two CPM5 rootport controller1. Error interrupt register and bits for both the controllers are at different. Signed-off-by: Thippeswamy Havalige --- Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml index 989fb0fa2577..b63a759ec2d7 100644 --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml @@ -17,6 +17,7 @@ properties: enum: - xlnx,versal-cpm-host-1.00 - xlnx,versal-cpm5-host + - xlnx,versal-cpm5-host1 reg: items: From patchwork Fri Sep 6 09:31:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thippeswamy Havalige X-Patchwork-Id: 1981723 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=amd.com header.i=@amd.com header.a=rsa-sha256 header.s=selector1 header.b=YA/KwICx; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Sep 2024 09:32:22.3380 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d9f89fac-557a-4b03-a6b0-08dcce56cf97 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D1.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7760 In the CPM5, controller-1 has platform-specific error interrupt bits located at different offsets compared to controller-0. Signed-off-by: Thippeswamy Havalige --- drivers/pci/controller/pcie-xilinx-cpm.c | 39 +++++++++++++++++++----- 1 file changed, 32 insertions(+), 7 deletions(-) diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c b/drivers/pci/controller/pcie-xilinx-cpm.c index a0f5e1d67b04..d672f620bc4c 100644 --- a/drivers/pci/controller/pcie-xilinx-cpm.c +++ b/drivers/pci/controller/pcie-xilinx-cpm.c @@ -30,10 +30,13 @@ #define XILINX_CPM_PCIE_REG_IDRN_MASK 0x00000E3C #define XILINX_CPM_PCIE_MISC_IR_STATUS 0x00000340 #define XILINX_CPM_PCIE_MISC_IR_ENABLE 0x00000348 -#define XILINX_CPM_PCIE_MISC_IR_LOCAL BIT(1) +#define XILINX_CPM_PCIE0_MISC_IR_LOCAL BIT(1) +#define XILINX_CPM_PCIE1_MISC_IR_LOCAL BIT(2) -#define XILINX_CPM_PCIE_IR_STATUS 0x000002A0 -#define XILINX_CPM_PCIE_IR_ENABLE 0x000002A8 +#define XILINX_CPM_PCIE0_IR_STATUS 0x000002A0 +#define XILINX_CPM_PCIE1_IR_STATUS 0x000002B4 +#define XILINX_CPM_PCIE0_IR_ENABLE 0x000002A8 +#define XILINX_CPM_PCIE1_IR_ENABLE 0x000002BC #define XILINX_CPM_PCIE_IR_LOCAL BIT(0) #define IMR(x) BIT(XILINX_PCIE_INTR_ ##x) @@ -280,10 +283,17 @@ static void xilinx_cpm_pcie_event_flow(struct irq_desc *desc) pcie_write(port, val, XILINX_CPM_PCIE_REG_IDR); if (port->variant->version == CPM5) { - val = readl_relaxed(port->cpm_base + XILINX_CPM_PCIE_IR_STATUS); + val = readl_relaxed(port->cpm_base + XILINX_CPM_PCIE0_IR_STATUS); if (val) writel_relaxed(val, port->cpm_base + - XILINX_CPM_PCIE_IR_STATUS); + XILINX_CPM_PCIE0_IR_STATUS); + } + + else if (port->variant->version == CPM5_HOST1) { + val = readl_relaxed(port->cpm_base + XILINX_CPM_PCIE1_IR_STATUS); + if (val) + writel_relaxed(val, port->cpm_base + + XILINX_CPM_PCIE1_IR_STATUS); } /* @@ -483,12 +493,19 @@ static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port) * XILINX_CPM_PCIE_MISC_IR_ENABLE register is mapped to * CPM SLCR block. */ - writel(XILINX_CPM_PCIE_MISC_IR_LOCAL, + writel(XILINX_CPM_PCIE0_MISC_IR_LOCAL, port->cpm_base + XILINX_CPM_PCIE_MISC_IR_ENABLE); if (port->variant->version == CPM5) { writel(XILINX_CPM_PCIE_IR_LOCAL, - port->cpm_base + XILINX_CPM_PCIE_IR_ENABLE); + port->cpm_base + XILINX_CPM_PCIE0_IR_ENABLE); + } + + else if (port->variant->version == CPM5_HOST1) { + writel(XILINX_CPM_PCIE1_MISC_IR_LOCAL, + port->cpm_base + XILINX_CPM_PCIE_MISC_IR_ENABLE); + writel(XILINX_CPM_PCIE_IR_LOCAL, + port->cpm_base + XILINX_CPM_PCIE1_IR_ENABLE); } /* Enable the Bridge enable bit */ @@ -615,6 +632,10 @@ static const struct xilinx_cpm_variant cpm5_host = { .version = CPM5, }; +static const struct xilinx_cpm_variant cpm5_host = { + .version = CPM5_HOST1, +}; + static const struct of_device_id xilinx_cpm_pcie_of_match[] = { { .compatible = "xlnx,versal-cpm-host-1.00", @@ -624,6 +645,10 @@ static const struct of_device_id xilinx_cpm_pcie_of_match[] = { .compatible = "xlnx,versal-cpm5-host", .data = &cpm5_host, }, + { + .compatible = "xlnx,versal-cpm5-host1", + .data = &cpm5_host1, + }, {} };