From patchwork Fri Sep 6 08:32:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jin Ma X-Patchwork-Id: 1981702 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.a=rsa-sha256 header.s=default header.b=wscDw+bC; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X0TyM6lmnz1yh1 for ; Fri, 6 Sep 2024 18:33:15 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C3D71384A84F for ; Fri, 6 Sep 2024 08:33:13 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from out30-132.freemail.mail.aliyun.com (out30-132.freemail.mail.aliyun.com [115.124.30.132]) by sourceware.org (Postfix) with ESMTPS id B40CE384A84E; Fri, 6 Sep 2024 08:32:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B40CE384A84E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.alibaba.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org B40CE384A84E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=115.124.30.132 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1725611575; cv=none; b=WvrrV6o/pbFTaf8fb6/ADAjDVCJoooH2RYu5/FMFCpUsy/CrlDb2n+kfHIzqxKMf4PMTzJ6eiWjsFVnAuHyetuUsMcHF+teRVlxVWpQlhvSZxdl70u/qAz9v0Kb/fVZdOo0X9eOLczCAHawQJ0AniJvZwTB2xUEid0x8k1fEsvE= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1725611575; c=relaxed/simple; bh=9yWhDCf67Hmz0dKnlG8nQEyOyUL/N70gThBf945OQ1k=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=R/mEIGj3GnzzHRjpF2qihRVucl8w1Q16KNVpEPDyfU3va1hF1RyD6qTCeRxhmdBlP8C36Ya3Y/HXCXHwQuBkF2Vo84GBLH+Xyp274w0+pLVOSdY6YF8hNGIO7WaQ+AzmBlLJlqCdmC9J7fVHqiAULnDfA+4j5VrYV7LpunlYWmg= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1725611567; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=M9iCPKzt8YFvT3/ZP1efg89wQleYsy35Uf+vQHsOGbw=; b=wscDw+bCiMpglR3nLBTfe0u40KaQ5SnTx0UxKbwpL6GQe22QcevWUqKAZ35MyN5H/w5pVqAAOVwdyv9ko2gl3HKSVYGM8z2vAZ9lTCed5QcYF7i7l/GcnJ9Iss5SsDlsZZzUUIhcH6I7fR4ur6rmmt8ozem5v2BNv7Xc5bgHzEk= Received: from localhost.localdomain(mailfrom:jinma@linux.alibaba.com fp:SMTPD_---0WEOvijZ_1725611564) by smtp.aliyun-inc.com; Fri, 06 Sep 2024 16:32:45 +0800 From: Jin Ma To: gcc-patches@gcc.gnu.org Cc: jeffreyalaw@gmail.com, juzhe.zhong@rivai.ai, pan2.li@intel.com, kito.cheng@gmail.com, christoph.muellner@vrull.eu, shuizhuyuanluo@gmail.com, pinskia@gcc.gnu.org, xry111@xry111.site, jinma.contrib@gmail.com, Jin Ma Subject: [PATCH v3] RISC-V: Fix illegal operands "th.vsetvli zero, 0, e32, m8" for XTheadVector Date: Fri, 6 Sep 2024 16:32:32 +0800 Message-Id: <20240906083232.947-1-jinma@linux.alibaba.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20240906071036.850-1-jinma@linux.alibaba.com> References: <20240906071036.850-1-jinma@linux.alibaba.com> MIME-Version: 1.0 X-Spam-Status: No, score=-27.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY, USER_IN_DEF_DKIM_WL, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Since the THeadVector vsetvli does not support vl as an immediate, we need to convert 0 to zero when outputting asm. PR target/116592 gcc/ChangeLog: * config/riscv/thead.cc (th_asm_output_opcode): Change '0' to "zero" gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/xtheadvector/pr116592.c: New test. Reported-by: nihui Reported-by: nihui --- gcc/config/riscv/thead.cc | 4 +-- .../riscv/rvv/xtheadvector/pr116592.c | 36 +++++++++++++++++++ 2 files changed, 38 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116592.c diff --git a/gcc/config/riscv/thead.cc b/gcc/config/riscv/thead.cc index 2f1d83fbbc7f..707d91076eb5 100644 --- a/gcc/config/riscv/thead.cc +++ b/gcc/config/riscv/thead.cc @@ -960,11 +960,11 @@ th_asm_output_opcode (FILE *asm_out_file, const char *p) if (strstr (p, "zero,zero")) return "th.vsetvli\tzero,zero,e%0,%m1"; else - return "th.vsetvli\tzero,%0,e%1,%m2"; + return "th.vsetvli\tzero,%z0,e%1,%m2"; } else { - return "th.vsetvli\t%0,%1,e%2,%m3"; + return "th.vsetvli\t%z0,%z1,e%2,%m3"; } } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116592.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116592.c new file mode 100644 index 000000000000..1350f739c42a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116592.c @@ -0,0 +1,36 @@ +/* { dg-do assemble } */ +/* { dg-options "-march=rv32gc_zfh_xtheadvector -mabi=ilp32d -O2" { target { rv32 } } } */ +/* { dg-options "-march=rv64gc_zfh_xtheadvector -mabi=lp64d -O2" { target { rv64 } } } */ + +#include +#include + +static vfloat32m8_t atan2_ps(vfloat32m8_t a, vfloat32m8_t b, size_t vl) +{ + float tmpx[vl]; + float tmpy[vl]; + __riscv_vse32_v_f32m8(tmpx, a, vl); + __riscv_vse32_v_f32m8(tmpy, b, vl); + for (size_t i = 0; i < vl; i++) + { + tmpx[i] = atan2(tmpx[i], tmpy[i]); + } + return __riscv_vle32_v_f32m8(tmpx, vl); +} + +void my_atan2(const float *x, const float *y, float *out, int size) +{ + int n = size; + while (n > 0) + { + size_t vl = __riscv_vsetvl_e32m8(n); + vfloat32m8_t _x = __riscv_vle32_v_f32m8(x, vl); + vfloat32m8_t _y = __riscv_vle32_v_f32m8(y, vl); + vfloat32m8_t _out = atan2_ps(_x, _y, vl); + __riscv_vse32_v_f32m8(out, _out, vl); + n -= vl; + x += vl; + y += vl; + out += vl; + } +}