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Fri, 6 Sep 2024 07:13:01 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by CY4PEPF0000EDD7.mail.protection.outlook.com (10.167.241.203) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7918.13 via Frontend Transport; Fri, 6 Sep 2024 07:13:01 +0000 Received: from jatayu.amd.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 6 Sep 2024 02:12:59 -0500 From: Shyam Sundar S K To: Jean Delvare , Andi Shyti CC: , , Shyam Sundar S K Subject: [PATCH v3 1/5] i2c: piix4: Allow more than two algo selection for SMBus Date: Fri, 6 Sep 2024 12:41:57 +0530 Message-ID: <20240906071201.2254354-2-Shyam-sundar.S-k@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240906071201.2254354-1-Shyam-sundar.S-k@amd.com> References: <20240906071201.2254354-1-Shyam-sundar.S-k@amd.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB03.amd.com (10.181.40.144) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD7:EE_|MN2PR12MB4046:EE_ X-MS-Office365-Filtering-Correlation-Id: 467c9a72-794b-484d-d5ba-08dcce435830 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|82310400026|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Sep 2024 07:13:01.5775 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 467c9a72-794b-484d-d5ba-08dcce435830 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4046 The current implementation of the piix4 driver has a limitation in that it only supports two algorithms for the I2C adapter: - SB800 Algorithm: This is used for newer AMD chipsets. - Legacy PIIX4 Algorithm: This is used for older systems. The selection between these two algorithms is controlled by a boolean parameter in the piix4_add_adapter() function. This means that the driver can only toggle between these two options, which limits its flexibility. AMD's SMBus (System Management Bus) implementation supports additional functionalities, such as ASF (Alert Standard Format). ASF is a protocol used for system management and monitoring, which can be part of the SoC (System on Chip). To support ASF or any other future algorithms, the driver needs to be more flexible in its algorithm selection. The proposed change involves modifying the piix4_add_adapter() function to accommodate more than just two algorithm selections. Instead of using a boolean parameter to select between two algorithms, the function signature will be updated to allow for multiple algorithm options. Co-developed-by: Sanket Goswami Signed-off-by: Sanket Goswami Signed-off-by: Shyam Sundar S K --- drivers/i2c/busses/i2c-piix4.c | 30 +++++++++++++++++++++++------- 1 file changed, 23 insertions(+), 7 deletions(-) diff --git a/drivers/i2c/busses/i2c-piix4.c b/drivers/i2c/busses/i2c-piix4.c index 4e32d57ae0bf..d56083e58a2d 100644 --- a/drivers/i2c/busses/i2c-piix4.c +++ b/drivers/i2c/busses/i2c-piix4.c @@ -165,6 +165,11 @@ struct sb800_mmio_cfg { bool use_mmio; }; +enum piix4_algo { + PIIX4_SB800, + PIIX4_SMBUS, +}; + struct i2c_piix4_adapdata { unsigned short smba; @@ -173,6 +178,7 @@ struct i2c_piix4_adapdata { bool notify_imc; u8 port; /* Port number, shifted */ struct sb800_mmio_cfg mmio_cfg; + u8 algo_select; }; static int piix4_sb800_region_request(struct device *dev, @@ -929,7 +935,7 @@ static struct i2c_adapter *piix4_aux_adapter; static int piix4_adapter_count; static int piix4_add_adapter(struct pci_dev *dev, unsigned short smba, - bool sb800_main, u8 port, bool notify_imc, + enum piix4_algo algo, u8 port, bool notify_imc, u8 hw_port_nr, const char *name, struct i2c_adapter **padap) { @@ -945,8 +951,18 @@ static int piix4_add_adapter(struct pci_dev *dev, unsigned short smba, adap->owner = THIS_MODULE; adap->class = I2C_CLASS_HWMON; - adap->algo = sb800_main ? &piix4_smbus_algorithm_sb800 - : &smbus_algorithm; + + switch (algo) { + case PIIX4_SMBUS: + adap->algo = &smbus_algorithm; + break; + case PIIX4_SB800: + adap->algo = &piix4_smbus_algorithm_sb800; + break; + default: + dev_err(&dev->dev, "Unsupported SMBus algorithm\n"); + return -EINVAL; + } adapdata = kzalloc(sizeof(*adapdata), GFP_KERNEL); if (adapdata == NULL) { @@ -957,7 +973,7 @@ static int piix4_add_adapter(struct pci_dev *dev, unsigned short smba, adapdata->mmio_cfg.use_mmio = piix4_sb800_use_mmio(dev); adapdata->smba = smba; - adapdata->sb800_main = sb800_main; + adapdata->algo_select = algo; adapdata->port = port << piix4_port_shift_sb800; adapdata->notify_imc = notify_imc; @@ -1013,7 +1029,7 @@ static int piix4_add_adapters_sb800(struct pci_dev *dev, unsigned short smba, for (port = 0; port < piix4_adapter_count; port++) { u8 hw_port_nr = port == 0 ? 0 : port + 1; - retval = piix4_add_adapter(dev, smba, true, port, notify_imc, + retval = piix4_add_adapter(dev, smba, PIIX4_SB800, port, notify_imc, hw_port_nr, piix4_main_port_names_sb800[port], &piix4_main_adapters[port]); @@ -1085,7 +1101,7 @@ static int piix4_probe(struct pci_dev *dev, const struct pci_device_id *id) return retval; /* Try to register main SMBus adapter, give up if we can't */ - retval = piix4_add_adapter(dev, retval, false, 0, false, 0, + retval = piix4_add_adapter(dev, retval, PIIX4_SMBUS, 0, false, 0, "", &piix4_main_adapters[0]); if (retval < 0) return retval; @@ -1114,7 +1130,7 @@ static int piix4_probe(struct pci_dev *dev, const struct pci_device_id *id) if (retval > 0) { /* Try to add the aux adapter if it exists, * piix4_add_adapter will clean up if this fails */ - piix4_add_adapter(dev, retval, false, 0, false, 1, + piix4_add_adapter(dev, retval, PIIX4_SMBUS, 0, false, 1, is_sb800 ? piix4_aux_port_name_sb800 : "", &piix4_aux_adapter); } From patchwork Fri Sep 6 07:11:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shyam Sundar S K X-Patchwork-Id: 1981649 X-Patchwork-Delegate: andi.shyti@kernel.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by CY4PEPF0000EDD1.mail.protection.outlook.com (10.167.241.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7918.13 via Frontend Transport; Fri, 6 Sep 2024 07:13:04 +0000 Received: from jatayu.amd.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 6 Sep 2024 02:13:01 -0500 From: Shyam Sundar S K To: Jean Delvare , Andi Shyti CC: , , Shyam Sundar S K Subject: [PATCH v3 2/5] i2c: piix4: Add i2c_algorithm operations to support AMD ASF with SMBus Date: Fri, 6 Sep 2024 12:41:58 +0530 Message-ID: <20240906071201.2254354-3-Shyam-sundar.S-k@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240906071201.2254354-1-Shyam-sundar.S-k@amd.com> References: <20240906071201.2254354-1-Shyam-sundar.S-k@amd.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB03.amd.com (10.181.40.144) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD1:EE_|CY5PR12MB6252:EE_ X-MS-Office365-Filtering-Correlation-Id: 9578bb0d-ff96-49a6-1da6-08dcce4359cc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Sep 2024 07:13:04.2728 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9578bb0d-ff96-49a6-1da6-08dcce4359cc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD1.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6252 Implement the i2c_algorithm operations to enable support for AMD ASF (Alert Standard Format) with SMBus. This enhancement includes: - Adding functionality to identify and select the supported ASF functions. - Implementing mechanisms for registering and deregistering I2C slave devices. - Providing support for data transfer operations over ASF. These changes will extend the piix4 driver to accommodate the additional capabilities provided by AMD's ASF Controller. Additionally, include a 'select' Kconfig entry for CONFIG_I2C_PIIX4, as the current patch utilizes reg_slave and unreg_slave callbacks, which are controlled by IS_ENABLED(CONFIG_I2C_SLAVE). Co-developed-by: Sanket Goswami Signed-off-by: Sanket Goswami Signed-off-by: Shyam Sundar S K --- drivers/i2c/busses/Kconfig | 1 + drivers/i2c/busses/i2c-piix4.c | 184 +++++++++++++++++++++++++++++++++ 2 files changed, 185 insertions(+) diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index a22f9125322a..10ad839bf4a2 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -197,6 +197,7 @@ config I2C_PIIX4 tristate "Intel PIIX4 and compatible (ATI/AMD/Serverworks/Broadcom/SMSC)" depends on PCI && HAS_IOPORT select I2C_SMBUS + select I2C_SLAVE help If you say yes to this option, support will be included for the Intel PIIX4 family of mainboard I2C interfaces. Specifically, the following diff --git a/drivers/i2c/busses/i2c-piix4.c b/drivers/i2c/busses/i2c-piix4.c index d56083e58a2d..003cb04312cf 100644 --- a/drivers/i2c/busses/i2c-piix4.c +++ b/drivers/i2c/busses/i2c-piix4.c @@ -50,6 +50,22 @@ #define SMBSLVEVT (0xA + piix4_smba) #define SMBSLVDAT (0xC + piix4_smba) +/* SB800 ASF register bits */ +#define SB800_ASF_SLV_LISTN 0 +#define SB800_ASF_SLV_INTR 1 +#define SB800_ASF_SLV_RST 4 +#define SB800_ASF_PEC_SP 5 +#define SB800_ASF_DATA_EN 7 +#define SB800_ASF_MSTR_EN 16 +#define SB800_ASF_CLK_EN 17 + +/* SB800 ASF address offsets */ +#define ASFLISADDR (9 + piix4_smba) +#define ASFSTA (0xA + piix4_smba) +#define ASFSLVSTA (0xD + piix4_smba) +#define ASFDATABNKSEL (0x13 + piix4_smba) +#define ASFSLVEN (0x15 + piix4_smba) + /* count for request_region */ #define SMBIOSIZE 9 @@ -101,6 +117,7 @@ #define SB800_PIIX4_FCH_PM_ADDR 0xFED80300 #define SB800_PIIX4_FCH_PM_SIZE 8 +#define SB800_ASF_BLOCK_MAX_BYTES 72 /* insmod parameters */ @@ -168,6 +185,7 @@ struct sb800_mmio_cfg { enum piix4_algo { PIIX4_SB800, PIIX4_SMBUS, + SMBUS_ASF, }; struct i2c_piix4_adapdata { @@ -179,6 +197,7 @@ struct i2c_piix4_adapdata { u8 port; /* Port number, shifted */ struct sb800_mmio_cfg mmio_cfg; u8 algo_select; + struct i2c_client *slave; }; static int piix4_sb800_region_request(struct device *dev, @@ -887,6 +906,168 @@ static s32 piix4_access_sb800(struct i2c_adapter *adap, u16 addr, return retval; } +static void sb800_asf_update_bits(unsigned short piix4_smba, u8 bit, unsigned long offset, bool set) +{ + unsigned long reg; + + reg = inb_p(offset); + if (set) + set_bit(bit, ®); + else + clear_bit(bit, ®); + outb_p(reg, offset); +} + +static void sb800_asf_update_bytes(struct i2c_piix4_adapdata *adap, u8 bit, bool set) +{ + unsigned long reg; + + reg = ioread32(adap->mmio_cfg.addr); + if (set) + set_bit(bit, ®); + else + clear_bit(bit, ®); + iowrite32(reg, adap->mmio_cfg.addr); +} + +static void sb800_asf_setup_slave(struct i2c_piix4_adapdata *adap) +{ + unsigned short piix4_smba = adap->smba; + + /* Reset both host and slave before setting up */ + outb_p(0, SMBHSTSTS); + outb_p(0, ASFSLVSTA); + outb_p(0, ASFSTA); + + /* Update slave address */ + sb800_asf_update_bits(piix4_smba, SB800_ASF_SLV_LISTN, ASFLISADDR, true); + /* Enable slave and set the clock */ + sb800_asf_update_bytes(adap, SB800_ASF_MSTR_EN, false); + sb800_asf_update_bytes(adap, SB800_ASF_CLK_EN, true); + /* Enable slave interrupt */ + sb800_asf_update_bits(piix4_smba, SB800_ASF_SLV_INTR, ASFSLVEN, true); + sb800_asf_update_bits(piix4_smba, SB800_ASF_SLV_RST, ASFSLVEN, false); + /* Enable PEC and PEC append */ + sb800_asf_update_bits(piix4_smba, SB800_ASF_DATA_EN, SMBHSTCNT, true); + sb800_asf_update_bits(piix4_smba, SB800_ASF_PEC_SP, SMBHSTCNT, true); +} + +static s32 sb800_asf_access(struct i2c_adapter *adap, u16 addr, u8 command, u8 *data) +{ + struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap); + unsigned short piix4_smba = adapdata->smba; + u8 len; + int i; + + outb_p((addr << 1), SMBHSTADD); + outb_p(command, SMBHSTCMD); + len = data[0]; + if (len == 0 || len > SB800_ASF_BLOCK_MAX_BYTES) + return -EINVAL; + + outb_p(len, SMBHSTDAT0); + inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */ + for (i = 1; i <= len; i++) + outb_p(data[i], SMBBLKDAT); + + outb_p(PIIX4_BLOCK_DATA, SMBHSTCNT); + /* Enable PEC and PEC append */ + sb800_asf_update_bits(piix4_smba, SB800_ASF_DATA_EN, SMBHSTCNT, true); + sb800_asf_update_bits(piix4_smba, SB800_ASF_PEC_SP, SMBHSTCNT, true); + + return piix4_transaction(adap); +} + +static int sb800_asf_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) +{ + struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap); + unsigned short piix4_smba = adapdata->smba; + u8 asf_data[SB800_ASF_BLOCK_MAX_BYTES]; + struct i2c_msg *dev_msgs = msgs; + u8 prev_port; + int ret; + + if (msgs->flags & I2C_M_RD) { + dev_err(&adap->dev, "Read not supported\n"); + return -EOPNOTSUPP; + } + + /* Exclude the receive header and PEC */ + if (msgs->len > SB800_ASF_BLOCK_MAX_BYTES - 3) { + dev_err(&adap->dev, "ASF max message length exceeded\n"); + return -EOPNOTSUPP; + } + + asf_data[0] = dev_msgs->len; + memcpy(asf_data + 1, dev_msgs[0].buf, dev_msgs->len); + + ret = piix4_sb800_region_request(&adap->dev, &adapdata->mmio_cfg); + if (ret) + return ret; + + sb800_asf_update_bits(piix4_smba, SB800_ASF_SLV_RST, ASFSLVEN, true); + sb800_asf_update_bits(piix4_smba, SB800_ASF_SLV_LISTN, ASFLISADDR, false); + /* Clear ASF slave status */ + outb_p(0, ASFSLVSTA); + + /* Enable ASF SMBus master function */ + sb800_asf_update_bytes(adapdata, SB800_ASF_MSTR_EN, true); + prev_port = piix4_sb800_port_sel(adapdata->port, &adapdata->mmio_cfg); + ret = sb800_asf_access(adap, msgs->addr, msgs[0].buf[0], asf_data); + piix4_sb800_port_sel(prev_port, &adapdata->mmio_cfg); + sb800_asf_setup_slave(adapdata); + piix4_sb800_region_release(&adap->dev, &adapdata->mmio_cfg); + return ret; +} + +static int sb800_asf_reg_slave(struct i2c_client *slave) +{ + struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(slave->adapter); + unsigned short piix4_smba = adapdata->smba; + int ret; + u8 reg; + + if (adapdata->slave) + return -EBUSY; + + ret = piix4_sb800_region_request(&slave->dev, &adapdata->mmio_cfg); + if (ret) + return ret; + + reg = (slave->addr << 1) | BIT(0); + outb_p(reg, ASFLISADDR); + + sb800_asf_setup_slave(adapdata); + adapdata->slave = slave; + sb800_asf_update_bits(piix4_smba, SB800_ASF_DATA_EN, ASFDATABNKSEL, false); + piix4_sb800_region_release(&slave->dev, &adapdata->mmio_cfg); + return 0; +} + +static int sb800_asf_unreg_slave(struct i2c_client *slave) +{ + struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(slave->adapter); + unsigned short piix4_smba = adapdata->smba; + + sb800_asf_update_bits(piix4_smba, SB800_ASF_SLV_INTR, ASFSLVEN, false); + sb800_asf_update_bits(piix4_smba, SB800_ASF_SLV_RST, ASFSLVEN, true); + adapdata->slave = NULL; + return 0; +} + +static u32 sb800_asf_func(struct i2c_adapter *adapter) +{ + return I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BYTE | + I2C_FUNC_SLAVE | I2C_FUNC_SMBUS_WRITE_BLOCK_DATA | I2C_FUNC_SMBUS_PEC; +} + +static const struct i2c_algorithm sb800_asf_smbus_algorithm = { + .master_xfer = sb800_asf_xfer, + .reg_slave = sb800_asf_reg_slave, + .unreg_slave = sb800_asf_unreg_slave, + .functionality = sb800_asf_func, +}; + static u32 piix4_func(struct i2c_adapter *adapter) { return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | @@ -959,6 +1140,9 @@ static int piix4_add_adapter(struct pci_dev *dev, unsigned short smba, case PIIX4_SB800: adap->algo = &piix4_smbus_algorithm_sb800; break; + case SMBUS_ASF: + adap->algo = &sb800_asf_smbus_algorithm; + break; default: dev_err(&dev->dev, "Unsupported SMBus algorithm\n"); return -EINVAL; From patchwork Fri Sep 6 07:11:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shyam Sundar S K X-Patchwork-Id: 1981650 X-Patchwork-Delegate: andi.shyti@kernel.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=amd.com header.i=@amd.com header.a=rsa-sha256 header.s=selector1 header.b=WI1kCoo9; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by CY4PEPF0000EDD4.mail.protection.outlook.com (10.167.241.200) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7918.13 via Frontend Transport; Fri, 6 Sep 2024 07:13:07 +0000 Received: from jatayu.amd.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 6 Sep 2024 02:13:04 -0500 From: Shyam Sundar S K To: Jean Delvare , Andi Shyti CC: , , Shyam Sundar S K , Andy Shevchenko Subject: [PATCH v3 3/5] i2c: piix4: Add ACPI support for ASF SMBus device Date: Fri, 6 Sep 2024 12:41:59 +0530 Message-ID: <20240906071201.2254354-4-Shyam-sundar.S-k@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240906071201.2254354-1-Shyam-sundar.S-k@amd.com> References: <20240906071201.2254354-1-Shyam-sundar.S-k@amd.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB03.amd.com (10.181.40.144) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD4:EE_|SJ0PR12MB7475:EE_ X-MS-Office365-Filtering-Correlation-Id: 60a56ca9-9477-4c79-65ba-08dcce435b97 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|82310400026|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Sep 2024 07:13:07.2672 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 60a56ca9-9477-4c79-65ba-08dcce435b97 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB7475 The AMD ASF controller is presented to the operating system as an ACPI device. The piix4 driver can obtain the ASF handle through ACPI to retrieve information about the ASF controller's attributes, such as the ASF address space and interrupt number, and to handle ASF interrupts. Currently, the piix4 driver assumes that a specific port address is designated for AUX operations. However, with the introduction of ASF, the same port address may also be used by the ASF controller. Therefore, a check needs to be added to ensure that if ASF is advertised and enabled in ACPI, the AUX port is not set up. Additionally, include a 'depends on X86' Kconfig entry for CONFIG_I2C_PIIX4, as the current patch utilizes acpi_dev_get_resources(), which is compiled only when CONFIG_ACPI is enabled, and CONFIG_ACPI depends on CONFIG_X86. Co-developed-by: Sanket Goswami Signed-off-by: Sanket Goswami Signed-off-by: Shyam Sundar S K --- Cc: Andy Shevchenko drivers/i2c/busses/Kconfig | 2 +- drivers/i2c/busses/i2c-piix4.c | 167 ++++++++++++++++++++++++++++++++- 2 files changed, 167 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 10ad839bf4a2..7d080a009ee3 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -195,7 +195,7 @@ config I2C_ISMT config I2C_PIIX4 tristate "Intel PIIX4 and compatible (ATI/AMD/Serverworks/Broadcom/SMSC)" - depends on PCI && HAS_IOPORT + depends on PCI && HAS_IOPORT && X86 select I2C_SMBUS select I2C_SLAVE help diff --git a/drivers/i2c/busses/i2c-piix4.c b/drivers/i2c/busses/i2c-piix4.c index 003cb04312cf..2bf9611d864a 100644 --- a/drivers/i2c/busses/i2c-piix4.c +++ b/drivers/i2c/busses/i2c-piix4.c @@ -60,9 +60,12 @@ #define SB800_ASF_CLK_EN 17 /* SB800 ASF address offsets */ +#define ASFINDEX (7 + piix4_smba) #define ASFLISADDR (9 + piix4_smba) #define ASFSTA (0xA + piix4_smba) #define ASFSLVSTA (0xD + piix4_smba) +#define ASFDATARWPTR (0x11 + piix4_smba) +#define ASFSETDATARDPTR (0x12 + piix4_smba) #define ASFDATABNKSEL (0x13 + piix4_smba) #define ASFSLVEN (0x15 + piix4_smba) @@ -118,6 +121,8 @@ #define SB800_PIIX4_FCH_PM_ADDR 0xFED80300 #define SB800_PIIX4_FCH_PM_SIZE 8 #define SB800_ASF_BLOCK_MAX_BYTES 72 +#define SB800_ASF_ERROR_STATUS 0xE +#define SB800_ASF_ACPI_PATH "\\_SB.ASFC" /* insmod parameters */ @@ -182,6 +187,11 @@ struct sb800_mmio_cfg { bool use_mmio; }; +struct sb800_asf_data { + unsigned short addr; + int irq; +}; + enum piix4_algo { PIIX4_SB800, PIIX4_SMBUS, @@ -194,10 +204,12 @@ struct i2c_piix4_adapdata { /* SB800 */ bool sb800_main; bool notify_imc; + bool is_asf; u8 port; /* Port number, shifted */ struct sb800_mmio_cfg mmio_cfg; u8 algo_select; struct i2c_client *slave; + struct delayed_work work_buf; }; static int piix4_sb800_region_request(struct device *dev, @@ -906,6 +918,67 @@ static s32 piix4_access_sb800(struct i2c_adapter *adap, u16 addr, return retval; } +static void sb800_asf_process_slave(struct work_struct *work) +{ + struct i2c_piix4_adapdata *adapdata = + container_of(work, struct i2c_piix4_adapdata, work_buf.work); + unsigned short piix4_smba = adapdata->smba; + u8 data[SB800_ASF_BLOCK_MAX_BYTES]; + u8 bank, reg, cmd = 0; + u8 len, val = 0; + int i; + + /* Read slave status register */ + reg = inb_p(ASFSLVSTA); + + /* Check if no error bits are set in slave status register */ + if (reg & SB800_ASF_ERROR_STATUS) { + /* Set bank as full */ + reg = reg | GENMASK(3, 2); + outb_p(reg, ASFDATABNKSEL); + } else { + /* Read data bank */ + reg = inb_p(ASFDATABNKSEL); + bank = (reg & BIT(3)) >> 3; + + /* Set read data bank */ + if (bank) { + reg = reg | BIT(4); + reg = reg & ~BIT(3); + } else { + reg = reg & ~BIT(4); + reg = reg & ~BIT(2); + } + + /* Read command register */ + outb_p(reg, ASFDATABNKSEL); + cmd = inb_p(ASFINDEX); + len = inb_p(ASFDATARWPTR); + for (i = 0; i < len; i++) + data[i] = inb_p(ASFINDEX); + + /* Clear data bank status */ + if (bank) { + reg = reg | BIT(3); + outb_p(reg, ASFDATABNKSEL); + } else { + reg = reg | BIT(2); + outb_p(reg, ASFDATABNKSEL); + } + } + + outb_p(0, ASFSETDATARDPTR); + if (cmd & BIT(0)) + return; + + i2c_slave_event(adapdata->slave, I2C_SLAVE_WRITE_REQUESTED, &val); + for (i = 0; i < len; i++) { + val = data[i]; + i2c_slave_event(adapdata->slave, I2C_SLAVE_WRITE_RECEIVED, &val); + } + i2c_slave_event(adapdata->slave, I2C_SLAVE_STOP, &val); +} + static void sb800_asf_update_bits(unsigned short piix4_smba, u8 bit, unsigned long offset, bool set) { unsigned long reg; @@ -1195,6 +1268,88 @@ static int piix4_add_adapter(struct pci_dev *dev, unsigned short smba, return 0; } +static irqreturn_t sb800_asf_irq_handler(int irq, void *ptr) +{ + struct i2c_piix4_adapdata *adapdata = ptr; + unsigned short piix4_smba = adapdata->smba; + u8 slave_int = inb_p(ASFSTA); + + if (slave_int & BIT(6)) { + /* Slave Interrupt */ + outb_p(slave_int | BIT(6), ASFSTA); + schedule_delayed_work(&adapdata->work_buf, HZ); + } else { + /* Master Interrupt */ + sb800_asf_update_bits(piix4_smba, SB800_ASF_SLV_INTR, SMBHSTSTS, true); + } + + return IRQ_HANDLED; +} + +static int sb800_asf_add_adap(struct pci_dev *dev) +{ + struct i2c_piix4_adapdata *adapdata; + struct resource_entry *rentry; + struct sb800_asf_data data; + struct list_head res_list; + struct acpi_device *adev; + acpi_status status; + acpi_handle handle; + int ret; + + status = acpi_get_handle(NULL, SB800_ASF_ACPI_PATH, &handle); + if (ACPI_FAILURE(status)) + return -ENODEV; + + adev = acpi_fetch_acpi_dev(handle); + if (!adev) + return -ENODEV; + + INIT_LIST_HEAD(&res_list); + ret = acpi_dev_get_resources(adev, &res_list, NULL, NULL); + if (ret < 0) { + dev_err(&dev->dev, "Error getting ASF ACPI resource: %d\n", ret); + return ret; + } + + list_for_each_entry(rentry, &res_list, node) { + switch (resource_type(rentry->res)) { + case IORESOURCE_IO: + data.addr = rentry->res->start; + break; + case IORESOURCE_IRQ: + data.irq = rentry->res->start; + break; + default: + dev_warn(&adev->dev, "Invalid ASF resource\n"); + break; + } + } + + acpi_dev_free_resource_list(&res_list); + ret = piix4_add_adapter(dev, data.addr, SMBUS_ASF, piix4_adapter_count, false, 0, + piix4_main_port_names_sb800[piix4_adapter_count], + &piix4_main_adapters[piix4_adapter_count]); + if (ret) { + dev_err(&dev->dev, "Failed to add ASF adapter: %d\n", ret); + return -ENODEV; + } + + adapdata = i2c_get_adapdata(piix4_main_adapters[piix4_adapter_count]); + ret = devm_request_irq(&dev->dev, data.irq, sb800_asf_irq_handler, IRQF_SHARED, + "sb800_smbus_asf", adapdata); + if (ret) { + dev_err(&dev->dev, "Unable to request irq: %d for use\n", data.irq); + return ret; + } + + INIT_DELAYED_WORK(&adapdata->work_buf, sb800_asf_process_slave); + adapdata->is_asf = true; + /* Increment the adapter count by 1 as ASF is added to the list */ + piix4_adapter_count++; + return 1; +} + static int piix4_add_adapters_sb800(struct pci_dev *dev, unsigned short smba, bool notify_imc) { @@ -1243,6 +1398,7 @@ static int piix4_probe(struct pci_dev *dev, const struct pci_device_id *id) { int retval; bool is_sb800 = false; + bool is_asf = false; if ((dev->vendor == PCI_VENDOR_ID_ATI && dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS && @@ -1279,6 +1435,10 @@ static int piix4_probe(struct pci_dev *dev, const struct pci_device_id *id) retval = piix4_add_adapters_sb800(dev, retval, notify_imc); if (retval < 0) return retval; + + /* Check if ASF is enabled in SB800 */ + if (sb800_asf_add_adap(dev)) + is_asf = true; } else { retval = piix4_setup(dev, id); if (retval < 0) @@ -1308,7 +1468,9 @@ static int piix4_probe(struct pci_dev *dev, const struct pci_device_id *id) if (dev->vendor == PCI_VENDOR_ID_AMD && (dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS || dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS)) { - retval = piix4_setup_sb800(dev, id, 1); + /* Do not setup AUX port if ASF is enabled */ + if (!is_asf) + retval = piix4_setup_sb800(dev, id, 1); } if (retval > 0) { @@ -1326,6 +1488,9 @@ static void piix4_adap_remove(struct i2c_adapter *adap) { struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap); + if (adapdata->is_asf) + cancel_delayed_work_sync(&adapdata->work_buf); + if (adapdata->smba) { i2c_del_adapter(adap); if (adapdata->port == (0 << piix4_port_shift_sb800)) From patchwork Fri Sep 6 07:12:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shyam Sundar S K X-Patchwork-Id: 1981651 X-Patchwork-Delegate: andi.shyti@kernel.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=amd.com header.i=@amd.com header.a=rsa-sha256 header.s=selector1 header.b=x2TIgsT2; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by CY4PEPF0000EDD6.mail.protection.outlook.com (10.167.241.202) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7918.13 via Frontend Transport; Fri, 6 Sep 2024 07:13:09 +0000 Received: from jatayu.amd.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 6 Sep 2024 02:13:06 -0500 From: Shyam Sundar S K To: Jean Delvare , Andi Shyti CC: , , Shyam Sundar S K Subject: [PATCH v3 4/5] i2c: piix4: Adjust the SMBus debug message Date: Fri, 6 Sep 2024 12:42:00 +0530 Message-ID: <20240906071201.2254354-5-Shyam-sundar.S-k@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240906071201.2254354-1-Shyam-sundar.S-k@amd.com> References: <20240906071201.2254354-1-Shyam-sundar.S-k@amd.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB03.amd.com (10.181.40.144) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD6:EE_|IA0PR12MB8301:EE_ X-MS-Office365-Filtering-Correlation-Id: 39d07886-febe-4229-65d7-08dcce435cd5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700013; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Sep 2024 07:13:09.3668 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 39d07886-febe-4229-65d7-08dcce435cd5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD6.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8301 With the addition of ASF, the current adapter information must now correctly print the SMBus node details, whether it pertains to PIIX4 or ASF. Update the driver to reflect this change accordingly. Co-developed-by: Sanket Goswami Signed-off-by: Sanket Goswami Signed-off-by: Shyam Sundar S K --- drivers/i2c/busses/i2c-piix4.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-piix4.c b/drivers/i2c/busses/i2c-piix4.c index 2bf9611d864a..6abbaeaf2810 100644 --- a/drivers/i2c/busses/i2c-piix4.c +++ b/drivers/i2c/busses/i2c-piix4.c @@ -1195,6 +1195,7 @@ static int piix4_add_adapter(struct pci_dev *dev, unsigned short smba, { struct i2c_adapter *adap; struct i2c_piix4_adapdata *adapdata; + const char *node = "PIIX4"; int retval; adap = kzalloc(sizeof(*adap), GFP_KERNEL); @@ -1214,6 +1215,7 @@ static int piix4_add_adapter(struct pci_dev *dev, unsigned short smba, adap->algo = &piix4_smbus_algorithm_sb800; break; case SMBUS_ASF: + node = "ASF"; adap->algo = &sb800_asf_smbus_algorithm; break; default: @@ -1244,7 +1246,7 @@ static int piix4_add_adapter(struct pci_dev *dev, unsigned short smba, } snprintf(adap->name, sizeof(adap->name), - "SMBus PIIX4 adapter%s at %04x", name, smba); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Sep 2024 07:13:11.5619 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8e5b8dee-d410-471b-57d2-08dcce435e24 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9452 To ensure successive interrupts upon packet reception, it is necessary to clear the remote IRR bit by writing the interrupt number to the EOI register. The base address for this operation is provided by the BIOS and retrieved by the driver by traversing the ASF object's namespace. Co-developed-by: Sanket Goswami Signed-off-by: Sanket Goswami Signed-off-by: Shyam Sundar S K --- drivers/i2c/busses/i2c-piix4.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/i2c/busses/i2c-piix4.c b/drivers/i2c/busses/i2c-piix4.c index 6abbaeaf2810..bf79b2280613 100644 --- a/drivers/i2c/busses/i2c-piix4.c +++ b/drivers/i2c/busses/i2c-piix4.c @@ -188,6 +188,8 @@ struct sb800_mmio_cfg { }; struct sb800_asf_data { + resource_size_t eoi_addr; + resource_size_t eoi_sz; unsigned short addr; int irq; }; @@ -199,6 +201,7 @@ enum piix4_algo { }; struct i2c_piix4_adapdata { + void __iomem *eoi_base; unsigned short smba; /* SB800 */ @@ -1285,6 +1288,7 @@ static irqreturn_t sb800_asf_irq_handler(int irq, void *ptr) sb800_asf_update_bits(piix4_smba, SB800_ASF_SLV_INTR, SMBHSTSTS, true); } + iowrite32(irq, adapdata->eoi_base); return IRQ_HANDLED; } @@ -1322,6 +1326,10 @@ static int sb800_asf_add_adap(struct pci_dev *dev) case IORESOURCE_IRQ: data.irq = rentry->res->start; break; + case IORESOURCE_MEM: + data.eoi_addr = rentry->res->start; + data.eoi_sz = resource_size(rentry->res); + break; default: dev_warn(&adev->dev, "Invalid ASF resource\n"); break; @@ -1346,6 +1354,9 @@ static int sb800_asf_add_adap(struct pci_dev *dev) } INIT_DELAYED_WORK(&adapdata->work_buf, sb800_asf_process_slave); + adapdata->eoi_base = devm_ioremap(&dev->dev, data.eoi_addr, data.eoi_sz); + if (!adapdata->eoi_base) + return -ENOMEM; adapdata->is_asf = true; /* Increment the adapter count by 1 as ASF is added to the list */ piix4_adapter_count++;